Apr 5, 2010 - -DSC 2GB. -GAME 1GB. -Note book 2GB. -Camcorder 8GB. E-Book. Telematics. DMB phone. Mobile & Consumer.
NAND Flash memory Samsung Electronics, co., Ltd Flash design team 2010. 05. 07
Kihwan Choi
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Contents Introduction Flash memory 101 Basic operations Current issues & approach In the near future
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NAND Flash Application DMB phone E-Book DVD player Telematics
SSD
PMP
Portable Internet
Mobile MP3 DSC Game PDA Compute r
Serve r
~1999
2002
PC Oriented
Digital TV Digital Camcorder
100GB
Mobile & Consumer 20GB Oriented --Smart Smart phone 1GB --MP3 MP3 Player 4GB --UFD UFD 2GB --DSC DSC 2GB --GAME GAME 1GB --Note Note book 2GB 1GB --Camcorder Camcorder 8GB --Smart Smart phone 32MB --MP3 MP3 Player 128MB --UFD UFD 256MB --DSC DSC 128MB --Note Note book 512MB
2010
2007
2006
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“Flash memory” in Wikipedia Flash memory is a non-volatile computer storage technology that can be electrically erased and reprogrammed. Flash memory offers fast read access times (although not as fast as volatile DRAM memory used for main memory in PCs) and better kinetic shock resistance than hard disks. Flash memory (both NOR and NAND types) was invented by Dr. Fujio Masuoka while working for Toshiba circa 1980. According to Toshiba, the name "flash" was suggested by Dr. Masuoka's colleague, Mr. Shoji Ariizumi, because the erasure process of the memory contents reminded him of the flash of a camera. NAND flash also uses floating-gate transistors, but they are connected in a way that resembles a NAND gate : several transistors are connected in series, and only if all word lines are pulled high (above the transistors' VT) is the bit line pulled low. - 4/48 ELECTRONICS
“Flash memory” in Wikipedia To read, most of the word lines are pulled up above the VT of a programmed bit, while one of them is pulled up to just over the VT of an erased bit. The series group will conduct (and pull the bit line low) if the selected bit has not been programmed. NAND flash uses tunnel injection for writing and tunnel release for erasing. One limitation of flash memory is that although it can be read or programmed a byte or a word at a time in a random access fashion, it must be erased a "block" at a time. Another limitation is that flash memory has a finite number of erase-write cycles. Most commercially available flash products are guaranteed to withstand around 100,000 write-erase-cycles, before the wear begins to deteriorate the integrity of the storage - 5/48 ELECTRONICS
“Flash memory” in Wikipedia Technology scaling down Reference: EETimes article on NAND scaling, 3/22/2010
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Major players
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Now in the market … Intel, Micron and IMFT announce world’s first 25-nm NAND technology February 2, 2010, By Sanjeev Ramachandran in Hardware The NAND flash production scene has received a shot in the arm with Intel Corporation and Micron Technology making it public that the world’s first 25-nanometer (nm) NAND technology is now on stream. Significantly enough, the 25nm process is the smallest NAND technology as well as the smallest semiconductor technology in the world
Hynix Develops 26nm NAND Flash Memory Tuesday, February 09, 2010 South Korea's Hynix Semiconductor Inc., the world's second-largest memory chipmaker, said Tuesday that it has developed a 26nanometer based NAND flash memory chip. The company is the world's second flash memory maker to apply the below 30-nanometer technology. Mass production of the new memory will start in in July.
Toshiba readies sub-25nm flash memory chip production By Jose Vilches, TechSpot.com Published: April 5, 2010, 12:14 PM EST The company produces 32nm and 43nm memory chips, but the plan is to begin production on "sub-25nm" chips that would enable larger storage capacities to be shoved into the same form factors that we use today. Toshiba will begin output of NAND chips with circuitry widths in the upper 20 nanometre range soon, while production of chips with circuitry widths in the lower 20 nanometres is slated to start as early as 2012.
Samsung pioneers 20-nm NAND flash memory technology April 19, 2010, By Thomas Antony in Storage Right on the heels of Toshiba’s announcement to start on sub-25nm flash memory, Samsung today announced the industry’s first production of 20 nanometer class NAND chips for use in SD cards. Samsung’s 20nm MLC 32-gigabit NAND chips are sampling now for use in embedded storage and SD memory cards ranging from 4GB to 64GB. This is a significant step forward for Samsung who started its 30nm production just one year ago. The new class of memory chips will allow for higher-density in storage, lower manufacturing costs and 50% higher productivity than 30nm technology. - 8/48 ELECTRONICS
Flash memory 101
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Flash memory cell vs. MOSFET Flash cell has a charge storage layer such that Vth of a cell can be changed memorize information
G
Charge storage
G S
F/G
n
D
S
D
n
n
n
p
p
B
B
Flash cell
MOSFET - 10/48 ELECTRONICS
Flash memory operation Write & read binary data to a flash cell data ‘0’ ‘OFF’ state (program) data ‘1’ ‘ON’ state (erase)
MOS Transistor Vg(Vg>Vth1)
ON No. of cells
Read Vs(0V)
Vth1
Program
Vd(>0V) Ids1(>0)
Erase Vg(Vg0V) Ids2(=0)
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Flash memory cell structure Cell Vth changes depending on the amount of F/G charge electrons can be injected(ejected) into(out of) the F/G through Tox with electric field across Tox
B/L Metal Dielectric : ONO C/G(W/L)
Charge Storage Node
F/G(F-Poly)
Tunnel Ox Drain
Source
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NAND vs. NOR NAND Truth table
NOR
A
B
C
A
B
C
0
0
0
0
0
1
0
1
0
0
1
0
1
0
0
1
0
0
1
1
1
1
1
0
A
A
Logic gate
C
C
B
circuit
B
A
B
A
C
B C
A
Flash
A
B
B
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Features : NAND vs. NOR
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Write methods in Flash memory Fowler-Nordheim Tunneling
Hot Electron Injection
Program in NOR Flash Impact ionization at drain side
Program/Erase in NAND Flash Erase in NOR Flash
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NAND Flash : Program & Erase
Vcg = 18 V
0V
e e e e
Vcg = 0V
float
0V
e e e e
float
Vsub = 0V
Vsub = 20V
Program F-N Tunneling
Erase F-N Tunneling
Off cell (Solid-0)
On cell (Solid-1) - 16/48 ELECTRONICS
Coupling ratio Vfg = Vcg × αcg
C/G CONO CS Source
F/G CB
αcg = CD
CONO (CD+CS+CB+CONO)
αcg : Coupling Ratio
Drain
(From Q=CV and Charge Conservation Law)
For fast programming, high Vfg is required, i.e. either high Vcg or large αcg
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NAND Flash cell structure BL
DC
Active Gate
SSL
SSL
WL
ONO
F-Poly
WL Tunnel Ox WL Direction F-Poly Gate
ONO
F-Poly
GSL GSL CSL
PP-Well
CSL Schematic
Tunnel Ox
BL Direction Top View
Vertical View
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Terms in NAND Flash – string, page, block string : minimum cell array element
page : program unit
block : erase unit
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NAND Flash chip architecture High density & simple architecture (cell efficiency > 65%) Control I/O Pad
Memory Array
Memory Array
Memory Array
Memory Array
WL Decoder & Driver
Block = 128-page (2Mb~4Mb) SLC : 64-page MLC : 128-page
Page Driver & Buffer (2KB~4KB) Peripheral & Charge Pump Data I/O Pad Samsung 63nm 8Gb MLC NAND - 20/48 ELECTRONICS
Functional block diagram of NAND Flash
A12~A30
A0~A11
X D E C.
X-Buffers Latches & Decoders Y-Buffers Latches & Decoders
Cell Array
Data Register & S/A Y-Gating
Command
Command Register
CE RE WE
VCC VSS
I/O Buffers & Latches
Control Logic & High Voltage Generator
Global Buffers
Output Driver
I/O 0
I/O 7 CLE
ALE
WP
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Basic operations NAND Flash
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Read operation Bias condition - selected WL : Target voltage (Vtarget) - unselected WLs : high enough to conduct all cells in a string 1V SSL Unselected WLs
Vread Vread Vread
Selected WL
Vtarget
Vread
Vtarget Vread P1
Unselected WLs
P2
Vread Vread
Vth
Vread Vread GSL
Vread 0V
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Sensing margin The ratio of On cell & Off cell current
Precharge Level (Vp)
Sensing margin Off cell Sensing Level On cell
0V
Precharge
Sensing
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Read disturbance Increasing Vread soft program occurs in the unselected cell of selected string
Vread # of cell
Vread
Vread
Vread Vtarget Vread
on 0V
Vread
Vth
On cell moves to off cell
Vread Vread Vread Vread - 25/48 ELECTRONICS
Program operation Bias condition - selected WL : Program voltage (Vpgm) - unselected WLs : Pass voltage (Vpass) Vcc
0V
Vcc
SSL
Vcc Vpass
Unselected WLs
# of cell
Vpass Selected WL
Vpgm Vpass on
off 0V
Unselected WLs
Vpass Vpass
Vth
on cell becomes off cell
Vpass Vpass GND
GSL - 26/48 -
ELECTRONICS
Program inhibition Should not be programmed (= program inhibited) Vcc
0V
Vcc
Vcc
Vcc Vpass
Vcc
Self boosting 0V Vpgm
OFF
Vcc-Vth+α
Vpass GND
Vpgm Vpass
Vcc
Vpass Vpass
Vcc
Vpass
Vpgm
OFF
Vpass GND
Vpass GND
For inhibition only, the higher Vpass, the better Vpgm disturbance But, higher Vpass causes more Vpass disturbance - 27/48 ELECTRONICS
Self boosting Inhibit BL : Vcc SSL
Vcc
WL31
10V
WL30
10V
WL29
20V
WL28
10V
Bias sequence for self boosting
Vpgm
Vpass WL1
10V
WL0
10V
GSL
0V
Inhibit channel is boosted !!!
Program channel
Channel potential strongly depends on the cell states in a string
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Vpass window “Optimal Vpass region” considering both Vpgm and Vpass disturbances at the same time Program cell 0V
SSL
VCC
WL31
10V
Inhibit cell VCC
Vpass Window Curve Vth Vpgm disturbance
WL30
10V Vpass disturbance
WL29
20V
WL28
10V -1V
WL1
10V
WL0
10V
GSL
0V
Vpass Vpass window
Vchannel = 0V
Vchannel = 8~9V - 29/48 ELECTRONICS
Erase operation Bias condition - all WLs in the selected Block : 0V - GSL/SSL : Floating - Bulk : Vera Floating # of cell
GND GND GND GND
on
off 0V
GND
Vth
off cell becomes on cell
GND GND GND Floating
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Erase disturbance “Self boosting” can be used Old Method
New Method B/L (20V)
B/L (20V)
SSLn(20V) Select Block
SSLn(Floating) Select Block
WL0(0V)
WL0(0V) WL7(0V)
WL7(0V) GSLn(20V)
GSLn(Floating)
CSL(20V)
CSL(20V)
GSLn-1(20V) Unselect Block
GSLn-1(Floating) Unselect Block
WL7(20V)
WL7(Floating)
WL0(20V)
WL0(Floating)
SSLn-1(20V)
SSLn-1(Floating)
Cell Array Substrate
0V
20V
Cell Array Substrate
0V
20V
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Cell Vth distribution Cell Vth width requirement - 1bit/cell vs. 2bit/cell vs. 3bit/cell # of cells 2 Level Cell
Vth Upper Limit
SLC
E
(∵ NAND Flash)
P
4 Level Cell Vread
MLC
E
P1
P2
P3
8 Level Cell
3bit
E
P1 P2 P3 P4 P5 P6 P7 0V
Vth - 32/48 ELECTRONICS
Cell Vth width control Incremental Step Pulse Program (ISPP) - programmed state Vth width can be controlled - narrower width requires more program loop
Change of cell Vth : slow vs. fast cell Cell Vth Vpgm Vvfy Vpgm
Vpgm_start
No. of Loop
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Current issues & approaches
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Criteria for a NAND Flash device MLC
Vread
NAND E
Cost • Chip size • Bit density • etc…
P1
P2
P3
Performance
Reliability
• Program time • Read time • etc…
• Data retention • Program/Read cycle • etc…
All these are strongly dependent on each other and may become worse as “cell size shrinks down” - 35/48 ELECTRONICS
Details on programmed Vth Factors which affect to programmed Vth width - Ideal : ΔVpgm during ISPP program - Noise : F-poly coupling, CSL noise, Back pattern dependency - Reliability : Endurance, program/read disturbance, charge loss # of Cells
Charge Loss : HTDR, RTDR
F-poly coupling Program disturbance Read disturbance
Endurance
Ideal 0V
Vth
Verify level - 36/48 ELECTRONICS
Neighborhood interference F-poly coupling noise - Cell Vth can be raised as neighboring cells are programmed
1
2 3 4
C-poly
C-poly
ONO
ONO
Victim
1
2 3 4
P-well BL(1) BL(2) WL(i+1)
4
WL(i)
2
Aggressor
BL(3)
3
4
1
2
Vth
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Cell Vth vs. F-poly coupling
WL Initial
Cell State
E
BL Diag.
Final
# of cells
P1
P2
WL1
Diag.
WL
Diag.
WL2
BL
V
BL
WL3
Diag.
WL
Diag.
BL1
BL2
BL3
P3
Vth
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Cell size vs. F-poly coupling ’09 ISSCC
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F-poly coupling reduction – (I) Shadow program - Make final Vth after being coupled 7
Shadow sequence
WL3
4 5
# of cells
LSB
2
E
P0
11
WL2
10
5
# of cells
LSB
11
P0
2
# of cells
WL1
1
10
cell Vth MSB
WL2
3
WL1
1
WL3
4 E
3
6
Convential sequence
cell Vth # of cells
MSB
E
P1
P2
P3
E
P1
P2
P3
11
01
00
10
11
10
00
01
cell Vth
cell Vth
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F-poly coupling reduction – (II)
Reprogram 7
- Make final Vth after being coupled
WL3
coupled
4 5
# of cells
WL2
7-1
2 3
Coarse program & coupled
9-1
5-1
WL1 1
E
P1’
P2’
P3’ cell Vth
Fine program
where P1’ < P1, P2’ < P2, P3’ < P3
Fine program
E
P1
P2
P3 cell Vth
Program performance overhead due to “Fine program” - 41/48 ELECTRONICS
F-poly coupling reduction – (III) All-bit line (ABL) architecture - all cells in a WL are programmed at the same time - in SBL, cells in even BL first, cells in odd BL next (BL-coupling exists) Physical 8KB cells
SBL(Shielded-bit line) BLe
BLo
ABL(All-bit line) BL1
BL2
64 cells (one string)
One block
PB
Features : SBL vs. ABL PB
PB
PB
SBL
ABL
No. of PBs (page depth)
4KB
8KB
pages/block
256 pages
128 pages
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In the near future
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3D Flash memory Bit-Cost Scalable(BiCS) technology 2007 IEDM, Toshiba
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3D Flash memory TCAT(Terabit Cell Array Transistor) technology 2009 VLSI, Samsung
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What is CTF ? CTF (Charge Trap Flash) - SONOS type Flash - electron is trapped in nitride trap layer
Floating Gate
SONOS
Si
Si (S) Oxide (O) Nitride (N) Oxide (O) n+
F-Gate
ON O
Oxide (O)
n+ n+
P.C.Y. Chen, TED, V. 24, pp.584-586, 1977
n+
F.Masuoka (Toshiba) IEDM 1984
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Floating gate vs. SONOS
“No neighborhood coupling”
All stored charge is lost
Only part of the charge is lost
Thicker tunnel oxide
Thinner tunnel oxide
Device Scaling is difficult
Device Scaling is easy - 47/48 ELECTRONICS
Thanks for your listening !
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