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IEEE ELECTRON DEVICE LETTERS, VOL. 39, NO. 4, APRIL 2018
Negative Differential Resistance in Negative Capacitance FETs Jiuren Zhou , Genquan Han , Member, IEEE , Jing Li, Yan Liu, Yue Peng, Jincheng Zhang, Qing-Qing Sun , David Wei Zhang, and Yue Hao, Senior Member, IEEE Abstract — We report the investigation of negative differential resistance (NDR) in negative capacitance (NC) germanium (Ge) pFETs. The NDR in NC transistors is attributed to the coupling of drain voltage to the internal gate voltage Vint via the gate-to-drain capacitance. It is demonstrated that NDR strongly depends on the matching between the NC induced by ferroelectric capacitance CFE and the positive capacitance associated with the underlying transistor capacitance CMOS . For the non-hysteretic devices, NDR gets pronounced with an increased thickness of ferroelectric film tfe and VGS . This is attributed to the fact that the drain coupling factor is improved with an increased tfe and VGS , leading to the better matching between CFE and CMOS . For the hysteretic NC transistors, however, NDR is only obtained at the lower VGS , but not observed at higher VGS . Index Terms — Negative capacitance, FET, ferroelectric, negative differential resistance.
I. I NTRODUCTION EGATIVE capacitance (NC) field-effect transistor (FET) has been considered as a promising candidate for the ultralow power applications, due to its capability of achieving sub-kT/q subthreshold swing (SS) [1]. Recently, many research efforts have been extensively explored on NC device technology [2]–[4] and NC transistor based circuit design [5], [6]. Besides sub-60 mV/decade SS, other typical characteristics of NC transistors were also studied, for instance, hysteresis in IDS -VGS curves [7], [8], peaks in gate capacitance curves [9]–[11], and negative differential resistance (NDR) in IDS -VDS curves [12], [13] We have demonstrated that non-hysteretic NCFETs can be realized by increasing the magnitude of negative ferroelectric capacitance |CFE | enabled
N
Manuscript received January 27, 2018; revised February 18, 2018; accepted February 23, 2018. Date of publication February 27, 2018; date of current version March 22, 2018. This work was supported by the National Natural Science Foundation of China under Grant 61534004, Grant 61604112, and Grant 61622405. The review of this letter was arranged by Editor M. Passlack. (Corresponding author: Genquan Han.) J. Zhou is with the State Key Discipline Laboratory of Wide Band Gap Semiconductor Technology, School of Microelectronics, Xidian University, Xi’an 710071, China, and also with the Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA 94720 USA. G. Han, J. Li, Y. Liu, Y. Peng, J. Zhang, and Y. Hao are with the State Key Discipline Laboratory of Wide Band Gap Semiconductor Technology, School of Microelectronics, Xidian University, Xi’an 710071, China (e-mail:
[email protected]). Q.-Q. Sun and D. W. Zhang are with the State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, China. Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2018.2810071
by tuning ferroelectric properties and the area of negative capacitor [7], [8], [12], [14]. In addition, the magnitude of gate capacitance peak was demonstrated to be directly associated with the drive current of NCFETs [9]. The NDR in NC transistors, originated from the coupling of drain voltage to the internal gate voltage Vint via the gate-to-drain capacitance CGD [6], [15], leads to the current loss of the device. NDR was observed in both NC planar transistor [12] and FinFET [16]. It was reported that, even if NC transistors achieve the hysteresis-free in IDS -VGS curves, the existence of NDR could lead to the hysteretic voltage transfer characteristics of the logic gates producing the higher noise margins [6], [17]. The theoretical study showed that the differential resistance, defined as gds = ∂ I D S /∂ V D S , depended on the matching between the negative capacitance induced by ferroelectric capacitance CFE and the positive capacitance associated with the underlying transistor capacitance CMOS , which was affected by the gate voltage VGS , the drain voltage VDS , as well as the material parameters, e.g. the thickness of ferroelectric layer tfe [6]. So far, there is still a lack of detailed experimental study on NDR in NC transistors. In this work, NDR in NC Ge pFETs with the different thicknesses of HfZrOx (HZO) is experimentally investigated. The dependence of NDR phenomena on tfe and VGS is discussed. II. E XPERIMENTS The starting wafer was a 4-inch n-Ge(001) wafer. The Ge surface was passivated using 10% Si2 H6 in H2 gas in an ultrahigh vacuum chamber with a base pressure of 10−7 Pa. During the passivation, the substrate temperature is 350 °C, and chamber pressure is about 10−4 Pa. After that, TaN/HZO/TaN/HfO2 stack was formed. HfO2 and HZO (with a Hf:Zr ratio of 0.5:0.5) were deposited by a commercial Picosun atomic layer deposition at 300 °C using Hf and Zr precursors of Tetrakis(ethylmethylamino)-Hf (TEMAH) and tetrakis(ethylmethylamino)-Zr (TEMAZ), respectively. Three tfe splits of 3.7, 4.5, and 6.6 nm were utilized. All TaN layers were deposited using reactive sputtering at room temperature with Ta target and N2 . After gate etching by dry etching using Cl2 based gas, BF+ 2 implantation with an energy of 20 KeV and a dose of 1015 cm−2 , and Ni deposition into source/drain (S/D) regions by lift-off process were carried out. Finally, HZO crystallization, dopant activation, and S/D metallization were performed through rapid thermal annealing at 450 °C and were performed 30 s in N2 atmosphere using UniTemp RTP-150. After post-annealing, Ni mono-germanide phase with a specific contact resistivity of 2 × 10−4 · cm2 were achieved by TLM [18]. Control device without HZO
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ZHOU et al.: NEGATIVE DIFFERENTIAL RESISTANCE IN NC FETs
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Fig. 1. (a) Schematic of the fabricated NC Ge pFET. (b) The top view SEM image of an NC device. (c) TEM image showing the gate stack of NC transistors on Ge channel. (d) HRTEM image features TaN/HfO2 stack on the Si2 H6 passivated Ge channel. (e), (f), (g) depicting different tfe of 6.6, 4.5, and 3.7 nm, respectively. (h) P-E hysteresis loops for TaN/HZO/TaN samples annealed at 450 °C with the different tfe .
was also fabricated. The schematic of the NC device is shown in Fig. 1(a). Fig. 1(b) depicts the top view scanning electron microscope (SEM) image of an NC device. The transmission electron microscope (TEM) image in Fig. 1(c) shows the gate stack of TaN/HZO/TaN/HfO2 on Ge channel. A SiO2 interfacial layer of ∼1.2 nm is observed between channel and HfO2 . High-resolution TEM (HRTEM) image in Fig. 1(d) depicts the TaN/HfO2 stack on the Si2 H6 passivated Ge channel. HRTEM images in (e), (f), and (g) feature the tfe splits of 6.6, 4.5, and 3.7 nm, respectively. Fig. 1(h) shows the curves of polarization P as a function of electric field E for the TaN/HZO/TaN samples with different tfe annealed at 450 °C. III. R ESULTS AND D ISCUSSION It is found that the NDR in NC Ge pFETs depends on tfe and gate overdrive, and NC transistors with and without hysteresis exhibit the different variation characteristics of gds values with gate overdrive.
A. NDR in Non-Hysteretic NC Ge pFETs Fig. 2 compares the NDR in the non-hysteretic NC Ge pFETs with different tfe . Fig. 2(a) shows the hysteresis-free transfer characteristics of the NC devices with 6.6 nm, 4.5 nm, and 3.7 nm HZO. Fig. 2(b) shows the output characteristics of the NC devices at different values of gate overdrive. The extracted gds as a function of VDS curves for the devices are illustrated in Fig. 2(c), demonstrating that NC Ge pFETs with 6.6 nm HZO have the more negative gds, i.e. more significant NDR, in comparison to the other devices with thinner HZO. For the device with a tfe of 3.7 nm, almost no negative gds is observed. Fig. 3 summaries the minimum values of gds for NC devices at different gate overdrive. It can be seen the minimum gds decreases with an increased tfe and |VGS -VTH |. From fig. 2(a), it is seen that there is a crossover point between forward and reverse sweeping of IDS -VGS curves, indicating that effect of traps also exist in the device. In spite of that, NC effect dominates the electrical behaviors, showing the improved IDS and SS over control [9], [12], and other unique capacitance characteristics (Fig. 4). According to the modeling in [6], the relation of Vint , VGS , and VDS can be expressed as: d Vint = ηd VG S − η G D d V D S,
(1)
where, η is given by 1/(1−C M O S /|C F E |) and coupling factor ηG D is expressed by C G D /(|C F E | − C M O S ). CMOS is the gate capacitance of the underlying transistor.
Fig. 2. (a) IDS -VGS curves of NC Ge pFETs with different thicknesses of HZO. (b) IDS -VDS curves of NC devices. (c) Extracted gds versus VDS for NC transistors at different gate overdrive showing that 6.6 nm HZO device has the more obvious NDR compared to the other devices.
For the non-hysteretic NC Ge pFETs, it is supposed that |CFE | is larger than CMOS [19], [20], and both η and ηG D are positive. With the increase of tfe , the magnitude of CFE is decreased and much closer to the value of CMOS , producing the better capacitance matching. Hence, ηG D rises with an increased t f e , i.e. the thicker HZO of an NC Ge pFET is, the more significant the NDR. With the fixed tfe , the increasing of gate overdrive leads to a higher CMOS , which also improves the matching between CMOS and CFE , contributing to the higher ηG D and more negative gds . Meanwhile, the matching between CMOS and CFE varies with tfe , which also can be seen from the gate capacitance CG characteristics of the devices, as shown in Fig. 4. CMOS -VG curve measured from a control device without HZO is also shown. The series combination of CFE and CMOS is referred to the CG , i.e. CG = CFE · CMOS /(CMOS + CFE ). Only if CFE < 0 and |CFE | > CMOS , CG peak higher than CMOS will appear. The peak of CG demonstrating the negative capacitance effect decreases with the increased |CFE | due to the reduction of tfe .
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IEEE ELECTRON DEVICE LETTERS, VOL. 39, NO. 4, APRIL 2018
Fig. 3. Comparison of the minimum gds versus gate overdrive for NC Ge pFETs with different tfe of 3.7, 4.5, and 6.6 nm.
Fig. 5. (a) IDS -VGS curves of an NC Ge pFET with 6.6 nm HZO showing obvious hysteresis. (b) CG -VG curves of the same NCFET. (c) IDS -VDS curves of the same device with forward and reverse sweeping of VGS . (d) Extracted gds versus VDS characteristics for the same NC transistor. (e) Minimum gds as a function of VGS showing that the most significant NDR occurs at the lower VGS .
Fig. 4. CG versus VG curves of the NC Ge pFETs with different tfe . CMOS -VG curve is also shown.
B. NDR in Hysteretic NC Ge pFETs It was demonstrated that obvious hysteresis was also observed in some NC Ge pFETs with 6.6 nm HZO, due to the variation of ferroelectric properties of HZO induced by non-uniform poly-crystallization [8], [12]. Fig. 5(a) shows the IDS -VGS of a hysteretic NC Ge pFET with 6.6 nm HZO. For hysteretic NC transistors, |CFE | < CMOS should occur during the sweeping of VGS . Fig. 5(b) shows the CG -CG curves of the same NC transistor, and CG peaks indicating the NC effect are observed in spite of the hysteresis. IDS -VDS curves of the same device are shown in Fig. 5(c), demonstrating the obvious NDR with the forward and reverse sweeping of VGS . The extract gds as a function of VDS curves at the different VGS of the device are illustrated in Fig. 5(d). Fig. 5(e) compares the minimum gds values at different VGS . For both forward and reverse sweeping of VGS , the most negative gds is achieved at the lower VGS , e.g. from 0.9 to 1.3 V. As gate overdrive increases the gds rises to the positive value. According to the Eq. (1), at a lower VGS , the value of CMOS is still smaller than |CFE |, which keeps the positive ηG D and NDR. However, with an increased VGS , the improved CMOS can be larger than |CFE |, and the NDR is not observed. It is noted that the reverse sweeping of VGS provides a larger NDR over forward sweeping. It has been demonstrated that the NC transistors with hysteresis always exhibit the asymmetrical electrical characteristics [4], [10], [15], [20]. Reverse sweeping
of VGS leads to the steeper SS compared to the forward case, indicating the more pronounced NC effect for the reverse sweeping of VGS . Hence, it is reasonable that, in hysteretic NC Ge device, the reverse sweep has a stronger NDR in comparison to the forward sweep. According to the analysis above, it is demonstrated that NDR, resulting in drive current loss, can be effectively suppressed by modulating the capacitance matching between negative CFE and positive CMOS , i.e. the reduction of tfe , which is consistent with some theoretical calculations [6], [15]. Experiments found that SS and IDS of NC Ge pFETs degrade with the reduction of tfe , due to the worse capacitance matching between CFE and CMOS [21]. Reduction of CGD by optimizing the device structure is an effective way to decrease NDR. Actually, on the other hand, the existence of NDR can compensate the drain induced barrier lowering effect in short channel MOSFET, pushing out the scalability limit of the CMOS devices. Finally, we clarify that, although NDR was observed in SOI MOSFET by self-heating [22], but it did not induce the C-V curves in Fig. 4 or provide the dependence of NDR on tfe . In addition, as we replace the HZO film by HfO2 , NDR phenomenon cannot be observed, and this proves that NDR is caused by NC effect induced by the ferroelectricity of HZO. IV. C ONCLUSION It is experimentally demonstrated that NDR in NC transistors is dependent on tfe and gate overdrive. For the nonhysteretic devices, more pronounced NDR is obtained with an increased tfe and VGS , which leads to the improved matching between CFE and CMOS . For the hysteretic NC transistors, NDR is only achieved at a lower VGS , because, at a higher VGS , |CFE | can be smaller than CMOS , giving rise to a negative ηG D , in which case NDR cannot be observed.
ZHOU et al.: NEGATIVE DIFFERENTIAL RESISTANCE IN NC FETs
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