New building block: multiplication-mode current

www.ietdl.org Published in IET Circuits, Devices & Systems Received on 5th June 2008 Revised on 12th November 2008 doi: 10.1049/iet-cds:20080156

ISSN 1751-858X

New building block: multiplication-mode current conveyor Y.-S. Hwang W.-H. Liu S.-H. Tu J.-J. Chen Department of Electronic Engineering, National Taipei University of Technology, Taipei 106, Taiwan, Republic of China E-mail: [email protected]

Abstract: A new building block called the multiplication-mode current conveyor (MMCC) is proposed here. The structure consists of a differential voltage current conveyor (DVCC) and a folded Gilbert cell without any other auxiliary circuits. Based on the MMCC, a four-quadrant analogue multiplier is designed in TSMC 0.35 mm CMOS 2P4M processes with power supply +1.65 V. HSPICE post-layout simulation results show that the maximum DC operating range is +200 mV, the loading range is from 1 to 10 kV, the bandwidth is about 90 MHz, the total harmonic distortion (THD) is 0.85%, the power consumption is 1.08 mW and the chip area without pads is 0.48  0.36 mm2. The new square summer and analogue divider applications employing MMCCs are also presented.

1

Introduction

The current-mode circuits are proven to offer several advantages over their voltage-mode counterparts [1, 2]. The secondgeneration current conveyor (CCII) has been receiving significant attention in current-mode filters [3, 4]. Moreover, many current-mode analogue signal processing applications are presented by using CCIIs [5–7]. Some different types of current conveyors are also proposed [8–10]. But they have the same features which the addition and/or subtraction of the input voltages use. On the other hand, the multiplier is a very useful building block in the modulator, adaptive filter, artificial neural network etc [11, 12]. It is often categorised as the single-quadrant (inputs are both unipolar), two-quadrant (one of the inputs is bipolar) and four-quadrant (inputs are both bipolar) circuits. The basic idea of the multiplier is that there are two input signals applied to a nonlinear device characterised by a high-order polynomial function. The polynomial function involves many nonlinear terms and these terms must be cancelled to reduce the total harmonic distortion (THD). In the recent years, a lot of different architectures of analogue multipliers based on CCIIs are proposed [13–15]. In the article, we propose a new architecture called the multiplication-mode current conveyor (MMCC) that combines the advantages of the differential voltage current conveyor (DVCC) and the folded Gilbert cell [16] four-quadrant multiplier to provide both voltage and IET Circuits Devices Syst., 2009, Vol. 3, Iss. 1, pp. 41– 48 doi: 10.1049/iet-cds:20080156

current signals from the outputs without any other auxiliary circuits. The circuit description of the proposed MMCC is introduced in Section 2, and the simulation results of the MMCC are shown in Section 3. Section 4 proposes the square summer and the analogue divider applications. Finally, the conclusion is made in Section 5.

2

Circuit descriptions

The circuit symbol of the DVCC is shown in Fig. 1. Basically, the terminal relationship of an ideal DVCC can be given by the following matrix 2

3 2 IY1 0 6 IY2 7 6 0 6 7 6 4 VX 5 ¼ 4 1 IZ 0

0 0 1 0

0 0 0 +1

3 32 VY1 0 6 7 07 76 VY2 7 0 54 IX 5 IZ 0

(1)

where the plus sign represents the positive DVCC and the minus one represents the negative DVCC, respectively. The CMOS circuit of the positive DVCC [8] is shown in Fig. 2. The circuit structure consists of additional differential pair and the CCII. The input stage (M1 and M2 , M7 and M8) adopts two differential pair and provides two inputs, Y1 and Y2 . The high-gain stage is composed of an active current mirror (M3 – M6) which converts the differential 41

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www.ietdl.org The CMOS folded Gilbert cell [16] is shown in Fig. 3, and it is modified from the Gilbert cell and owns the larger input common-mode range than the traditional one. The output voltage of the folded Gilbert cell can be derived from a straightforward circuit analysis and yields

Figure 1 Circuit symbol of DVCC currents to a single-ended output current (M9 and M10), and others (M13 – M18) provide the bias currents. In addition, the transistors (M11 and M12 , M19 and M20) make a copy of current signal from the input stage, so the output currents of X and Z terminals are equal. Considering the open loop gain (Ao) of the first stage, the voltage relationship between X, Y1 and Y2 can be represented as VX ¼ Ao (VY1  VY2 )

(2)

When the unity-gain negative feedback applied from the output node (X terminal) to the input terminal (gate of M7), and the open loop gain is much larger than one, the relationship between the output and input voltages can be represented as follows VX ¼

Ao (V  VY2 ) ’ VY1  VY2 1 þ Ao Y1

(3)

Vout ¼ Iout Rout ¼ (I7  I8 )Rout 2vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi !2 u u ISS V32 V3 6t K p ¼ Kn V4 4  þ pffiffiffi V42 Kn Kp 2 2 ffi3 vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi !2 u uK 2 ISS V3 V t p 7   p3ffiffiffi V42 5Rout  Kn Kp 2 2 ’

qffiffiffiffiffiffiffiffiffiffiffiffiffi 2Kn Kp V4 V3 Rout

(4)

where Kn and Kp are the transconductance parameters of NMOS and PMOS, and Rout is the output load resistance of the folded Gilbert cell, respectively. The advantages of the DVCC and the folded Gilbert cell are now combined and extended to a new building block called the MMCC shown in Fig. 4. The M1 to M6 are the folded Gilbert cell, and the M7 to M8 are the diodeconnection active loads to achieve higher linearity. In addition, the fully differential circuit with diode-connection loads does not need any common-mode feedback network; it can simplify the structure of the MMCC. The M9 to

Figure 2 CMOS circuit of positive DVCC 42

& The Institution of Engineering and Technology 2009

IET Circuits Devices Syst., 2009, Vol. 3, Iss. 1, pp. 41– 48 doi: 10.1049/iet-cds:20080156