New Cascaded Multilevel Inverter Topology With Reduced Variety of ...

New Cascaded Multilevel Inverter Topology With Reduced Variety of Magnitudes of dc Voltage Sources Sepideh Bahravar

Ebrahim Babaei, Member, IEEE

Department of Electrical Engineering Science and Research Branch, Islamic Azad University Tabriz, Iran [email protected]

Faculty of Electrical and Computer Engineering University of Tabriz Tabriz, Iran [email protected]

Seyed Hossein Hosseini, Member, IEEE Faculty of Electrical and Computer Engineering University of Tabriz Tabriz, Iran [email protected]

Abstract—In this paper, a new basic topology is proposed for cascaded multilevel inverters. The proposed basic topology is comprised of two dc voltage sources, two unidirectional power switches, and an H-bridge. A new generation of cascaded multilevel inverters can be achieved by series connection of some number of proposed basic topology. The proposed cascaded multilevel inverter in symmetric condition utilizes less number of switches in comparison with the conventional symmetric multilevel inverter. In addition, in asymmetric condition, the variety of magnitudes of dc voltages sources is less than the conventional ones. In order to generate all voltage levels (odd and even), four new algorithms are suggested to determine the magnitudes of dc voltage sources. The ability of the proposed topology in generating the desired output voltage is proved through the simulations results carried out in PSCAD/EMTDC software. Keywords—Multilevel inverters; symmetric cascaded multilevel inverters; asymmetric cascaded multilevel inverters.

I.

INTRODUCTION

In recent years, vast researches are conducted in the field of multilevel inverters. The general concept of the multilevel inverter is to use more power switches to accomplish the power transform with small voltage steps. There is good attention to multilevel inverters in comparison with the conventional two level inverters due to several advantages such as generating output waveforms with lower harmonics distortions level, lower dv / dt stress on power switches, the possibility of using switches with lower nominal rating values, and lower electromagnetic interference [1-2]. The Researches conducted on multilevel inverters mainly concentrate on two general aspects of the topology and the control techniques of this type of inverters.

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Three basic topologies of “flying capacitor multilevel inverter” [3], “clamping diode multilevel inverter” [4], and “cascaded multilevel inverter” [5] have been presented for multilevel inverters. Control simplicity and the possibility of packing of cascaded multilevel inverters make this type of inverters to be more under consideration. This paper focuses on cascaded multilevel inverters. This type of inverters are comprised of the series connection of full H-Bridge single-phase inverters. Here, each single-phase bridge is fed by its own dc voltage source and with proper switching; the desired output voltage is generated. This type of inverters can be easily expanded to any number of voltage levels by connecting more numbers of single-phase bridges in series. Two symmetric and asymmetric approaches can be under attention for this type of inverters considering the values of the used dc voltage sources. The symmetric multilevel inverter is the one in which all dc voltage sources have equal values. Here, all series bridges are similar because they have the same topology and operate with the similar voltage levels. This is called modularity feature, leads to a decrease in inverter design costs, and makes it possible to use similar parts in the topology of the inverter. The major problem of the symmetric cascaded inverter is the fact that the number of power switches strongly increases as the number of levels increases. In return, the values of the dc voltage sources are different in asymmetric multilevel inverters. This is to generate more voltage levels using lower number of power switches. In this type of multilevel inverters, two binary and trinary arrangements are considered for dc voltage sources. In binary arrangement, the size of dc voltage sources varies with orders of two, where it varies with orders of three in trinary arrangements. One of the defects of the asymmetric multilevel inverter in comparison with the symmetric one is to lose the modularity. In result, according to not to existence of the

complete iterative switching states in asymmetric multilevel inverters, it is not possible to apply the charge balance control methods. The charge balance control methods are the ones applied to control symmetric multilevel inverters to equalize the power fed by the dc voltage sources [6-10].

TABLE I. State

S1

S2

T1

T2

T3

T4

vo

1

0 0

0 0

1 0

0 1

1 0

0 1

0

The most obvious disadvantage of the cascaded multilevel inverters is the high number of used power switches. It should be mentioned that the used switches have low voltage rating and therefore, they are cheaper in comparison with the high power switches applied in two-level inverters. However, each power switch requires its own driver circuit which would lead to increase the overall size of the inverter. In this paper, a new topology is proposed for the cascaded inverters which require lower elements to generate similar output levels in comparison with the conventional cascaded multilevel inverters. For the proposed topology, four new algorithms are presented to determine the magnitudes of dc voltage source to generate all levels (odd and even) in the output voltage. In addition, a comprehensive comparison is carried out between the proposed topology and the conventional ones. The capability of the proposed topology in generating all desired voltage levels is finally reconfirmed through the simulation results of a 25-level inverter based on the proposed topology. II. PROPOSED TOPOLOGY The basic proposed topology for the multilevel inverters is illustrated in Fig. 1. The basic topology consists of two dc voltage sources, two unidirectional power switches, and an Hbridge. Each applied switch consists of an insulated gate bipolar transistor (IGBT) along with an anti-parallel diode. It is possible to generate two voltage levels of V 1 and V 1 +V 2 at output of H-bridge by properly controlling S 1 and S 2 switches. The voltage levels of 0, ±V 1 , and ±(V 1 +V 2 ) can be generated at the output of the inverter using the applied Hbridge and properly controlling its switches. Therefore, the number of the generated voltage levels in the proposed basic topology equals to five. Table I shows different values of the inverter output voltage in terms of different switch states. In this Table, 1 constitutes the on-state and zero indicates the offstate of switches. According to Table I, it is obvious that the maximum amplitude of the generated voltage at output of inverter equals to V 1 +V 2 .

DIFFERENT OUTPUT VOLTAGE VALUES FOR PROPOSED BASIC TOPOLOGY

2

1

0

1

0

0

1

+V 1

3

0

1

1

0

0

1

+(V 1 +V 2 )

4

1

0

0

1

1

0

−V 1

5

0

1

0

1

1

0

−(V 1 +V 2 )

As shown in Fig. 2, the topology of proposed cascaded multilevel inverter is based on the series connection of some number of the proposed basic topology. This topology is comprised of series connection of n proposed basic inverters. The output voltage (v o ) of the proposed multilevel inverter equals to the sum of output voltages of each basic topology. In the other words, the following is valid:

(1)

v o = v o ,1 + v o ,2 + L + v o , n

where v o ,1 , v o , 2 , and v o , n are the output voltages of the first, second, and the n -th basic topology, respectively. It is possible to generate the desired output voltage by proper selecting the magnitudes of dc voltage sources.

+

V 1,1 S 1,1

T1,1

T 3,1

v h ,1 (t ) V 2,1

S 2,1

−

+ v o ,1 (t )

T 2,1

T 4,1

T1,2

T 3,2

−

i o (t ) +

V 1,2 S 1,2

v o ,2 (t )

v h ,2 (t ) V 2,2

S

2,2

−

+

V 1,n S 1,n

T 2,2

T 4,2

T1,n

T 3,n

S

2, n

−

−

+

v o (t ) −

+

v o ,n (t )

v h ,n (t ) V 2,n

+

T 2, n

T 4, n

−

Fig. 2. The proposed cascaded multilevel inverter V1

+

S1

T1

T3

v h (t ) V2

S

2

−

+ v o (t )

T2

T4

−

Fig. 1. Basic topology proposed for the cascaded multilevel inverters

III. DETERMINATION THE VALUES OF DC VOLTAGE SOURCES In this section, to generate all voltage levels (odd and even) in the proposed cascade multilevel inverter, four new algorithms are proposed to determine the magnitudes of dc voltage sources used.

A. The first proposed algorithm In the first proposed algorithm, the magnitudes of all dc voltage sources are the same and are considered V dc . In other words, the following is valid:

V 1,1 =V 2,1 =V 1,2 =V 2,2 = L =V 1, n =V 2, n =V dc

(2)

Applying this algorithm, the number of output levels (N step ) , number of power switches (N switch ) , number of dc voltage sources ( N source ) , maximum generated voltage (V o ,max ) , and the variety of magnitudes of dc voltage source

(N variety ) are respectively calculated by the following equations:

N step = 4n + 1

(3)

N switch = 6n

(4)

N source = 2n

(5)

V o ,max = 2nV dc

(6)

N variety = 1

(7)

B. The second proposed algorithm In the second proposed algorithm, the magnitudes of all dc voltage sources in each i -th basic topology are similar and considered 2i −1V dc ( i is the number of basic topology) for i = 1, 2, L, n . In other words, the following equations can be applied to calculate the magnitudes of dc voltage sources in different basic topologies. First basic topology (8)

Second basic topology

V 1,2 =V 2,2 = 2V dc

N step = 2n + 2 − 3

(12)

V o ,max = 2(2 n − 1)V dc

(13)

N variety = n

(14)

C. The third proposed algorithm In the third proposed algorithm, the magnitudes of dc voltage sources in each basic topology are equal and considered as 4i −1V dc . In other words, the following equations can be applied to calculate the magnitudes of dc voltage sources in different basic topologies. First basic topology

V 1,1 =V 2,1 =V dc

(15)


It is important to mention that if the variety of magnitudes of dc voltage sources sizes is less the overall cost of a multilevel inverter will be low. In this algorithm, the inverter is the symmetric multilevel inverter since the magnitudes of all dc voltage sources are equal.

V 1,1 =V 2,1 =V dc

Applying this algorithm, the number of generated levels, the maximum output voltage, and the variety of magnitudes of dc voltage sources are calculated through the following relations, respectively:

(9)

V 1,2 =V 2,2 = 4V dc

(16)

Third basic topology

V 1,3 =V 2,3 = 16V dc

(17)

n -th basic topology V 1, n = V 2, n = 4n −1V dc

(18)

Applying this algorithm, the number of generated levels and the maximum output voltage are calculated as follows, respectively: N step =

4 n +1 − 1 3

(19)

V o ,max =

2(4 n − 1) V dc 3

(20)

D. The fourth proposed algorithm In the fourth proposed algorithm, the magnitudes of dc voltage sources in each i -th basic topology are equal and considered 5i −1V dc . In other words, the following equations can be applied to calculate the magnitudes of dc voltage sources in different basic topologies. First basic topology


V 1,3 =V 2,3 = 4V dc

V 1,1 =V 2,1 =V dc (10)

(21)


V 1,2 =V 2,2 = 5V dc

(22)


(11)


V 1,3 =V 2,3 = 25V dc

(23)


(24)

Applying this algorithm, the number of generated levels and the maximum output voltage are calculated through the following relations, respectively: N step = 5

n

the proposed topology needs less value of the variety. This causes a major reduction in the overall cost of the inverter. TABLE II.

DIFFERENT QUANTITIES OF CONVETIONAL CASCADED MULTILEVEL [11] Asymmetric Binary Trinary 4 ln(N step + 1) 4ln N step −4 ln 3 ln 2

Symmetric

(25)

2( N step − 1)

N switch n

V o ,max =

5 −1 V dc 2

(26)

N source

In second, third, and fourth algorithms, the number of switches and the number of dc voltage sources can be calculated by (4) and (5), respectively. In addition, the variety of magnitudes of dc voltage sources of third and fourth algorithms are obtained by (14).

ln 2

V o ,max N variety

1

ln 3

ln(N step + 1) ln 2

N step − 1 V dc 2 ln N step

−1

ln 3

S 3,1

+ v o ,1 −

V1 S 4,1

S 2,1

S 1,2

S 3,2

+ v o ,2

V2

In this section, in order to show the advantages and disadvantages of the proposed topology, the comparison results with the conventional cascaded multilevel inverter (shown in Fig. 3) are given. The relations of N switch , N source , and N variety versus N step for both of conventional and proposed topologies are summarized in Tables II and III, respectively. As shown in these Tables, for same number of steps the maximum value of output voltage for both topologies under different conditions is equal. In addition, in symmetric condition, the variety and number of dc voltage sources for both topologies are same.

ln N step

−1

N step − 1 V dc 2

S 1,1

IV. COMPARISON THE PROPOSED TOPOLOGY WITH THE CONVENTIONAL TOPOLOGY

Fig. 5 shows the variations of variety of magnitudes of dc voltage sources versus the number of output steps. As shown in this figure, for generating the same number of output steps,

ln(N step + 1)

2 N step − 1 V dc 2

It is important to mention that the magnitudes of dc voltage sources in second, third, and fourth algorithms are different. As a result, this type of inverters is considered asymmetric. Considering the results of four proposed algorithms, it is clear that for the similar numbers of sources and switches, the fourth algorithm can generate more number of levels as well as higher maximum output voltage in comparison with the third algorithm. It is also shown that the performance of the third one is better than the second one and the performance of the second one is better than the first.

Fig. 4 shows the variations of number of switches versus the number of output steps for both of the conventional and proposed topologies. As shown in Fig. 4(a), in symmetric condition, for producing the same number of output voltage, the proposed topology needs less number of switches in comparison with the conventional topology. Reduction of the number of switches leads to use less number of gate driver circuits. As a result, the volume and cost of the inverter is decreased. In addition, the control system of inverter is simplified. As shown in Fig. 4(b), the third and fourth algorithms use less number of switches in comparison with conventional binary algorithm. In addition, it is clear that the number of switches for both of fourth and conventional trinary algorithms is approximately same.

N step − 1

S 4,2

S 2,2

S 1,n

S 3,n

−

vo

+ v o ,n

Vn

−

S 2 ,n

S 4 ,n

Fig. 3. Conventional cascaded multilevel inverter

TABLE III.

DIFFERENT QUANTITIES OF PROPOSED MULTILEVEL

Symmetric (First Algorithm) N switch N source

Asymmetric Second Algorithm Third Algorithm

3( N step − 1)

6 ln( N step + 3)

2

ln 2

N step − 1

2 ln( N step + 3)

2

ln 2

V o ,max

N step − 1 V dc 2

N variety

1

− 12 −4

N step − 1 V dc 2 ln(N step + 3) ln 2

−2

3ln(3N step + 1)

−6

ln 2 ln(3N step + 1) ln 2

−2

N step − 1 V dc 2 ln(3N step + 1) ln 4

−1

Fourth Algorithm 6 ln N step ln 5 2 ln N step ln 5 N step − 1 V dc 2 ln N step ln 5

+

20V

200

S 1,1

150

20V

N switch 100

25

50 N step

75

S

N switch

−

+

100V S 1,2

100

T 2,1

T 4,1

T1,2

T 3,2

i o (t ) +

−

L = 35mH

100V

S

2,2

−

+

R = 20Ω

v o ,2 (t ) −

v h ,2

(a)

30 Conventional Binary 25 Second Algorithm 20 15 10 Fourth Algorithm 5 Third A lgorithm Conventional 0 0 25 50 75 N step

2,1

+ v o ,1 (t )

vo

Proposed Symmetric

0 0

T 3,1

v h ,1

Conventional Symmetric

50

T1,1

T 2,2

T 4,2

−

Fig. 6. 25-level inverter based on the proposed topology

25-Level Inverter

Trinary

Vh,1 [V]

100

40

(b) Fig. 4. Variation of N switch versus N step ; (a) Symmetric topologies; (b)

20

Asymmetric topologies

0 6 4

0.0000

Conventional Binary Second Algorithm

0.0050

0

Third A lgorithm

0

25

0.0150

0.0200

0.0150

0.0200

(a)

N variety 2

0.0100

Conventional Trinary Fourth Algorithm

50

75

100

N step Fig. 5. Variation of N variety versus N step

25-Level Inverter

250

Vh,2 [V]

200 150 100 50 0

V. SIMULATION RESULTS In this section, to show the ability of the proposed inverter in generation of the desired output voltage, a 25-level inverter based on the proposed topology is simulated in PSCAD/EMTDC software. It is assumed that the aim is to generate the maximum 240V at output. In the simulated inverter, the fourth algorithm has been used to determine the values of dc voltage sources. Using this algorithm, the value of the lowest dc voltage source will be V dc = 20V . Fig. 6 shows the power circuit of the simulated topology. In simulation, the switches have been assumed ideal. In addition, a R − L load with values R = 20Ω and L = 35mH has been considered. Fig. 7 shows the input voltages of the H-bridges for first and second applied basic topologies, respectively. As shown in this figure, the input voltage of the H-bridges has only positive values of voltage.

0.0000

0.0050

0.0100 (b)

Fig. 7. Input voltages of H-bridges; (a) first H-bridge; (b) second H-bridge

As mentioned before, to generate both of positive and negative values of voltages at the output of the basic topology, an H-bridge inverter must be used. Fig. 8 shows the output voltages of both basic topologies. As shown in this figure, both of the positive and negative values of voltages are generated at the output of H-bridges Figs. 9 and 10 show the output voltage and current, respectively. As shown in Fig. 9, all of odd and even steps are generated at the output voltage. It is important to mention that the R − L load has a low-pass filter behavior. This causes that the output current has a near sinusoidal waveform.

VI.

25-Level Inverter

Vo,1 [V] 40 20 0 -20 -40 0.0000

0.0050

0.0100

0.0150

0.0200

(a)

25-Level Inverter

CONCLUSION

In this paper, a new topology of cascaded multilevel inverter was proposed. The proposed topology is comprises of series connection of some number of the presented basic topology. Also, four different algorithms were proposed to determine the magnitudes of dc voltage sources. It was proved that the generated topology needs less number of switches in comparison with the conventional cascaded topology. In addition, in the proposed topology the variety of the magnitudes of dc voltage sources is considerably less than the conventional ones. The validity of the presented theories was proved with the simulation results of a 25-level inverter based on the proposed topology.

Vo,2 [V]

200 100

REFERENCES

0 [1]

-100 -200 0.000

0.050

0.100

0.150

0.200

(b) Fig. 8. Output voltages of H-bridges; (a) first H-bridge; (b) second H-bridge

25-Level Inverter

300 200 100 0 -100 -200 -300

Vo [V]

0.000

0.020

0.040

0.060

0.040

0.060

Fig. 9. Output voltages

25-Level Inverter

Io [A] 10.0 5.0 0.0 -5.0 -10.0

0.000 Fig. 10. Output current

0.020

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