New Developments in Charge Pumping Measurements on Thin

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 11, NOVEMBER 2008

New Developments in Charge Pumping Measurements on Thin Stacked Dielectrics María Toledano-Luque, Robin Degraeve, Mohammed B. Zahid, Luigi Pantisano, Enrique San Andrés, Guido Groeseneken, Fellow, IEEE, and Stefan De Gendt

Abstract—This paper shows important improvements in charge pumping (CP) measurements on stacked high-k dielectrics, where the defects in high-k and SiO2 can be distinguished and estimated. The spatial profile of the interface traps and bulk traps is obtained by plotting the trap density as a function of the discharge time. Furthermore, the spectroscopic character of the base-level CP technique is demonstrated in HfSiON/SiO2 gate dielectrics by changing the applied pulse bias. It is found that when large pulse amplitude is applied to the gate, two bands appear superimposed on top of the usual base-level CP curve, suggesting the presence of two separate defect energy levels in the high-k dielectric. Index Terms—Dielectric films, MOSFETs.

I. INTRODUCTION

A

S THE SCALING of metal–oxide–semiconductor fieldeffect transistor (MOSFET) devices continues, silicon dioxide is no longer suitable due to the high tunneling leakage current [1]. Alternative dielectrics with higher dielectric constant are being extensively researched, and hafnium-based dielectrics are among the most promising candidates. However, the large amount of bulk traps causes VT instabilities [2], reduces mobility [3], and may result in early breakdown [4]. Therefore, a sensible technique to characterize these defects is extremely valuable. Conventional charge pumping (CP) measurement has been a reliable tool for the quantitative characterization of the MOS interface trap density, the extraction of its energy distribution within the Si bandgap, and the calculation of electron- and holecapture cross sections [5]. Low-frequency CP has been used to

Manuscript received February 1, 2008; revised July 29, 2008. Current version published October 30, 2008. This work was supported in part by IMEC’s Industrial Affiliation Program on High-k and Metal Gates and in part by the Spanish M.E.C. under Contract TEC 2007-63318/MIC. M. Toledano-Luque’s stay in IMEC was supported by the Spanish M.E.C. through its F.P.U. program. The review of this paper was arranged by Editor J. Suehle. M. Toledano-Luque and E. San Andrés are with the Dpto. Física Aplicada III (Electricidad y Electrónica), Facultad de Ciencias Físicas, Universidad Complutense de Madrid, Madrid 28040, Spain (e-mail: [email protected]). R. Degraeve, M. B. Zahid, and L. Pantisano are with the Interuniversity Microelectronics Center, 3001 Leuven, Belgium. G. Groeseneken is with the Interuniversity Microelectronics Center, 3001 Leuven, Belgium, and also with the Katholieke Universiteit Leuven (K.U.Leuven), 3001 Leuven, Belgium. S. De Gendt is with the Interuniversity Microelectronics Center, 3001 Leuven, Belgium, and also with the Department of Chemistry, Katholieke Universiteit Leuven, 3001 Leuven, Belgium. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2008.2005129

obtain near-interface and/or bulk trap density in MOSFET fabricated with SiO2 [6]. Recently, CP as a function of frequency has been used to characterize HfO2 bulk traps in gate stacks [7]. However, there exists disagreement in literature about how deep CP measurements can probe in the dielectric stack. Some groups [8]–[10] claim that the deepest accessible traps by CP are placed within the interfacial layer, whereas other groups [11], [12] state that traps within the high-k dielectrics can also be probed by this technique. In this paper, the applicability of the variable-frequency CP technique is further developed for high-k materials by independently controlling the low-level discharging time and the high-level charging time of the pulse. This allows us to clearly separate the contribution of SiO2 interface traps and HfO2 traps [12]. Note that high-k materials are known to have a dominant electron trapping component [2], thus simplifying enormously the interpretation of the CP data. The spatial profile of the interface and bulk traps can be estimated by plotting the trap density as a function of the discharging time. Furthermore, the thickness of SiO2 can also be determined from the CP data, and this nicely matches other estimation based on leakage current. Finally, when the CP measurements are done with large gate voltage amplitude, shallow, as well as deep, high-k traps can be sensed and assessed. This paper is organized as follows. After the experimental details (Section II), the evolution of the CP principles and applications are summarized in Section III. A first-order tunneling theory is introduced in Section IV to demonstrate that the CP technique is capable of scanning traps deeper than 1 nm inside SiO2 layers. The technique is used to assess the trap density as a function of both energy and physical depth in stacked dielectrics with an interfacial layer thinner than 1 nm. Experimental results (Section V) corroborate the validity of the proposed model and demonstrate the simplicity of the technique in order to obtain both the trap depth profile and the energy distributions in a single measurement. Finally, we summarize the conclusions of this paper in Section VI. II. EXPERIMENTAL SETUP TiN-gated nFETs with thin HfO2 /SiO2 and HfSiON/SiO2 were considered in this paper. Prior to the high-k dielectric deposition, a surface cleaning was done using an O3 -based chemistry [13]. This results in a ∼0.9-nm-thick SiO2 layer which is used as a starting surface for the HfO2 or HfSiO growth by atomic layer deposition (ALD). HfO2 films were grown using HfCl4 and H2 O as sources of hafnium and oxygen,

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TOLEDANO-LUQUE et al.: NEW DEVELOPMENTS IN CHARGE PUMPING MEASUREMENTS

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Fig. 2. Schematic illustration of the base-level CP measurement for the case of an n-channel MOSFET.

B. Bulk Trap Density in SiO2 Fig. 1. Possible current contributions in a CP measurement with alternative dielectrics. (1) Recombination current due to fast and slow interface states. (2) Charging and discharging of bulk defects. (3) Leakage current.

respectively. The source of silicon for HfSiO was SiCl4 . Plasma nitridation was used to incorporate N into the HfSiO film. Equivalent oxide thickness values of 1.2 and 1.7 nm were extracted for the gate stacks with 2-nm-thick HfO2 and 3-nmthick HfSiON, respectively. CP measurements were performed with an Agilent 81110A pulse generator and a Keithley 4200 semiconductor parameter analyzer. III. CP PRINCIPLES A. Conventional CP: SiO2 /Si Interface Trap Density The basic experimental setup to perform CP measurements for the determination of the SiO2 /Si interface state density was introduced by Brugler and Jespers [14] and is shown in Fig. 1. The drain and the source are connected to ground or to a reverse bias, whereas a voltage pulse train is applied to the gate. In the first-order theory for an n-MOS transistor pulsed into inversion, electrons flow from the source and the drain into the channel, and some of them will be captured by the interface traps. When the gate is pulsed again into accumulation, electrons of the channel flow into the drain and the source, but electrons captured in the traps recombine with the majority carriers coming from the substrate. The overall effect is a net charge transfer from the substrate to the source and the drain, measured as dc current ICP proportional to the interface trap density Dt when applying a pulse train of frequency f to the gate, according to ICP = f QCP = f qAG

Dt (E)dE ≈ f qAG Dt ΔE.

(1)

The CP current vanishes as soon as the inversion or accumulation condition is no longer reached during the top or the baselevel voltage, respectively. The CP current as a function of the base-level voltage is a hat-shaped current curve with a constant level proportional to the interface trap density and with rising and falling edges indicative of the threshold VT and the flatband VFB voltages of the transistor, as shown in Fig. 2.

Declercq and Jespers [6] pointed out that the contribution to the CP current is not only due to the SiO2 /Si interface traps but also due to the SiO2 bulk traps. The traps situated in the oxide at some distance from the SiO2 /Si interface can communicate with the semiconductor by tunneling. Bauza and Ghibaudo [15] discussed the characteristics of this current. They neglected the emission of charge and considered that, in an n-MOSFET, a trap placed at a tunneling distance from the interface can capture an electron during the inversion time and a hole during the accumulation time. The contribution to the CP of this recombination process was assessed using (1) Shockely–Read–Hall statistics [16] to study the evolution with time of the trap occupancy factor and (2) Heiman and Warfield’s tunneling model [17] for evaluating the capture cross section as a function of the distance from the interface. They showed that the SiO2 bulk trap density at xmax (maximum interface–trap distance from which a trap can capture both an electron and a hole during one gate pulse) was linearly proportional to dQCP /d ln f . IV. BULK TRAP DENSITY IN STACKED DIELECTRICS In stacked dielectrics such as HfO2 /SiO2 , the voltage applied to the gate produces a large shift in energy of HfO2 defects with respect to the Fermi level. The large difference of the dielectric constants between SiO2 and HfO2 amplifies this displacement [2]. This idea is sketched in the band diagrams of the TiN/HfO2 (2 nm)/SiO2 (1 nm)/Si stack shown in Fig. 3. These diagrams were built from both the silicon surface potential Ψs (VG ) and the voltage across the insulator (VHfO2 + VSiO2 ) obtained from the analysis of capacitance voltage curves with the CVC program [18]. Some of the trap levels which capture electrons during the charging time are afterward shifted above the silicon conduction band during the discharging time. Thus, the electrons may be emitted and contribute to the CP signal. This fact should be taken into account to assess the maximum depth that the CP technique is able to scan inside the stacks. Fig. 3(a) shows the band diagram during charging time tcharge . The traps below the Fermi level (EF = Echarge ) will be occupied by electrons in thermal equilibrium, provided that the traps can see the carriers at the semiconductor surface. Electrons are captured cn in the bulk of the dielectric, and/or holes are emitted ep to the substrate by tunneling processes. The


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Fig. 3. Band diagrams during charging and discharging times of TiN/HfO2 /SiO2 /Si stack. Traps below the channel Fermi level (Echarge ) are filled with electrons during the inversion (charge) period, and traps above the silicon conduction band (Edischarge ) are emptied during the accumulation (discharge) period.

latter mechanism is identical to consider electrons tunneling from the valence band of the Si to the traps. The first-order tunneling model developed by Heiman and Warfield [17] is used in this paper to demonstrate that the SiO2 /HfO2 interface is reached and that the HfO2 traps can be scanned. According to this model [17] and the Shockley–Read–Hall [16] theory, the electron capture cn and hole emission ep rates are given by EF − Ei,0 = σn (x)vth ns (2) kT EV,0 − Et ep (x, Et ) = σp (x)vth NV exp = σp (x)vth p1 kT cn (x) = σn (x)vth ni exp

(3) where ni is the silicon intrinsic concentration, ns is the electron concentration at the surface, NV is the effective density of states at the valence band of the semiconductor, and p1 = NV exp[(EV,0 − Et )/kT ]. The effective cross section of an oxide trap σn(p) is reduced by a factor λn(p) that decreases exponentially with the distance x to which the trap is located from the interface. This parameter λn(p) depends on the barrier offset Φn(p) for electrons (holes) and the effective electron (hole) mass mn(p) inside the dielectric σn(p) (x) = σn(p) (0)e−x/λn(p)

(4)

λn(p) = . 2 2mn(p) Φn(p)

(5)

In this simplified approach, the parameters used to asses the electron-capture and hole-emission cross sections were the usual for SiO2 layers: σn (0) = 5 × 10−14 cm−2 , σp (0) = 10−16 cm−2 , me = 0.5m0 , mp = 0.4m0 , Φn = 3.1 eV, and Φp = 3.8 eV. Under the conditions summarized in Fig. 3, ns = 1 × 1020 cm−3 is about the same order of magnitude as the maximum value of p1 [p1 (Et = Ev ) = NV = 1.83 × 1019 cm−3 ]. However, since the effective cross section for electrons is higher than for holes, the tunneling process from

Fig. 4. Filling of traps nt /Nt as a function of the trap–interface distance for different charging times (3, 30, 56, 10, 180, 300, 560, and 1000 μs). The inset shows the filled depth (nt /Nt > 0.9) as a function of the charging time.

the silicon conduction band is the most likely and dominant charging mechanism. The occupancy of the traps nt /Nt at energy Et and depth x after a time of charge tcharge is given by (6) when all the traps are emptied at tcharge = 0 1 nt (x, Et ) −(cn +ep )tcharge 1 − e . (6) = Nt 1 + e(Et −EF )/kT In Fig. 4, the numerator of (6) is plotted as a function of depth x at different charge times tcharge ’s. The traces in Fig. 4 can be approximated by step functions varying from one to zero at xcharge ∼ λn ln(cn,0 · tcharge ). This charge distance shifts to larger depths with increasing charging time tcharge . It should be noted that the maximum interface–trap distance xcharge , from which a trap can capture an electron, is longer than the interface layer thickness (∼1 nm) for charging times longer than 3 μs, as shown in the inset of Fig. 4. Thus, under these simulation conditions, electrons can be captured inside the high-k dielectric



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layer. As soon as the tunneling front reaches the high-k layer, the capture cross-section values for SiO2 should be replaced by the HfO2 ones which would even favor a deeper penetration since the offset barriers are substantially reduced to 1.5 eV for electrons and 3.1 eV for holes. Fig. 3(b) shows the band diagram of the stack during the discharging time tdischarge in a bias condition wherein (filled) high-k bulk traps can emit electrons into the Si conduction band (EF = Edischarge ). Note that to reach the thermal equilibrium occupancy, the trapped electrons are emitted en toward the silicon conduction band, and holes are captured cp from the silicon valence band by tunneling processes. The former mechanism is equivalent to consider holes tunneling from the Si conduction band to the traps. Again, two mechanisms are involved in the process. The hole capture cp and electron emission en rates [16], [17] are given by

Ei,0 − EF cp (x) = σp (x)vth ni exp = σp (x)vth ps kT Et − EC,0 en (x) = σn (x)vth NC exp = σn (x)vth n1 kT

(7)

Fig. 5. Emptying of traps (Nt − nt )/Nt as a function of the trap–interface distance for different discharging times (3, 30, 56, 10, 180, 300, 560, and 1000 μs). The inset shows the emptied depth ((Nt − nt )/Nt > 0.9) as a function of the discharging time.

(8)

where ps is the hole concentration at the surface, NC is the effective density of states at the conduction band of the semiconductor and, n1 = NC exp[(Et − EV,0 )/kT ]. Fig. 3(b) shows that some of the filled traps in HfO2 during tcharge are now above the silicon conduction band EC,0 (Et > EC,0 ). As it was stated previously, this fact is due to the large difference of the dielectric constants between SiO2 and HfO2 that produces an important shift of the HfO2 bands. According to (7), electron emission exponentially depends on Et − EC,0 . The higher the energies where the traps are placed, the higher the emission rate. For the traps placed at higher energies than EC,0 , the electron emission rate is about the same order as the electron capture rate during the charge period (n1 (Et = EC.0 ) = NC = 2.82 × 1019 cm−3 ) and cannot be neglected in the calculations. Conversely, for the traps placed just 0.2 eV below the silicon conduction band, n1 is reduced to 1 × 1016 cm−3 ; thus, their emission can be neglected, making the hole capture more significant. These competing mechanisms make the discharge a complex process that certainly needs further research to be fully understood. The emptied traps (Nt − nt ) above the Fermi level at energy Et and depth x after a time of discharge tdischarge is given by (9) when all the traps are occupied at tdischarge = 0 1 Nt −nt (x, Et ) −(cp +en )tdischarge 1 − e . = Nt 1+e(EF −Et )/kT (9) In Fig. 5, the numerator of (9) is plotted for different tdischarge ’s. Correspondingly, the maximum interface–trap distance from which a trap placed at Et − EC,0 = 0 can emit an electron is controlled by means of the discharging time tdischarge . As shown in the inset of Fig. 5, for tdischarge > 30 μs, electrons trapped in depths higher than 1 nm, i.e., inside the high-k dielectric, have enough time to tunnel out.

Fig. 6. Trap density (Dt = ICP /qAf ) versus discharge time (tdischarge ) at different tcharge ’s for 2-nm-thick HfO2 on 0.9-nm-thick SiO2 . The vertical arrow indicates the SiO2 /HfO2 transition (tSiO2 ).

A. Spatial Profile As a conclusion, the maximum distance of filling and emptying traps during one gate pulse is controlled independently by the charging and discharging times, respectively. When the charge time tcharge is long enough for electrons to fill HfO2 traps, a change in the discharge time tdischarge enables one to probe how efficiently the traps in the dual-layer stacks are emitting electrons. Since the emission time depends exponentially on the trap distance from the interface, the trap density is estimated from the linear fit of the QCP = ICP /qAf as a function of the log(tdischarge ). B. Spectroscopic CP In addition, the scanned energy during the process is fixed by the low gate voltage (VGL ) and high gate voltage (VGH ), as shown in Fig. 3. This figure shows that during the charging time, electrons fill traps below the energy Echarge fixed by the gate voltage VGH . Afterward, during tdischarge , the trapped CB , fixed by VGL , can be emitted back to the electrons above ESi


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Fig. 7. Schematic illustration of the charge and discharge processes. (a) SiO2 and HfO2 traps are filled by electrons during the charge time. (b) Only SiO2 traps are emptied for the discharge time shorter than 30 μs. (c) SiO2 and HfO2 traps are discharged.

silicon conduction band, recombining with the holes coming from the substrate. Therefore, as the pulse base-level voltage is changed, different energy intervals are filled and emptied of electrons (note that the charging and discharging times have been kept constant). If a defect band is reached during this process, an increase of the CP current should be measured. V. EXPERIMENTAL RESULTS A. Spatial Profile To illustrate the process for determining the spatial profile, the CP current was measured for different tcharge ’s and tdischarge ’s. The details of the setup for the experiment are shown in Fig. 6. The trap density was calculated using (1). The following three regimes are observed in Fig. 6. 1) As the tdischarge increases up to 30 μs, more traps in the SiO2 interface layer can respond to the gate signal. For tcharge > 30 μs, the slope increases, indicating that more traps are contributing to the CP signal (i.e., the scanning depth has reached the SiO2 /HfO2 interface). For the charge time of 3 μs, the slope change in the curve is not detected. This indicates that a small amount of traps inside the high-k dielectric has been filled with electrons during this short charge time in agreement with the calculation performed in the last section (see Fig. 4). 2) For tdischarge 30 μs, the bulk traps in HfO2 are scanned until a saturation level tsat is reached. The saturation level shifts to higher values when charge time increases. 3) Finally, when tdischarge > tsat , no additional traps are measured, and the curves tend to saturate. The scanned traps for the longest tdischarge (∼ 3000 μs) increase with increasing tcharge . This indicates that deeper traps are filled when increasing tcharge . These results are in agreement with the proposed model for capture and emission of charge and with the previous calculations. When tcharge is long enough for electrons to fill HfO2 traps, a sweep of tdischarge allows scanning of the dielectric stack in depth. Fig. 7 shows this idea: (a) During the charging time (transistor in inversion), if the high-k dielectric

Fig. 8. Intersection between low and high discharge time tSiO2 regimes of the CP measurements as a function of gate current at 3.3-V gate voltage.

is separated from the substrate by a very thin SiO2 interfacial layer, the traps are filled with electrons up to a fixed distance inside the HfO2 ; (b) for tdischarge < 30 μs, only the traps close to the SiO2 /Si interface are emptied since there is not enough time to discharge traps inside the high-k dielectric layer; and (c) for tdischarge 30 μs, trapped charges in the SiO2 interlayer and in the high-k can be removed. Finally, if the discharge time is long enough, the saturation regime is reached. In the following paragraphs, further experimental results are presented to strengthen the validity of the technique to assess traps located in both the SiO2 interfacial layer and the high-k dielectric layer. First, a fair correlation between the leakage current at high VG and the discharge time tSiO2 necessary to empty traps placed at the SiO2 /HfO2 interface is obtained. Second, the results of two HfO2 /SiO2 stacks fabricated with different water pulse times in the ALD process are described. A detailed study about the statistical correlation between the leakage current IG and the discharge time tSiO2 on HfO2 /SiO2 stack was performed by extensive measurement on wafer (i.e., “wafer mapping”). One way to independently measure electrically the thickness of interfacial SiO2 is by monitoring the gate leakage IG at very high bias (VG = 3.3 V). In this range, IG is exponentially dependent (i.e., direct tunnelinglike mechanism) on SiO2 , thus giving a reliable estimation of the SiO2 thickness, as shown in Fig. 8 (inset). On similar devices, an estimation of the SiO2 interfacial layer thickness by



Fig. 9. Trap density (Dt = ICP /qAf ) versus base-level voltage (VBL ) at different discharging times varying from 0.2 to 200 μs. Each base level was performed with a charging time of 0.56 μs, amplitude voltage of 2.2 V, and rise and fall times of 100 ns.

discharge time CP has also been considered, i.e., the intersection tSiO2 between low and high discharge time regimes at the CP measurements of Fig. 6. Fig. 8 shows the linear correlation of the tSiO2 discharging time with the IG at very high bias. Note that a decrease in IG indicates a thicker interfacial SiO2 ; thus, a longer tSiO2 discharging time is measured with CP. The clear correlation between independent measurements is a strong support to our CP measurement interpretation. In order to further support our model, the spatial profile of an analogous HfO2 /SiO2 stack but with a 10-s H2 O pulse applied between each cycle of the ALD process was determined in the work of Zahid et al. [19]. It was observed that the spatial profile up to the tdischarge of 30 μs (i.e., up to tSiO2 discharging time) does not suffer any change. However, the slope for the curve for tdischarge 30 μs undergoes a significant increase for the stack subjected to the long water pulse, which is an indication of higher trap density inside the high-k dielectric. This experiment further supports the layer separation achieved by this measurement procedure. In summary, CP measurements with a variable discharge time can be used to separate the contribution of the SiO2 traps from the high-k traps, therefore determining the spatial profile of the traps in stacked structures.

B. Spectroscopic CP Fig. 9 shows the trap density (Dt = ICP /qf A) calculated from the base-level CP current at different discharge times for the HfSiON/SiO2 stack described in Section II. A gate pulse with an amplitude of 2.2 V was applied with a base-level sweep from −1.8 to 0.5 V. The discharge time was varied from 0.2 to 200 μs. In all cases, the charge time was 0.56 μs. It should be noted that this time is shorter than the one used for the previous experiment. However, the charging voltage VGH was much higher, thus allowing an efficient trapping of electrons inside the high-k dielectric layer. For short discharge times, the CP signal in Fig. 9 shows the usual hat-shaped curve due to SiO2 interface traps. However, an increase of current at VBL = −1.5 V, and

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Fig. 10. Trap density (Dt = ICP /qAf ) versus discharge time (tdischarge ) for 3-nm-thick HfOSiN on 0.9-nm-thick SiO2 . The vertical arrow indicates the SiO2 /HfOSiN transition (tSiO2 ). (Solid lines) The linear fittings for large and short discharge times are also shown, together with the R2 coefficients. The prolongations of the linear fitting are plotted with dashed lines.

two superimposed bands at −0.55 and −0.05 V are detected for longer discharge times. The former is due to the leakage current. For these devices, the leakage current is about 1.5 nA at VG = −1.5 V, and the CP current is proportional to the frequency f of the signal according to (1) and is then inversely proportional to the discharge time tdischarge . For the shortest discharge time used in this experiment, the CP current is about 20 nA, which means that it is one order of magnitude higher than the leakage current. However, when the discharge time is increased, the CP current is reduced to values less than 1 nA, which means that it is reduced to a value less than the leakage current. In conclusion, the CP current is dropped by the leakage current at so high voltage (in absolute value). The two bands at the base-level voltages of −0.55 and −0.05 V also become evident as the discharge time increases. However, the leakage current at these voltages is well below the CP current. In Fig. 10, the trap density at a base voltage of −0.55 V is plotted as a function of the discharge time. It can be observed that the slope is steeper for the largest discharge times than for the shortest ones. The saturation regime was observed for the band at −0.05 V when the discharge time was lengthened, but not for the other band due to the effect of the leakage current. These observations point to the fact that these bands are due to traps inside the HfSiON layer. Thus, the resultant CP signal is the usual one due to interface traps plus two superimposed bands. These results may be explained by the presence of two defect levels located at the high-k dielectric. These defect levels are effectively charged and discharged when the low-level voltage reaches the values of −0.55 and −0.05 V (i.e., when the high-level voltage reaches the values of 1.65 and 2.15 V). To calculate the position of the defect levels, it is necessary to construct the energy band diagram and then to determine the voltage drops across the silicon, SiO2 , and HfSiON. In the band diagram shown in Fig. 11, the voltage drops are again calculated from the capacitance–voltage curve and using the CVC program [18]. Fig. 11 shows the band diagrams during


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Fig. 11. Calculated energy band diagrams of the TiN/HfSiON/SiO2 /Si gate stack. (a) Defect band at 0.40 eV above the Si conduction band is charged efficiently at VG = 1.65 V. (b) the defect band at 0.85 eV above the Si conduction band is charged at VG = 2.15 V.

the charging time for the voltages where the CP reaches the maximum. The calculated trap energy levels are situated at 0.40 and 0.85 eV above the Si conduction band. In the literature, several groups have previously postulated the existence of several defect energy levels within HfO2 . For instance, the leakage current through the HfO2 /SiO2 gate stacks has been explained by Frenkel–Poole hopping in the HfO2 layer, where a shallow energy trap level around 0.35 eV [20] or 0.5 eV [21] with respect to the HfO2 conduction band has been proposed. Also, a defect band located at 1.2 eV below the HfO2 conduction band has been pointed out in trapping–detrapping experiments [22]. In all these cases, the results have been attributed to oxygen vacancies according to theoretical calculations [23]–[25]. In those simulation works, different energy levels for the different charge states of the O vacancies are given. In this paper, we have shown that these previous results are compatible, since two defect bands have been simultaneously detected by means of base-level CP and independently controlling the discharging time and the charging time. Indeed, Cartier et al. [26] have also found two electron trap levels in HfO2 using amplitude sweep CP. VI. CONCLUSION This paper shows that the CP technique is an ideal tool for the study of defects in the high-k layer of stacked dielectrics. The improvements introduced in the procedure and interpretation of the CP measurements make it possible to determine the spatial profile of traps and to detect defect levels in the high-k dielectric. By means of the spatial profile of the traps, a clear separation of the traps in the SiO2 interlayer from the traps in the high-k dielectric does allow a thorough study of trap generation in both constituent layers. The spectroscopic character of the technique does point out the existence of two defect bands in the high-k dielectric, with one of them being situated at 0.40 eV and the other one at 0.85 eV from the Si conduction band. R EFERENCES [1] International Technology Roadmap for Semiconductors, Semicond. Ind. Assoc., San Jose, CA, 2001. [Online]. Available: http://public.itrs.net [2] A. Kerber, E. Cartier, L. Pantisano, R. Degraeve, G. Groeseneken, H. E. Maes, and U. Schwalke, “Charge trapping in SiO2 /HfO2 gate dielectrics: Comparison between charge-pumping and pulsed ID –VG ,” Microelectron. Eng., vol. 72, no. 1–4, pp. 267–272, Apr. 2004.

[3] E. San Andrés, L. Pantisano, S. Severi, L. Trojman, I. Ferain, M. Toledano-Luque, M. Jurczak, G. Groeseneken, S. De Gendt, and M. Heyns, “Mobility extraction using RFCV for 80 nm MOSFET with 1 nm EOT HfSiON/TiN,” Microelectron. Eng., vol. 84, no. 9/10, pp. 1878–1881, Oct. 2007. [4] R. Degraeve, A. Kerber, P. Roussel, E. Cartier, T. Kauerauf, L. Pantisano, and G. Groeseneken, “Effect of bulk trap density on HfO2 reliability and yield,” in IEDM Tech. Dig., 2003, pp. 935–938. [5] G. Groeseneken, H. E. Maes, N. Beltran, and R. F. de Keersmaecker, “A reliable approach to charge-pumping measurements in MOS transistors,” IEEE Trans. Electron Devices, vol. ED-31, no. 1, pp. 42–53, Jan. 1984. [6] M. Declercq and P. Jespers, “Analysis of interface properties in MOS transistors by means of ‘charge pumping’ measurements,” Rev. HF, vol. 9, no. 8, pp. 244–253, 1974. [7] M. B. Zahid, R. Degraeve, T. Kauerauf, G. Groeseneken, and J. F. Zhang, “Investigation of channel-length dependent time-tobreakdown (tBD) with variable frequency charge pumping,” in Proc. IEEE 36th Int. Conf. SISC, 2005, pp. 88–89. [8] D. Heh, C. D. Young, G. A. Brown, P. Y. Hung, A. Diebold, G. Bersuker, E. M. Vogel, and J. B. Bernstein, “Spatial distributions of trapping centers in HfO2 /SiO2 gate stacks,” Appl. Phys. Lett., vol. 88, no. 15, p. 152 907, Apr. 2006. [9] D. Heh, C. D. Young, G. A. Brown, P. Y. Hung, A. Diebold, E. M. Vogel, J. B. Bernstein, and G. Bersuker, “Spatial distributions of trapping centers in HfO2 /SiO2 gate stack,” IEEE Trans. Electron Devices, vol. 54, no. 6, pp. 1338–1345, Jun. 2007. [10] C. D. Young, D. Heh, S. V. Nadkarni, R. Choi, J. J. Peterson, J. Barnett, B. H. Lee, and G. Bersuker, “Electron trap generation in high-k gate stacks by constant voltage stress,” IEEE Trans. Device Mater. Rel., vol. 6, no. 2, pp. 123–131, Jun. 2006. [11] C. Leroux, G. Ghibaudo, X. Garros, G. Reimbold, B. Guillaumot, and F. Martin, “Characterization and modeling of hysteresis phenomena in high K dielectrics,” in IEDM Tech. Dig., 2004, pp. 737–740. [12] M. B. Zahid, R. Degraeve, L. Pantisano, J. F. Zhang, and G. Groeseneken, “Defects generation in SiO2 /HfO2 studied with variable tcharge − tdischarge charge pumping (VT2 CP),” in Proc. IRPS, 2007, pp. 55–60. [13] F. De Smedt, C. Vinckier, I. Cornelissen, S. De Gendt, and M. Heyns, “A detailed study on the growth of thin oxide layers on silicon using ozonated solutions,” J. Elecrochem. Soc., vol. 147, no. 3, pp. 1124–1129, Mar. 2000. [14] J. S. Brugler and P. G. Jespers, “Charge pumping in MOS devices,” IEEE Trans. Electron Devices, vol. ED-16, no. 3, pp. 297–302, Mar. 1969. [15] D. Bauza and G. Ghibaudo, “Analytical study of the contribution of fast and slow oxide traps to the charge pumping current in MOS structures,” Solid State Electron., vol. 39, no. 4, pp. 563–570, Apr. 1996. [16] W. Shockley and W. T. Read, “Statistics of the recombinations of holes and electrons,” Phys. Rev., vol. 87, no. 5, pp. 835–842, Sep. 1952. [17] F. P. Heiman and G. Warfield, “The effects of oxide traps on the MOS capacitance,” IEEE Trans. Electron Devices, vol. ED-12, no. 4, pp. 167–178, Apr. 1965. [18] N. Yang, W. K. Henson, J. R. Hauser, and J. J. Wortman, “Modeling study of ultrathin gate oxides using direct tunneling current and capacitance–voltage measurements in MOS devices,” IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1464–1471, Jul. 1999. [19] M. B. Zahid, R. Degraeve, J. F. Zhang, and G. Groeseneken, “Impact of process conditions on interface and high-κ trap density studied by variable tcharge −tdischarge charge pumping (VT2 CP),” Microelectron. Eng., vol. 84, no. 9/10, pp. 1951–1955, Sep./Oct. 2007. [20] G. Ribes, S. Bruyere, D. Roy, C. Parthasathy, M. Müller, M. Denais, V. Huard, T. Skotnicki, and G. Ghibaudo, “Origin of Vt instabilities in high-k dielectrics Jahn–Teller effect or oxygen vacancies,” IEEE Trans. Device Mater. Rel., vol. 6, no. 2, pp. 132–135, Jun. 2006. [21] Z. Xu, M. Houssa, S. De Gendt, and M. Heyns, “Polarity effect on the temperature dependence of leakage current through HfO2 /SiO2 gate dielectric stacks,” Appl. Phys. Lett., vol. 80, no. 11, pp. 1975–1977, Mar. 2002. [22] S. Zafar, A. Kumar, E. Gusev, and E. Cartier, “Threshold voltage instabilities in high-k gate dielectric stacks,” IEEE Trans. Device Mater. Rel., vol. 5, no. 1, pp. 45–63, Mar. 2005. [23] K. Xiong, J. Robertson, M. C. Gibson, and S. J. Clark, “Defect energy levels in HfO2 high-dielectric constant gate oxide,” Appl. Phys. Lett., vol. 87, no. 18, pp. 183 505-1–183 505-3, Oct. 2005. [24] J. L. Gavartin, D. Muñoz-Ramo, L. Shluger, G. Bersuker, and B. H. Lee, “Negative oxygen vacancies in HfO2 as charge traps in high-k stacks,” Appl. Phys. Lett., vol. 89, no. 8, pp. 82 908-1–82 908-3, Aug. 2006.



[25] N. Umezawa, K. Shiraishi, T. Ohno, M. Boero, H. Watanabe, K. Toriid, K. Yamabe, K. Yamada, and Y. Nara, “Unique behavior of F-centers in high-k Hf-based oxides,” Phys., B Condens. Matter, vol. 376/377, pp. 392–394, Apr. 2006. [26] E. Cartier, B. P. Linder, V. Narayanan, and V. K. Paruchuri, “Fundamental understanding and optimization of PBTI in nFETs with SiO2 /HfO2 gate stack,” in IEDM Tech. Dig., 2006, pp. 1–4.

María Toledano-Luque was born in Madrid, Spain, in 1980. She received the M.Sc. degree in electrical engineering and the Ph.D. degree in high-k dielectrics deposition and characterization from the Universidad Complutense de Madrid (UCM), Madrid, in 2003 and 2008, respectively. She was with IMEC, Leuven, Belgium, as a European Ph.D. student on the electrical characterization of Hf-based gate oxides during 2006. In 2003, she was a member of the “Láminas Delgadas y Microelectrónica” Research Group, UCM, where she has been with the Dpto. Física Aplicada III (Electricidad y Electrónica), Facultad de Ciencias Físicas, as an Assistant Professor since 2007.

Robin Degraeve received the M.Sc. degree in electrical engineering from the University of Gent, Gent, Belgium, in 1992 and the Ph.D. degree from the Catholic University of Leuven, Leuven, Belgium, in 1998. He has been with the CMOS Reliability Group, Interuniversity Microelectronics Center (IMEC), Leuven, Belgium, since 1992, where he is currently a Senior Researcher. His work has been focusing on reliability aspects of thin insulating layers under electrical stress. His current interests and activities include hot-carrier-related reliability issues in MOSFETs, the study of the physics of degradation and breakdown phenomena in gate oxide films, the reliability of flash memory devices, the reliability of ultrathin oxide and oxynitride layers for VLSI technologies, and the reliability of high-k materials as MOSFET gate insulators for future CMOS generations.

Mohammed B. Zahid received the University Diploma in electrical and computer science from the University of Technologies (IUT), Cachan, France, in 2001, the B.S. degree in electrical engineering and the M.S. degree in microelectronics from Liverpool John Moores University (LJMU), Liverpool, U.K., in 2002 and 2003, respectively, and the Ph.D. degree from LJMU in collaboration with the Reliability, Electrical Characterization and Modeling Group, Silicon Process and Device Technology Division, Interuniversity Microelectronics Center (IMEC), Leuven, Belgium, in 2006. He is currently with IMEC. His current research interest during his Postdoc includes the technology, electrical characterization, reliability of advanced gate dielectric for future generation of devices (nonvolatile memory).

Luigi Pantisano was born in Parma, Italy. He received the Laurea degree (in cooperation with the Reliability Laboratory, ETH, Zurich, Switzerland) and the Ph.D. degree in electrical engineering from the University of Padova, Padova, Italy, in 1996 and 2000, respectively. In 2000, he was with Bell Laboratories, Lucent Technologies, Murray Hill, NJ, working toward the impact of plasma charging damage on RF CMOS devices. Since 2001, he has been a Senior Scientist with the Interuniversity Microelectronics Center, Leuven, Belgium, working on high-k gate dielectrics for CMOS technologies. He has more than 120 papers in the fields of plasma damage, RF measurements, and reliability and electrical characterization of novel high-k devices.

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Enrique San Andrés was born in Madrid, Spain, in 1976. He received the M.S. degree in physics (electronics branch) and the Ph.D. degree in physics (in the area of high-k deposition and characterization) from the Universidad Complutense de Madrid (UCM), Madrid, in 1999 and 2004, respectively. In 2001, he was with the Departamento de Física Aplicada III (Electricidad y Electrónica), UCM, as an Assistant Professor. In 2005–2006, he was with IMEC, Leuven, Belgium, as a Postdoctoral Researcher in the field of advanced RF characterization of MOSFET devices. He is currently with the Dpto. Física Aplicada III (Electricidad y Electrónica), Facultad de Ciencias Físicas, UCM, as a Doctor Assistant Professor. He has authored or coauthored more than 35 international journal papers and more than 15 conference contributions.

Guido Groeseneken (S’80–M’80–SM’95–F’05) received the M.Sc. degree in electrical and mechanical engineering and the Ph.D. degree in applied sciences from the Katholieke Universiteit Leuven (K.U.Leuven), Leuven, Belgium, in 1980 and 1986, respectively. Since 1987, he has been with the R&D Laboratory, Interuniversity Microelectronics Center (IMEC), Leuven, where he is responsible for the research in reliability physics for deep-submicrometer CMOS technologies. Since October 2005, he has also been responsible for the IMEC Post CMOS Nanotechnology Program within IMEC’s core partner research program. In 2007, he became an IMEC Fellow. Since 2001, he has also been a Professor with the K.U.Leuven. He has made contributions to the fields of nonvolatile semiconductor memory devices and technology, reliability physics of VLSI technology, hot-carrier effects in MOSFETs, time-dependent dielectric breakdown of oxides, ESD protection and testing, plasma-processing-induced damage, electrical characterization of semiconductors, and characterization and reliability of high-k dielectrics. He has authored or coauthored more than 300 publications in international scientific journals and in international conference proceedings and three book chapters, and he is the holder of seven patents in his fields of expertise. Dr. Groeseneken has served as a technical program committee member of several international scientific conferences, among which the IEEE International Electron Device Meeting (IEDM), the European Solid State Device Research Conference, the International Reliability Physics Symposium, the IEEE Semiconductor Interface Specialists Conference, and the EOS/ESD Symposium. From 2000 to 2002, he also acted as a European Arrangements Chair of IEDM. In 2005, he was the General Chair of the Insulating Films on Semiconductor Conference, Leuven.

Stefan De Gendt received the Ph.D. degree in chemistry from the University of Antwerp, Antwerpen, Belgium. He has been with the Interuniversity Microelectronics Center (IMEC), Leuven, Belgium, since 1996. His initial research interest dealt with the ultraclean processing of silicon substrates, where he studied the impact of metallic and organic contaminants and the use of ozonated chemistries and worked on the development of analytical techniques for trace contaminant analysis. Since 2000, he has been acting as the Program Manager and the Principal Scientist for high-k and metal-gated research. Recently, he was appointed as the Program Manager for IMEC’s Post CMOS NANO Program. He is also a Professor in physical and analytical chemistry with the Department of Chemistry, Katholieke Universiteit Leuven, Leuven. He has authored or coauthored more than 130 peer-reviewed journal papers and 180 conference contributions (of which 50 are by invitation for the team).
