Int’l Conf. on Computer & Communication Technology | ICCCT’10 |
New Low-Power Techniques: Leakage Feedback with Stack & Sleep Stack with Keeper Pankaj Kr. Pal#, Rituraj S. Rathore#, Ashwani K.Rana*, Gaurav Saini# #
M.Tech (VDAT), E&CED, National Institute Of Technology, Hamirpur (H.P.) *
AP, E&CED, National Institute Of Technology, Hamirpur (H.P.) 1
[email protected],
[email protected]
3
[email protected],
[email protected]
Abstract - For the most recent CMOS feature sizes (e.g., 90 nm and 65 nm), leakage power dissipation has become an overriding concern for VLSI circuit designers. ITRS reports that leakage power dissipation may come to dominate total power consumption [1]. We are doing comparable analysis of different low power, leakage current reduction techniques like SLEEP approach, STACK, ZIGZAG & some new techniques like , SLEEPY–STACK, LEAKAGE FEEDBACK approach and SLEEPY KEEPER techniques and , after that to combine the advantages of above written techniques, we propose two novel approaches from simulation study, named “Leakage Feedback with Stack (LFS)” & “Sleep Stack with Keeper (SSK)” which reduces leakage current while saving exact logic state. But based on simulations result with a full adder circuit, “Sleep-Stack with keeper approach” achieves up to 76-80 % less power consumption.
Keywords— low power design, leakage reduction, sleep, stack, sleepy-stack, keeper.
I. INTRODUCTION Power consumption is one of the top concerns of Very Large Scale Integration (VLSI) circuit design, for which Complementary Metal Oxide Semiconductor (CMOS) is the primary technology. Today’s focus on low power is not only because of the recent growing demands of mobile applications. Even before the mobile era, power consumption has been a fundamental problem. To solve the power dissipation problem, many researchers have proposed different ideas from the device level to the architectural level and above. However, there is no universal way to avoid tradeoffs between power, delay and area, and thus designers are required to choose appropriate techniques that satisfy application and product needs. Power consumption of CMOS consists of dynamic and static components. Dynamic power is consumed when transistors are switching, and static power is consumed regardless of transistor switching. Dynamic power
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FRQVXPSWLRQ ZDV SUHYLRXVO\ DW ȝP WHFKQRORJ\ DQG above) the single largest concern for low-power chip designers since dynamic power accounted for 90% or more of the total chip power. Therefore, many previously proposed techniques, such as voltage and frequency scaling, focused on dynamic power reduction. However, as the feature size VKULQNV WR ȝP DQG ȝP VWDWLF SRZHU KDV EHFRPH D great challenge for current and future technologies. Based on the International technology roadmap for semiconductors (ITRS) [1], Kim et al. report that sub-threshold leakage power dissipation of a chip may exceed dynamic power dissipation at the 65nm feature size [11]. One of the main reasons causing the leakage power increase is increase of sub-threshold leakage power. When technology feature size scales down, supply voltage and threshold voltage also scale down. Sub-threshold leakage power increases exponentially as threshold voltage decreases. Furthermore, the structure of the short channel device lowers the threshold voltage even lower. In addition to sub-threshold leakage, another contributor to leakage power is gate-oxide leakage power due to the tunnelling current through the gateoxide insulator. Since gate-oxide thickness will be reduced as the technology decreases, in nano-scale technology, gateoxide leakage power may be comparable to sub-threshold leakage power if not handled properly. However, we assume other techniques will address gate-oxide leakage; for example, high-k dielectric gate insulators may provide a solution to reduce gate-leakage [11]. Therefore, this work focuses on reducing sub-threshold leakage power consumption. II. PREVIOUS WORK We here review previously proposed circuit level approaches for sub-threshold leakage power reduction. The most well-known traditional approach is the sleep approach [2-3]. In the sleep approach, both (i) an additional "sleep" PMOS transistor is placed between V DD and the pull-up
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Int’l Conf. on Computer & Communication Technology | ICCCT’10 | network of a circuit and (ii) an additional "sleep" NMOS transistor is placed between the pull-down network and GND. These sleep transistors turn off the circuit by cutting off the power rails. Fig. 1 shows its structure. The sleep transistors are turned on when the circuit is active and turned off when the circuit is idle. By cutting off the power source, this technique can reduce leakage power effectively. However, output will be floating after sleep mode, so the technique results in destruction of state plus a floating output voltage. A variation of the sleep approach, the zigzag approach, reduces wake-up overhead caused by sleep transistors by placement of alternating sleep transistors assuming a particular pre-selected input vector [4]. In fig. 2, we assume that, in sleep mode, the input of the logic is ‘0’ and each logic stage reverses its input signal, i.e., the output is ‘1’ if the input is ‘0,’ and the output is ‘0’ is the input is ‘1.’ If the output is ‘1,’ then a sleep transistor is added to the pull-down network; if the output is ‘0’, then a sleep transistor is added to the pull-up network. Thus, the zigzag approach uses fewer sleep transistors than the original sleep approach. Furthermore, this approach still results in destruction of state (i.e., state is set to the particular pre-selected input vector), although the problem of floating output voltage is eliminated.
Fig. 1 Sleep approach
Fig. 3 Stack Approach
Fig. 4 Sleepy Stack Approach
Then sleep transistors are added in parallel to one of the divided transistors. Fig. 4 shows its structure. During sleep mode, sleep transistors are turned off and stacked transistors suppress leakage current while saving state. Each sleep transistor, placed in parallel to the one of the stacked transistors, reduces resistance of the path, so delay is decreased during active mode. However, area penalty is a significant matter for this approach since every transistor is replaced by three transistors and since additional wires are added for S and S’, which are sleep signals.
Fig. 2 Zigzag approach Fig. 5 Leakage feedback approach
Another technique for leakage power reduction is the stack approach, which forces a stack effect by breaking down an existing transistor into two half size transistors [5]. Fig. 3 shows its structure. When the two transistors are turned off together, induced reverse bias between the two transistors results in sub-threshold leakage current reduction.
Fig. 6 Sleepy Keeper approach
The leakage feedback approach is based on the sleep approach. However, the leakage feedback approach uses two additional transistors to maintain logic state during sleep mode, and the two transistors are driven by the output of an inverter which is driven by output of the circuit implemented utilizing leakage feedback [14]. As shown in Figure 5, a PMOS transistor is placed in parallel to the sleep transistor (S) and a NMOS transistor is placed in parallel to the sleep transistor (S'). The two transistors are driven by the output of the inverter which is driven by the output of the circuit.
The sleepy stack approach combines the sleep and stack approaches [6-7]. The sleepy stack technique divides existing transistors into two half size transistors like the stack approach.
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Int’l Conf. on Computer & Communication Technology | ICCCT’10 | k (high dielectric constant) gate insulators [9]. In any case, this papers targets reduction of the sub-threshold leakage component of static power consumption; other approaches should be considered for reduction of gate oxide leakage. Do please note, however, that all results reported in this paper include all sources of leakage power. With application of dual threshold voltage (V th ) techniques, the sleep, zigzag and sleepy stack approaches result in orders of magnitude subthreshold leakage power reduction [7] but in this paper, we are not using dual V th approach. The major advantage of the sleepy stack approach over the sleep and zigzag approaches is that the sleepy stack approach saves exact logic state. However, the sleepy stack approach carries a non-trivial penalty: each transistor in the original, base case, traditional CMOS design results in three transistors in the sleepy stack equivalent. The goal of our new approach is to achieve the benefit of all above written techniques, and now we propose two novel approaches, named “leakage feedback with stack” & “sleep stack with keeper” which reduces leakage current while saving exact logic state.
During sleep mode, sleep transistors are turned off and one of the transistors in parallel to the sleep transistors keep the connection with the appropriate power rail. The basic problem with traditional CMOS is that the transistors are used only in their most efficient, and naturally inverting, way: namely, PMOS transistors connect to V DD and NMOS transistors connect to GND. It is well known that PMOS transistors are not efficient at passing GND; similarly, it is well known that NMOS transistors are not efficient at passing V DD . However, to maintain a value of ‘1’ in sleep mode, given that the ‘1’ value has already been calculated, the sleepy keeper approach uses this output value of ‘1’ and an NMOS transistor connected to V DD to maintain output value equal to ‘1’ when in sleep mode. As shown in Figure 6, an additional single NMOS transistor placed in parallel to the pull-up sleep transistor connects V DD to the pull-up network. When in sleep mode, this NMOS transistor is the only source of V DD to the pull-up network since the sleep transistor is off. Similarly, to maintain a value of ‘0’ in sleep mode, given that the ‘0’ value has already been calculated, the sleepy keeper approach uses this output value of ‘0’ and a PMOS transistor connected to GND to maintain output value equal to ‘0’ when in sleep mode. As shown in fig. 6, an additional single PMOS transistor placed in parallel to the pull-down sleep transistor is the only source of GND to the pull-down network which is the dual case of the output ‘1’ case explained above.
IV. LFS & SLEEP STACK WITH KEEPER In this section, we describe our new leakage reduction techniques in which we call the first one “leakage feedback with stack (LFS)” approach and other is “sleep-stack with keeper”. This section explains the structure of the leakage feedback with stack approach and sleep-stack with keeper.
For this approach to work, all that is needed is for the NMOS connected to V DD and the PMOS connected to GND to be able to maintain proper logic state. This seems likely to be possible as other researchers have described ways to use far lower V DD values to maintain logic state. For example, Flautner et al. propose some significantly reduced V DD values sufficient to maintain state [10]. For the sleep, zigzag, sleepy stack and leakage feedback approaches, sleepy keeper approach, dual Vth technology can be applied to obtain greater leakage power reduction. Since high-Vth results in less leakage but lowers performance, highVth is applied only to leakage reduction transistors, which are sleep transistors, and any transistors in parallel to the sleep transistors; on the other hand, low-Vth is applied to the remaining transistors to maintain logic performance [2-7].
Fig. 7 Leakage feedback with stack
III. MOTIVATION
In first technique i.e. leakage feedback with stack, we are combining the two low power techniques or taking advantage of two techniques i.e. leakage feedback approach due to less transistor than sleepy-stack in which we replaces each transistor in base case into three transistors, and ultra low power technique i.e. Stack approach. This is shown in fig. 7
Currently, sub-threshold leakage seems to be the dominant contributor to overall leakage power [8]. Another possible contributor to leakage power is gate-oxide leakage. A possible solution widely reported is the potential use of high-
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Int’l Conf. on Computer & Communication Technology | ICCCT’10 | In second approach i.e. sleep-stack with keeper, we are combining the three different low power leakage reduction techniques i.e. sleep transistors, stack approach with keeper as shown in fig 8.
Technology
ȝ
0.ȝ
ȝ
ȝ
V DD
1.0 V
1.3 V
1.6 V
2.0 V
VI. SIMULATION RESULTS We measure only the average power consumption for nine design approaches i.e. the base case, sleep, zigzag, stack, sleepy stack, leakage feedback and sleepy keeper approaches with newly proposed approaches named leakage feedback with stack and sleep stack with keeper. The static power measurement for the leakage feedback approach by using same method for all other approaches resulted in 10X greater than the result of the base case. For this reason, we do not show results for the leakage feedback approach. A 1-bit full-adder (mirror design) is chosen to compare our leakage feedback with stack & sleep stack approach to the other considered approaches for four different technologies. The simulations table for 1-bit full-adder is shown below in table 2. Table 2 Average power consumed in watts
Fig. 8 Sleep stack with keeper approach
V. EXPERIMENTAL METHODOLOGY In order to compare the results of our new approach with prior leakage reduction approaches, experiments include all the techniques discussed in section 2, namely, stack, sleep, zigzag, sleepy stack and leakage feedback & sleepy-keeper approaches. In addition, we consider a base case and the newly proposed novel approaches, named “leakage feedback with stack” & “sleep stack with keeper”. Schematics are designed for all considered techniques using schematics editor i.e. S-EDIT in T-SPICE targeting TSMC ȝPȝPȝPDQGȝPWHFKQRORJ\6FKHPDWLFV are used to obtain netlists of test circuits, and the netlists are used to simulate and test performance. Schematics are created based on TSMC process parameters. Netlists of test circuits for different techniques are extracted from the schematics. The netlists are modified to fit into all silicon technologies targeted using the TSMC process as well as the Berkeley Predictive Technology Model (BPTM) [12][13] approach for 0.18, 0.13, 0. DQG ȝP processes. We use Tanner-SPICE i.e. T-SPICE simulation to estimate only average power consumption. The supply voltages used by the technologies are tabulated in table 1. Table 1.Supply voltages for different technologies
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Techniques
70 nm
100 nm
130 nm
180 nm
Base Case
3.86E-08
8.90E-08
2.29E-07
6.35E-07
Sleep
1.20E-08
3.87E-08
8.85E-08
2.27E-07
Zigzag
1.46E-08
4.47E-08
9.89E-08
2.55E-07
Stack
1.49E-08
4.24E-08
9.74E-08
3.08E-07
Sleepy-stack
1.79E-08
1.34E-07
1.34E-07
3.75E-07
Sleepy-keeper
1.64E-08
5.45E-08
1.27E-07
3.63E-07
Sleepy-stackkeeper
7.91E-09
2.79E-08
6.39E-08
1.57E-07
LF with Stack
1.69E-08
5.21E-08
1.29E-07
3.32E-07
Now we are showing the simulations results of 1-bit full adder circuit with four different technology generations for all above discussed eight techniques i.e. base case, sleep, zigzag, stack, sleepy stack, leakage feedback and sleepy keeper approaches with newly proposed approaches in forms of graphs by which we can easily see the average power consumption.
Int’l Conf. on Computer & Communication Technology | ICCCT’10 |
Fig. 10 Average power consumed chart for rest technologies
VII. CONCL USION From the model of the sleepy stack inverter [6], we observe that the sleepy stack inverter can reduce delay by 25%, which alternatively can be used to increase V th by 69%. Using this increased threshold voltage, the sleepy stack inverter can potentially achieve a large (e.g. 10X) leakage power reduction compared to the forced stack inverter. Other proposed technique is leakage feedback with stack effect, it reduces power comparable to sleepy stack and it is also better area as well as delay. We are find that the proposed technique i.e. sleepy- stack with keeper is the better technique for leakage power reduction but little bit area and delay overhead but compared with other power reduction techniques like sleepy stack, it takes less numbers of transistor, so because of this, technique has less area than sleepy stack approach. It reduces almost 80% of static or leakage power. For our future work, we plan to investigate about the exact delay and area in these proposed techniques.
Fig. 9 Average power consumed chart for 70 nm
REFERENCES
300
[1]
International Technology Roadmap for Semiconductors Semiconductor Industry Association, http://public.itrs.net, 2007.
by
[2]
S. Mutoh et al., “1-V Power Supply High-speed Digital Circuit Technology with Multi-threshold-Voltage CMOS,” IEEE Journal of Solis-State Circuits, Vol. 30, No. 8, pp. 847-854, August 1995.
[3]
M. Powell, S.-H. Yang, B. Falsafi, K. Roy and T. N. Vijay kumar, “Gated-V dd : A Circuit Technique to Reduce Leakage in Deep submicron Cache Memories,” International Symposium on Low Power Electronics and Design, pp. 90-95, July 2000.
Int’l Conf. on Computer & Communication Technology | ICCCT’10 | [4]
K.-S. Min, H. Kawaguchi and T. Sakurai, “Zigzag Super Cut-off CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-gating Scheme in Leakage Dominant Era,” IEEE International Solid-State Circuits Conference ,pp. 400-401, February 2003.
[5]
Z. Chen, M. Johnson, L. Wei and K. Roy, “Estimation of Standby Leakage Power in CMOS Circuits Considering Accurate Modelling of Transistor Stacks,” International Symposium on Low Power Electronics and Design, pp. 239-244, August 1998.
[6]
J.C. Park, V. J. Mooney III and P. Pfeiffenberger, “Sleepy Stack Reduction of Leakage Power,” Proceeding of the International Workshop on Power and Timing Modelling, Optimization and Simulation, pp. 148-158, September 2004.
[7]
J. Park, “Sleepy Stack: a New Approach to Low Power VLSI and Memory,” Ph.D. Dissertation, School of Electrical and Computer Engineering, Georgia Institute of Technology, 2005. [Online].Available http://etd.gatech.edu/theses
[8]
A. Kahng, S. Muddu, P. Sharma, “Defocus-aware leakage estimationand control,” International Symposium on Low Power Electronicsand Design, pp. 263-268, Aug. 2005.
[9]
G. Ribes, J. Mitard, M. Denais, S. Bruyere, F. Monsieur, C.Parthasarathy, E. Vincent, and G. Ghibaudo, “Review on high-k dielectrics reliability issues,” IEEE Transactions on Device and materials Reliability, Vol. 5, Issue 1, pp. 5-19, March 2005.
[10]
K. Flautner, N. S. Kim, S. Martin, D. Blaauw, and T. Mudge, “Drowsy Caches: Simple Techniques for Reducing Leakage Power,” Proceedings of the International Symposium on Computer Architecture, pp. 148-157, May 2002
[11] Kim, N., Austin, T., Baauw, D., Mudge, T., Flautner, K., Hu, J., Irwin, M., Kandemir, M., And Narayanan, V., “Leakage Current: Moore’s Law Meets Static Power,” Ieee Computer, Vol. 36, Pp. 68–75, December 2003. [12] Berkeley Predictive Technology Model, http://www.eas.asu.edu/~ptm/. [13]
Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu., “New paradigm of predictive MOSFET and interconnect modelling for early circuit design,” Proceeding of IEEE Custom Integrated Circuits Conference, pp. 201-204, June 2000.
[14] J. Kao and A. Chandrakasan, "MTCMOS sequential circuits," Proceedings of European Solid-State Circuits Conference, pp 332335, September 2001.
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