New Self-checking Output-Duplicated Booth Multiplier with High Fault ...

New Self-checking Output-Duplicated Booth Multiplier with High Fault Coverage for Soft Errors D. Marienfeld

E. S. Sogomonyan ∗

V. Ocheretnij

M. Gössel

University of Potsdam, Fault Tolerant Computing Group, 14439 Potsdam, Germany E-mail: dmarien | egor | vitalij | mgoessel @cs.uni-potsdam.de Abstract In this paper a new self-checking code-disjoint Booth-2 multiplier with an improved error detection and with a reduced area overhead is proposed. Compared to the 64 × 64 multiplier without error detection the area for the proposed multiplier increases for the different implementations only by 23%-30%. Especially for soft errors the error detection capability is significantly improved. All even or odd (soft) errors in the output registers are detected.

1. Introduction Due to the rapidly shrinking dimensions and to the diminishing voltage levels VLSI circuits are becoming more and more sensitive to temporary faults and errors [1] and soft errors are of growing importance. If a transient fault occurs in a single node or in several nodes of the combinational part of the circuit the transient fault results only in a soft error if a single erroneous bit or several erroneous bits due to this fault are captured in a latch or register. According to [2] and [3] the effects of transient faults in the combinational parts of a circuit are limited by the following conditions: 1. To capture a single-bit soft error in a latch there must be a sensitized path from the location of the transient fault to the latch. To capture a multiple-bit soft error in the corresponding latches there must be some simultaneously sensitized paths from the locations of the transient fault to the corresponding latches (logic condition). Thereby a simultaneous sensitization of several different paths is a rare situation. This is especially true for circuits of realistic size. ∗ Guest

professor at the University of Potsdam

Proceedings of the 14th Asian Test Symposium (ATS ’05) 1081-7735/05 $20.00 © 2005

IEEE

2. There must be a significant duration and amplitude of the faulty signal (electrical condition). 3. The timing of the transient fault must be such that the erroneous value arrives at the input of the latch within the “latching window” (timing condition). Since these conditions are valid, we have to assume that a very high percentage of transient faults will cause either no errors or only single bit errors at the outputs of the combinational parts of the circuit. These errors may manifest themselves as single-bit soft errors in the latches and they can be detected by parity prediction. This is completely different for soft errors directly generated in the latches. For these soft errors we have to expect errors with even or odd parity with almost the same probability. To detect these soft errors the registers have to be duplicated. This situation has to be reflected in the design of self-checking circuits. In this paper we are interested in self-checking multipliers. Multipliers are part of the data path of the computer. The data path is usually checked by parity codes, and therefore we are interested in parity checked multipliers only. Since Booth-2 multipliers are widely used we propose a new self-checking Booth-2 multiplier. The basic principles for the design of self-checking Booth multipliers are described in [4, 5, 6, 7] and the proposed Booth-2 multiplier relies on the ideas outlined in these papers. The main improvements of the proposed Booth-2 multiplier with respect to the known solutions are: 1. The final carry propagation adder is a sum-bit duplicated adder. All even and odd (soft!) errors in the output registers of the multiplier are detected. 2. The carry save adder of the multiplier is designed by use of carry-dependent sum adder cells with a single

3. By adding only a parity tree for the multiplicand (instead of a parity tree for both the multiplicand and the multiplier) the circuit is completely code-disjoint.

In this chapter we shortly recapitulate the basic structure of a Booth-2 multiplier without error detection for computing the product P = a × b of the operands a and b. The multiplication of the two operands a = (an−1 , . . . , a0 ) and b = (br−1 , . . . , b0 ) consists of the two steps - generation of the r/2 partial products and addition of the partial products. The operands a and b are called the multiplicand and the multiplier respectively. Table 1. Encoding of multiplier b in Booth-2 group of 3 bits of multiplier b b2i+1 b2i b2i−1

encoded control signals Add1i

action to generate a partial product

SMi

S2Mi

1

2

3

4

5

6

7

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 1 1 0 0 1 1 0

0 0 0 1 1 0 0 0

0 0 0 0 1 1 1 1

+0 +multiplicand a +multiplicand a +2×multiplicand a -2×multiplicand a -multiplicand a -multiplicand a -0

In the Booth algorithm the multiplicand and the multiplier are signed integers in two‘s complement representation. Groups of two bits, overlapping groups of 3 bits and 4 bits of the multiplier are used for the encoding of the partial products in the different Booth algorithms. Since the Booth2 multiplier is a high-speed multiplier which is frequently used in industrial designs we discuss here the Booth-2 multiplier only. The recoding of a group of three bits of the multiplier b is described in Table 1. First to the r bits br−1 , . . . , b0 of the multiplier b a zero-bit b−1 = 0 is added in LSB position. Then the bits of the multiplier are divided into groups of three overlapping bits [b1 , b0 , b−1 ], [b3 , b2 , b1 ], [b5 , b4 , b3 ] . . .. There are r/2 groups.

Proceedings of the 14th Asian Test Symposium (ATS ’05) 1081-7735/05 $20.00 © 2005

IEEE

a

an−1

a0 Booth−2 Decoder

"0"

cell 0

block G0

b0 b1

SM S2M

block G1

cell 1

b2 b3

Add1

b

2. Booth-2 Multiplier without Error Detection

multiplicand

multiplier

For the different implementations of a 64 × 64 selfchecking Booth-2 multiplier with an improved error detection especially for soft errors the necessary area is increased only by 23% - 30%. For different word-length of the operands the multiplier is modeled by use of a Synopsys CAD-tool from the EUROPRACTICE-project. It is assumed that the reader is familiar with computer arithmetics as it is for instance described in [8, 9, 10].

For every bit combination of three bits of a group in the columns 1, 2 and 3 of Table 1, the values of the control signals SMi , S2Mi and Add1i are given in columns 4, 5 and 6. The corresponding partial products which are derived from the multiplicand a are presented in column 7.

partial product generator

carry-out signal only instead of carry duplicated adder cells in the known solutions.

block Gk−1

cell k−1

b r−2 b r−1

partial products

carry save adder CSA (array or tree of carry save adder cells)

A m−1

Bm−1

A0

B0

carry propagation adder CPA Cout

sum

P=a x b

Figure 1. Booth-2 multiplier without error detection The general structure of the Booth-2 multiplier without error detection is shown in Fig. 1. The Booth-2 multiplier consists of a Booth-2 decoder, a partial product generator, a carry save adder (CSA) and a carry propagation adder (CPA) to add the partial products generated by the partial product generator. The groups of always three overlapping bits of the multiplier are encoded by the cells of the Booth-2 decoder into the control signals SMi (SMi = b2i ⊕ b2i−1), S2Mi (S2Mi = b2i ⊕ b2i+1 ∨ b2i ⊕ b2i−1) and Add1i (Add1i = b2i+1 ) of the partial product generator according to Table 1. Fig. 2 shows an implementation of the i-th Booth-2 decoder cell. For i = 0, . . . , r/2 − 1 the i-th partial product part_producti is determined from the bits of the multiplicand a by the control signals SMi , S2Mi , Add1i of the i-th decoder cell in a partial product generation block Gi . A partial product generation block Gi is presented in Fig. 3. The MSB of the generated partial product part_producti is used for sign extension. When the partial products are determined they have to be added. To avoid to add a large number of bits which are generated only by ordinary sign extension different methods

multiplicand

b 2i−1

S2M i

b 2i

Add1i

b 2i+1

pa

a a0

an−1

Booth−2 Decoder"0"

S2M

b

a0 SM i S2M i Add1 i

Bm−1

A0

?=

p(S2M) p(S2M d) p(b) pb

pC

parity predictor of partial products

B0

p

A B

CPA

a1

? =

carry save adder CSA (array or tree of carry save adder cells)

Am−1

b r−2 b r−1

p(SM)

pb

an−2

b3

cell k−1

block Gk−1 p(Add1)

an−1

cell 1

Add1

partial products

were developed especially for the case n and r even. For both even and odd cases we refer here for instance to [8, 4].

b2

SM

block G1

b0 b1

S2M d

multiplier

Figure 2. Cell celli of the Booth-2 decoder without error detection

cell 0

block G0

partial product generator

SM i

code−disjoint sum−bit duplicated adder

Cout

sum

P=a x b

Cout

?=

pA pB

sum

P=a x b

block G i MSB

used for SIGN extension

si

part_product i

Add1 i

Figure 3. Implementation of a partial product generation block Gi The partial products part_product0 , . . ., part_productr/2−1 are added in a first step by a carry save adder, which can be implemented as an array or a (Wallace-)tree of half-adder and full-adder cells into two operands A = (Am−1 , . . . , A0 ) and B = (Bm−1 , . . . , B0 ). And finally these two operands are added by a carry propagation adder into the product P = a × b which is stored in the output register of the multiplier.

3. Proposed Self-checking Booth-2 Multiplier In this section we describe the proposed self-checking Booth-2 multiplier and we explain the differences to the till now known solutions [4, 7]. The general principles proposed in this paper can be extended for the design of selfchecking Booth-1 and Booth-3 multipliers. Fig. 4 shows the proposed self-checking Booth-2 multiplier. We assume that both the multiplicand a = (an−1 , . . . , a0 ) and the multiplier b = (br−1 , . . . , b0 ) are parity encoded with the corresponding input parities p a = an−1 ⊕ . . . ⊕ a0 and pb = br−1 ⊕ . . . ⊕ b0. n and r are supposed to be even. In most cases we have n = r. The self-checking Booth-2 multiplier consists of a parity checked Booth-2 decoder, a partial product generator, a parity predictor for the partial products, a parity checked carry save adder, a final code-disjoint sum-bit duplicated adder and some XOR-trees.

Proceedings of the 14th Asian Test Symposium (ATS ’05) 1081-7735/05 $20.00 © 2005

IEEE

Figure 4. Proposed self-checking Booth-2 multiplier

The decoder cells celli , i ≥ 1, for the proposed selfchecking Booth-2 multiplier are shown in Fig. 5a. Compared to the decoder cells of Fig. 2 only the outputs S2Mi are duplicated into S2Mid . For the cell cell0 the first input b−1 is always zero. To avoid redundant faults cell0 is optimized and shown in Fig. 5b. S2M di SM i S2M i Add1 i S2M di SM i S2M i Add1 i

b 2i−1 1

b 2i b 2i+1

a) "0" b−1 b0 b1

b)

Figure 5. Modified cells celli and cell0 of the self-checking Booth-2 decoder From the outputs SMi , S2Mi , S2Mid and Add1i of the decoder cells the corresponding parities p(SM), p(S2M), p(S2M d ) and p(Add1) are determined by XOR-trees and the Booth-2 decoder is parity checked. This parity checking reduces the area compared to [4] where the complete Booth-2 decoder is duplicated and the duplicated decoders are compared by a self-checking two-rail checker. The partial product generator which is the same as in [4]

generates at its outputs the r/2 partial products. The parity predictor predicts the parity p(part_products) of the partial products in dependence on the signals pa , p(SM), p(S2M) and the MSB an−1 of the multiplicand according to [4] as 
  p(part_products) = P(SM) ⊕ P(S2M) ∧ an−1 ⊕   ⊕ p(S2M) ∧ pa ⊕ p(Add1). There it is used that for i = 0, . . . , r/2 − 1 never both SMi and S2Mi are simultaneously equal to 1 (see Table 1). The partial products are added in a parity checked carry save adder which is similar to the carry save adder as proposed in [11] into two operands A = (Am−1 , . . . , A0 ) and B = (Bm−1 , . . . B0 ). The parity p(part_products) of the partial products is the parity of the inputs of the carry save adder. Since the parity of the result of an addition equals the parity of the inputs XORed with the parity of all internal carry signals of the adder we have for the parity pA ⊕ pB with pA = Am−1 ⊕ . . . ⊕ A0 and pB = Bm−1 ⊕ . . . ⊕ B0 of the output operands A and B of the carry save adder pA ⊕ pB = p(part_products) ⊕ pC . Thereby pC is the parity of all internal carries of the cells of the carry save adder and it has to be determined by an XOR-tree. To achieve the self-checking property the adder cells and the carry save adder itself have to be specially designed. In the proposed self-checking design the adder cells of CSA are carry-dependent sum adders [11]. In a carry-dependent sum adder cell with the input operands a, b, the carry-in cin and the carry-out cout the sum-bit s is defined as an XOR-sum of a function f with f = ab ∨ bcin ∨ cin a and the carry-out signal cout = ab ∨ acin ∨ bcin as s = f ⊕ cout [12]. To achieve 100% fault coverage for single stuck-at faults in the carry-dependent sum adder cell of Fig. 6a the function f and cout are structurally separately implemented. To reduce the necessary area and to guarantee a 100% (or almost 100%) error detection probability for single stuck-at faults for the carry-dependent sum adder cell the function f and the output cout can be jointly implemented as shown in Fig. 6b and 6c. In Fig. 6b the only gate which is shared between the lines f and cout is the OR-gate 1. It can be easily shown that in the carry-dependent sum adder cell of Fig. 6b the function f and the output cout are functionally (but not structurally)

Proceedings of the 14th Asian Test Symposium (ATS ’05) 1081-7735/05 $20.00 © 2005

IEEE

f

b

s a c out c in b

a) 1

0

f

MUX

s

1

2

a 2’

c in

c out

3

b

1

b) 0

s−a−0

MUX 1

2

f

s

a c out

c in 3

c)

Figure 6. Carry-dependent sum adder cells of the self-checking CSA

independent and that this adder cell has the same 100% error detection probability for errors caused by single stuckat faults as the independent implementation of f and cout in Fig. 6a. With respect to an independent implementation the necessary area is reduced by 12%. To further reduce the necessary area for the adder cell we utilize that the NAND-gates 2 and 2
in Fig. 6b implement both the same function b cin . These two NAND-gates are replaced by a single NAND-gate 2 in Fig. 6c. The error detection properties of this cell are almost the same as of the cells in Fig. 6a and 6b. Only an error due to a single stuckat-0 fault at the output-line of the NAND-gate 2 under the input a, b, cin = 1, 0, 0 cannot be detected by parity checking. All other errors caused by all possible single stuck-at faults are immediately detected by parity checking. Compared to the cell of Fig. 6a the necessary area is reduced by 22%. Instead of carry-dependent sum adder cells with a single carry-out signal in [4] adder cells with duplicated carry-out signals and a higher area overhead were used. The outputs A = (Am−1 , . . . , A0 ) and B = (Bm−1 , . . . , B0 ) of the carry save adder are added in the final carry propagation adder. This carry propagation adder is implemented as a code-disjoint sum-bit duplicated adder according to [13]. The adder is code-disjoint with respect to a parity code. The parity of the partial products p(part_products) and the pa-

rity pC of the internal carries of the cells of the carry save adder are XORed to form the parity of the outputs A and B of the carry save adder p(part_products) ⊕ pC = pA ⊕ pB = = (Am−1 ⊕ . . . ⊕ A0 ) ⊕ (Bm−1 ⊕ . . . ⊕ B0 ). A and B are also the inputs of the final code-disjoint sum-bit duplicated adder and p(part_products) ⊕ pC = pA ⊕ pB is also the input-parity of this adder. The propagation signals Am−1 ⊕ Bm−1 , . . ., A0 ⊕ B0 of the sum-bit duplicated adder are XORed into pA⊕B = Am−1 ⊕ Bm−1 ⊕ . . . ⊕ A0 ⊕ B0 and checked against the input parity pA ⊕ pB. The sum-bits and the inverted sum-bits of this codedisjoint sum-bit duplicated adder are designed by use of the already parity checked propagation signals and the final result, i. e. the product P = a × b and the inverted product P = a × b are stored in the two output registers. The resulting product a × b and the inverted product a × b are checked in the system and all odd and even (soft) errors in the final registers are detected. If, as in [4] the product is only parity checked only odd errors in the final register can be detected. The input parity pb of the multiplier b is checked against the XOR-sum of the parity p(SM) of the control signals SMi of the Booth-2 decoder and br−1 of the multiplier b. If the input parity pa is checked against an XOR-sum an−1 ⊕ . . . ⊕ a0 of the bits of the multiplicand which can be easily determined by an additional XOR-tree of n − 1 XOR-gates the proposed self-checking multiplier is completely code-disjoint. The proposed Booth-2 multiplier is completely self-checking. All errors due to single stuck-at faults in the combinational parts are immediately detected by parity checking and all soft errors, even or odd, in the output registers are detected. Because of the limited length of the paper we refer to [14] for a detailed discussion.

4. Experimental Results The proposed code-disjoint self-checking outputduplicated Booth-2 multiplier was experimentally compared with self-checking multiplier design according to [4]. The experimental results were obtained for 8 × 8, 16 × 16, 32 × 32 and 64 × 64 multipliers, in which the carry save adders are implemented as an array of adder cells. The final carry propagation adder was implemented

Proceedings of the 14th Asian Test Symposium (ATS ’05) 1081-7735/05 $20.00 © 2005

IEEE

as code-disjoint sum-bit duplicated ripple adder. All multipliers were modeled by use of the SYNOPSYS CADtool from the EUROPRACTICE-project with the library vtvtlib25 [15, 16]. In Table 2 the necessary area for the multiplier without error detection, for the multiplier according to [4], for the proposed multiplier with the carry-dependent sum adder cells of Fig. 6b and with the carry-dependent sum adder cells of Fig. 6c are presented in columns 1, 2, 3 and 4. In the columns 3 and 4 the area for the XOR-tree of the multiplicand is included and the modeled proposed self-checking Booth-2 multipliers are completely code-disjoint. The multiplier in column 2 is not code-disjoint. Compared to the self-checking multiplier Type B according to [4] for the adder cells in Fig. 6b the necessary area can be reduced from 166% to 158% for 8 × 8 bits, from 152% to 143% for 16 × 16 bits, from 144% to 135% for 32 × 32 bits and from 140% to 130% for 64 × 64 bits. For the adder cells in Fig. 6c we obtained an improvement of the area from 166% to 155% for 8 × 8 bits, from 152% to 138% for 16 × 16 bits, from 144% to 128% for 32 × 32 bits and from 140% to 123% for 64 × 64 bits. The error detection capability of the proposed Booth-2 multiplier is much better since additional to all errors due to single stuck-at faults within the multiplier which are detected by parity checking also all soft errors in the output registers and all odd input errors are detected.

5. Conclusions In this paper a code-disjoint self-checking outputduplicated Booth-2 multiplier with a high fault coverage for soft errors was proposed. It was experimentally shown that even with this improved error detection capability compared to the till now known solution the necessary area could be reduced. Since the final carry propagation adder was chosen as a code-disjoint sum-bit duplicated adder and all even and odd soft errors in the output registers are detected. It was demonstrated that the self-checking carry save adder can be designed by use of carry-dependent sum adder cells with only one carry-out signal instead of the carryduplicated adder cells in the known design. It was shown that the Booth-2 decoder has only to be partially duplicated and can be parity checked. By adding only a single parity tree for the multiplicand the proposed Booth-2 multiplier is completely codedisjoint, and all odd errors at the input lines are detected. If no parity tree is added some of the odd input errors are detected with some latency.

Table 2. Area overhead and error detection capabilities of Booth-2 multipliers proposed multiplier CSA adder cell CSA adder cell of Fig. 6b of Fig. 6c

multiplier without error detection

multiplier according to [4]

1

2

3

4

8x8 16x16 32x32 64x64

26874 (100%) 101393 (100%) 385808 (100%) 1503984 (100%)

44678 (166%) 154077 (152%) 556625 (144%) 2104559 (140%)

42578 (158%) 145146 (143%) 520595 (135%) 1960578 (130%)

41571 (155%) 139436 (138%) 494731 (128%) 1851413 (123%)

error detection capability

no error detection

single s-a-fault in the combinational part, odd errors of output registers

AREA

For 8 × 8, 16 × 16, 32 × 32 and 64 × 64 the proposed selfchecking Booth-2 multiplier was modeled by a SYNOPSYS CAD-tool of the EUROPRACTICE project. Compared to the 64 × 64 bits multiplier without error detection the area for the proposed self-checking Booth-2 multiplier increases only by 23-30%. It was demonstrated that the proposed self-checking Booth-2 multiplier improves as well the necessary area as the error detection capability especially for soft errors.

References [1] P. Shivakumar and et al., “Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic,” in Proceedings of International Conference on Dependable Systems and Networks, pp. 389–398, 2002. [2] P. Liden ´ and et al., “On Latching Probability of Particle Induced Transients in Combinational Networks,” FTSC, pp. 340–349, 1994. [3] K. Mohanram and N. A. Touba, “Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits,” in Proceedings of ITC, pp. 803–901, 2003. [4] M. Nicolaidis and R. Duarte, “Fault-Secure Parity Prediction Booth Multipliers,” IEEE Design & Test of Computers, pp. 90–101, 1999. [5] M. Nicolaidis, R. Duarte, S. Manich, and J. Figueras, “Fault-Secure Parity Prediction Arithmetic Operators.,” D&T of Computers, vol. 14, no. 2, pp. 60–71, 1997. [6] I. A. Noufal, “Outils de cao pour la gen ´ eration ´ d’operateurs ´ arithmetiques ´ auto-controlables,” ˆ tech. rep., Diss., Grenoble, May 2001. [7] K. S. Papadomanolakis, A. P. Kakarountas, V. Kokkinos, N. Sklavos, and C. E. Goutis, “The Effect of Fault

Proceedings of the 14th Asian Test Symposium (ATS ’05) 1081-7735/05 $20.00 © 2005

IEEE

single s-a-fault in the combinational part, all errors of output registers all odd input errors

Secureness in Low Power Multiplier Designs,” in International Workshop - Power and Timing Modeling, Optimization and Simulation, (Switzerland), 2001. [8] I. Koren, Computer Arithmetic A.K.Peters, Natick, MA, 2002.

Algorithms.

[9] M. J. Flynn and S. F. Oberman, Advanced Computer Arithmetic Design. John Wiley & Sons, 2001. [10] B. Parhami, Computer Arithmetic. Algorithms and Hardware Designs. Oxford University Press, 2000. [11] D. Marienfeld, E. S. Sogomonyan, V. Ocheretnij, and M. Gössel, “A New Self-checking Multiplier by Use of a Code-disjoint Sum-bit Duplicated Adder,” in 9th IEEE European Test Symposium, pp. 73–78, 2004. [12] M. Y. Hsiao and F. F. Sellers, “The Carry Dependent Sum Adder,” IEEE Transactions on Electronic Computers, vol. EC-12, pp. 265–268, June 1963. [13] E. S. Sogomonyan, V. Ocheretnij, and M. Gössel, “A new code-disjoint sum-bit duplicated carry look-ahead adder for parity codes,” in 10th Asian Test Symp., pp. 57–62, 2001. [14] D. Marienfeld, E. S. Sogomonyan, V. Ocheretnij, and M. Goessel, “Self-checking output-duplicated booth-2 multiplier,” tech. rep., University of Potsdam, Institute of Informatic, 001/2005, ISSN 0946-7580, 2005. [15] J. B. Sulistyo, J. Perry, and D. S. Ha, “Developing standard cells for tsmc 0.25um technology under mosis deep rules,” tech. rep., Department of Electrical and Computer Engineering, Virginia Tech, Technical Report VISC-2003-01, 2003. [16] J. B. Sulistyo and D. S. Ha, “A New Characterization Method for Delay and Power Dissipation of Standard Library Cells,” VLSI Design, vol. 15, no. 3, pp. 667– 678, 2002.