Invited Paper
Novel Fabrication Methods for 2D Photonic Crystals in Silicon Slab Waveguides Dennis W. Prather, Janusz Murakowski, Sriram Venkataraman, Yao Peng, Anita Balcha, Thomas Dillon, and David Pustai The University of Delaware Department of Electrical and Computer Engineering 140 Evans Hall Newark, DE 19716 Email:
[email protected] ABSTRACT: In this paper we present the development of several new and novel fabrication methods for the realization of two-dimensional photonic crystal devices in silicon slab waveguides. We begin by presenting a process for the fabrication of high fill-factor devices in silicon-on-insulator wafers. Next, we present a grayscale fabrication process for the realization of three-dimensional silicon structures, such as tapered horn couplers. We then present the fabrication of suspended silicon slabs using a co-polymer process based on direct write electron beam lithography and silicon sputtering. And lastly, we conclude by presenting an alternate method for realizing PhC devices in a silicon slab based on a combination of wet and dry etching processes in bulk silicon wafers. Keywords: photonic crystal devices, nano-fabrication, silicon-on-insulator, and slab waveguides
1. INTRODUCTION Since their introduction, photonic crystal (PhC) devices have steadily received increased attention from the research community [1]. In terms of device geometries, most references to PhC devices have come in the form of two-dimensional PhCs fabricated in slab waveguides, with the majority of these being silicon slab waveguides [2-4]. A major reason for this is the ease with which PhCs can be fabricated using silicon-on-insulator (SOI) wafers, which offer a streamlined process for creating suspended silicon slabs or asymmetric slab waveguides having a glass under layer. However, despite the ease of fabricating PhCs in SOI wafers, they remain significantly more expensive than their bulk silicon counterparts. As a result, there is a motivation to develop silicon slab fabrication methods that do not require expensive SOI wafers, yet offer the ability to realize suspended silicon slab waveguides. Therefore, in this paper we present two such methods that not only enable suspended silicon slab PhCs but also are compatible with standard microelectronic manufacturing processes. However, before we discuss these methods we first present two novel fabrication processes that build upon SOI fabrication techniques for the realization of high fill factor PhCs and tapered horn couplers.
Micromachining Technology for Micro-optics and Nano-optics, Eric G. Johnson, Editor, Proceedings of SPIE Vol. 4984 (2003) © 2003 SPIE · 0277-786X/03/$15.00
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2. HIGH FILL FACTOR PHOTONIC CRYSTALS To maximize the extent of the photonic bandgap in a finite-height photonic-crystal (PhC) slab one can increase the fill-factor in the PhC lattice. Among the realistic choices of possible 2D lattices, high fillfactor triangular lattices of cylindrical holes in a high index dielectric, namely silicon, are by far the most commonly used. In this paper, we present a method for fabrication of very high fill-factor PhC devices in silicon-on-insulator (SOI) substrates using electron-beam lithography and high-aspect-ratio reactive-ion etching (RIE). SOI wafers are an attractive platform for the fabrication of photonic band gap devices for several reasons. First, the use of silicon offers a large difference in refractive index between the silicon waveguide and the cladding layers (air and glass), thereby creating strong vertical confinement. And second, the fabrication process is compatible with standard silicon CMOS processing. Accordingly, PhC devices in SOI are realized by creating a lattice of air-holes in silicon, which can by achieved by anisotropic etching, of a high resolution patterned surface, into the silicon device layer (top layer of the SOI wafer). The refractive-index modulation, depth, and length of the device are the main parameters that are used to determine the optical properties of devices based on a photonic bandgap. Thus, stringent control of these parameters necessitates high-resolution lithography and high-aspect-ratio etching. While high aspect ratio etching technology is common in the microelectromechanical systems (MEMS) industry, they typically use sophisticated etching systems to realize structures with feature sizes ranging from tens to hundreds of microns. In the case of a PhC structures, the challenge is to realize these devices using sub-micron (often less than 100nm) fabrication processes.
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In the MEMS industry, systems for deep reactive-ion etching (c) (DRIE) utilize fast pumping, fast-response mass-flow controllers, inductive coupling of power, and heated chamber and pump lines, that are critical to achieve reliable etch rates. In contrast, we have achieved 8:1 aspect-ratio PhC structures with 62nm vertical membrane walls using a standard reactive-ion etching process based on a sidewall passivation processes. In the remainder of this section, Figure 1. (a) Top-view, (b) we discuss this fabrication process. perspective view, and (c) zoom-in view of the etched high-fill factor To begin we use SOI wafers manufactured by SOITEC that consist (r/a~0.45) PhC device. Silicon of two different SOI wafers: one consisting of a 0.45µm silicon sidewall membranes separating device layer (waveguide core) with a 1µm SiO2 insulator layer the holes in the PhC lattice are as supported by a bulk silicon substrate, and the other with a 0.26µm thin as 62nm, yet no lateral silicon device layer and a 1µm SiO2 insulator layer on a silicon erosion of the PMMA etch mask is substrate. Our process is based on modifications to previous etch observed. methods in the literature [5,6] and begins with the use of a Raith-50 electron-beam lithography system, which is used to pattern the PhC devices in poly-methyl methacrylate (PMMA). For this we spin 200 nm of PMMA, with a molecular weight of 950K, at 3000 rpm for 45 seconds and bake out the sample at 180°C for one minute to remove the solvent. The resulting PMMA pattern consists of a high-fill-factor (r/a>0.4) triangular PhC lattice structure, which was obtained using a 100pA beam current and 20kV accelerating voltage, which serves as our etch mask. After exposure, the 90
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pattern was developed in a 1:3 solution of methyl isobutyl ketone (MIBK) in isopropyl alcohol for 30 seconds. The electron dose must be precisely controlled while exposing PMMA in order to achieve the desired diameter of the holes in the photonic-crystal lattice. We have used two different schemes to realize the photonic crystal, namely dot exposure and area exposure. In dot exposure, the electron beam is held at a fixed position, the center of the desired hole, for a period of time that yields the necessary hole diameter as a result of the proximity effect. In area exposure, we pattern a lattice of hexagons smaller than the desired hole diameter to compensate for the proximity effect, which results in the opening of areas larger than that which was exposed. Once the devices are patterned using e-beam lithography, the etching is carried out using a PlasmaTherm 790 series machine set up for reactive-ion etching. This is a parallel-plate, single-chamber, manualloading RIE system with an 8-inch aluminum plate, a 13.56-MHz RF source, and operator-controlled power or bias voltage and gas-flow rates. The key to realizing deep anisotropic silicon etching is to have a higher etch rate in the vertical direction than in the direction parallel to the surface. We have found it to be difficult to achieve repeatable high-aspect ratio structures in the sub-micron regime with a low-end RIE system using conventional etching techniques with structures containing minimum feature sizes less than 100nm. Using conventional etching techniques it becomes increasingly difficult to control the etch depth, minimize surface roughness and achieve vertical sidewalls, all of which greatly influence the optical properties of PhC devices. Thus, fabrication of high-efficiency and high fill-factor PhC devices with a high yield, motivates the need to develop a custom DRIE process with minimal surface roughness, accurate control of the etch depth and vertical sidewalls with a conventional RIE etching system. Such a deep anisotropic etch process is attributable to three etch characteristics: a) increased etch rate at the bottom of exposed silicon, b) decreased etch rate at the sidewalls, and c) removal of the passivants from the bottoms of the trenches. With the addition of gases like CHF3 or C4F8 (passivant precursors) to the plasma, a sidewall passivation layer can be deposited, which blocks etching in the lateral direction. However, the etch rate in the vertical direction also decreases with increasing concentration of the passivant, as the passivation layer deposited at the bottom of the trench has to be constantly removed by ion bombardment in order to allow the chemically active fluorine radicals to etch the trench bottom. In conventional etching process, all the gases are introduced into the plasma as a continuous gas mixture, hence the deposition of a passivation layer, its removal from the bottom of the trench, and etching are carried out simultaneously. This, however, could lead to insufficient sidewall passivation, or to the formation of "grass," (also called black silicon) due to micromasking. To alleviate these difficulties, in a time-multiplexed method we have separated the processes of sidewall passivation, trench-bottom passivant removal, and silicon etching are each performed separately. Accordingly, we have divided the process into cycles, wherein each cycle consists of three separate steps: the deposition of sidewall passivating polymer film using CF4 and H2 gases, and two etching steps using SF6 and He gases. Each of the steps within a cycle is optimized to realize the fabrication of high-fill-factor photonic-crystal structures with narrow wells separating the holes of PhC lattice. Following the deposition of the passivation layer, during the first etching step, the passivating film is preferentially removed from the bottom of the trenches by high-energy ion bombardment in the SF6 and He plasma. In the second etching step, SF6 and He plasma containing large concentration of atomic fluorine etches silicon in the trench bottoms, while the passivating polymer film left on the sidewalls prevents its etching. These steps are cycled until the required etch depth is achieved, which is in our case equal to the thickness of the top Si layer (t=450nm). The alternating between the deposition and etching steps produces anisotropically etched trenches with a high selectivity to resist, which permits us to define high-quality photonic crystal structures within SOI substrates, as shown in Fig. 1. Using this high-aspect ratio custom DRIE process we have fabricated high fill-factor PhC devices (r/a~0.45) with the thickness of the dielectric walls of the order of 60nm and an etch depth of 450nm, as shown in Fig. 1. In Fig. 1(c), which depicts the sidewall Proc. of SPIE Vol. 4984
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profile (surface roughness) of the etched device, we can clearly observe ripples where each ripple corresponds to one cycle step. We have measured the surface roughness to be of the order of 20nm, which can be reduced by increasing the cycle rate of the DRIE process. In the next section we discuss the use of grayscale lithography methods to realize three-dimensional tapered horn couplers.
2. GRAYSCALE SOI STRUCTURES The fabrication of three-dimensionally profiled optical structures has been described in the literature for some time [7]. One particularly useful method to achieving these profiles is through the application of grayscale photolithography. Many grayscale methods have been investigated, which include the successive alignment of multiple conventional binary masks, direct-write e-beam lithography, resist reflow lithography, the preparation of half-tone masks, the successive evaporation of Inconel metal onto a mask substrate, and high-energy-beam-sensitive (HEBS) glass masks. However, a drawback common to most of these techniques is the limitation of the device features to a discreet number of quantized height levels. For the utmost flexibility in design and the highest achievable efficiency, one would prefer a method that offers continuously graded device features. To this end, we have developed a process to produce such features using a continuous-tone grayscale mask fabricated by exposure of HEBS glass to a direct write electron beam. To develop this capability, we have investigated the response of HEBS glass to exposure by an energetic electron beam in our Raith50 electron beam lithography system. We initially characterized the material response for both single-pixel-line exposures and to bulk-area exposures that were large enough to allow saturation of the optical density due to proximity effects. From the bulk-area exposures, over an extended range of doses, we were able to calibrate the exposure dose to the net optical density. Results for a range of electron beam accelerating potentials are shown in Fig. 2. From this we were then able to infer the scattered dose concentration profiles of the line exposures from their optical density profiles; this is related to the e-beam Figure 2. HEBS saturated response characterization for 1nA point spread function for the particular beam current, 0.1 micron addressing grid. The saturation write parameters employed. A results from the proximity effect with large exposure areas. reasonably good Gaussian fit to the dose profiles was obtained. Because the response of the HEBS glass may be modeled in terms of a convolution of the e-beam point spread function with the exposure grid, it becomes possible to determine the optimal exposure profile through the deconvolution of the desired optical density profile with the experimentally determined beam profile. To do this we found the Gaussian fit to the beam profiles that had a half-width independent of the exposure dose. This ensured a single kernel with which to perform the deconvolution. This technique 92
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works quite well for profiles that are smooth in nature; however, for devices with many large discontinuities, such as multi-level phase-relief DOEs or blazed gratings, the transform of the device profile contains much high frequency content, while the Gaussian e-beam point spread function is inherently low frequency. This makes deconvolution difficult for such situations. To apply our grayscale process to the realization of functional devices, we considered the material in which the device was to be fabricated, and began with the height profile for the device that we wished to produce in this material. If the device material is other than photoresist, it is necessary to transfer the device profile from the resist into the desired material via etching. For a grayscale process, the photoresist etch mask must be removed in a smooth and controllable fashion, so that the underlying material is gradually exposed and etched. The result is a translation of the photoresist profile into the substrate with a height gain equivalent to the selectivity of the etch chemistry. With the gain of the etch process determined, the necessary photoresist height profile follows.
Figure 3. Optical microscope image of HEBS glass continuous-tone grayscale mask for use in the fabrication of tapered optical couplers. The input waveguides are ten microns in width.
Now the resist height upon developing must be calibrated to UV exposure energy, from which the optical density of the device features in the mask may be determined. To this end, the resist height that results from an optimized lithography process was calibrated with a range of optical densities from a reference mask. From this information, the device height profile is encoded into the optical density profile necessary to produce it. The calibration is valid only for the particular lithography process parameters employed and would need to be changed if the lithography process were altered, e.g. in exposure energy and time or develop time and temperature. For the purpose of grayscale lithography a resist with low contrast is desired in order to provide a reasonable range over which to linearize its response. We have determined that given the proper process parameters, a linear resist height to optical density relationship can be obtained.
(a) (b) Figure 4. (a) Tapered optical couplers fabricated in photoresist. The devices inputs are ten microns and taper down to as small as one micron and (b) Optical couplers etched into SOI, diced, and polished in preparation for characterization.
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In this application we needed to produce a high contrast in the mask to maximize the utilization of available resist height; hence high optical density in the mask is desired. However, achieving high contrast necessitates higher electron doses and hence reduces resolution because of increased electron scattering. We typically choose a maximum optical density of 0.6, to improve resolution and decrease write time, while maintaining an acceptable contrast level to maximize utilization of the photoresist. With the process issues for grayscale mask fabrication, photolithography, and selective etching well in hand, we proceeded to apply our expertise to the production of a number of useful optical devices, namely a horn coupler for silicon slab waveguides. In this case we set out to fabricate a horn structure whose input end was comparable in size to that of a single mode fiber, which required a cross-section of around ten square microns. The tapered region was then reduced to multi-mode waveguides in the SOI device layer with typical dimensions of a micron or less. Our devices were designed with various taper sizes and geometries; these Output of tapered coupling system included one and three micron outputs with sinusoidal, linear, and exponential tapers. Simulations predicted little dependence of the output efficiency on the taper length or geometry, input Schematic representation of the tapered provided that the taper was long enough to coupling system adiabatically transform the guided mode Figure 5. Demonstration of successful coupling into profile. and out of a two-sided tapered waveguide device. The fabrication proceeded from the generation of a grayscale mask, as described previously. Photolithography was then carried out with thick film resist AZ4620. We chose to work with ten micron resist thickness in order to utilize a 1:1 etch selectivity during translation of the developed resist pattern into the underlying silicon. In our experience this gives the highest fidelity reproduction of the device geometry. In order to achieve good etch results, careful consideration of the process parameters is required. We chose to proceed with SF6 chemistry and O2 for etching the photoresist. It was necessary to use He to cool the substrate and produce smooth etching results. After etching, the devices were diced and polished and end-fire coupled with a 1310nm laser into the front facet and observed the signal at the exit facet. Figure 5 shows the successful outcoupling of the laser through the exit facet. We are currently quantifying insertion loss and throughput efficiency for the device. In the next section we discuss the fabrication of a suspended silicon slab without the use of an SOI wafer and in its use for PhC devices obviates the need for an associated etch process. As such, we refer to this method as the etchless fabrication technique for two-dimensional PhC devices.
3. ETCHLESS FABRICATION OF SUSPENDED PhCs IN SILICON SLABS As discussed in the introduction and as shown in the previous two sections, the fabrication of PhC silicon slabs using SOI wafers is a very useful process. However, the costs associated with the SOI process are very high and, for this reason, we have explored the development of alternative silicon slab fabrication methods. The first of these methods is base on a two step process where we first create a suspended
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organic membrane, using direct write electron beam lithography. In the second step we coat the organic membrane with silicon, which results in high dielectric contrast as required for PhC devices. To arrive at the suspended organic membrane, we first coat the substrate with a 900 nm thick layer MMA/MAA (methyl methacrylate / methacrylic acid) copolymer by spinning its liquid solution at 3000 rpm for 45 seconds. The solvent, ethyl lactate, is evaporated away in a 60 second bakeout at 180°C. Then, we spin 200 nm of PMMA (polymethylmethacrylate) at 3000 rpm for 45 seconds and bakeout the sample again at 180°C for one minute to remove the solvent. From this process we obtain a silicon substrate with a 900 nm layer of MMA/MAA copolymer and a 200 nm layer of PMMA on top. In order to pattern the photonic crystal, we expose the sample with an array of dots using Raith50 electron-beam lithography system at approximately 100 pA probe current. Both MMA/MAA and PMMA are e-beam sensitive polymers, and the 20 kV electrons easily penetrate the 200 nm layer of PMMA to expose MMA/MAA underneath. The interaction of the electrons with the polymers results in breaking the polymer chains, thus, making them more soluble in the developer, a 1:3 solution of MIBK (methyl isobutyl ketone) in isopropyl alcohol. For the development, the sample is immersed for 30 seconds in the solution. The developer dissolves the regions exposed to electron beam beginning with the top PMMA layer. As soon as a hole opens up in the PMMA, the bottom layer of MMA/MAA starts dissolving away. However, the dissolution of MMA/MAA proceeds faster since this copolymer is characterized by a higher dissolution rate than PMMA. As a result, since a wider region of MMA/MAA was exposed due to proximity effect, the PMMA is undercut and a perforated membrane suspended above the substrate is created as shown in Fig. 6.
Figure 6. Perspective view of the released holey membrane. Overexposed area, on the right, shows three-dimensional nature of the structure. Correct dose results in the structure shown in picture on the left. However, the index of refraction of PMMA is insufficient to allow for the creation of a photonic bandgap. Thus, in order to produce a high index material structure, in the second step, we coat the PMMA membrane with a layer of silicon, by way of DC sputter coating. The silicon was sputtered for five minutes at 200 Watts of DC power. Additionally, the stage was cooled to 23°C to ensure the membrane PMMA did not disintegrate or deform during the process, in addition the substrate was continuously rotated to ensure uniform sputtering deposition. The sputtering system contains a confocal cathode arrangement in which the cathode is focused on a central area of the substrate table. Table rotation during sputtering provided even substrate exposure to the cathode, and resulted in excellent coating uniformity to within 5%. The resulting structure can be seen in Fig. 7. Clearly, the PMMA membrane held well under
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the deposition of silicon. Slight bowing can be observed in the close-up view, which is a result of stress induced during the deposition process. The last fabrication process we introduce in this paper is a technique for fabricating suspended silicon slab waveguides using bulk silicon wafers, which is discussed in the next section.
4. SUSPENDED PhCs IN SILICON SLABS USING BULK WAFERS In this section we present a new approach for fabricating suspended PhC structures using (111) oriented single crystal silicon (SCS). Unlike SOI or multi-layer growth techniques [2-4,8,9] our method employs a combined RIE dry etch, of the PhC structure, followed by a wet chemical etch, to release the silicon slab. The thickness of the structures as well as the gap between the released structures and substrate are fully determined during the RIE step of the process. The wet-etch step stops naturally at the (111) planes and thus results in smooth bottom surfaces.
Figure 7. The resulting perforated silicon membrane as created by sputtering silicon on the PMMA canvas. Note that the lattice self formed according to the underlying PMMA template, thereby eliminating the need for an etch step! To understand how this process works, it is necessary to first discuss the wet release mechanism of (111) SCS. There are a total of 8 (111) planes, which include top and bottom surfaces and six others that are tilted at 19.47˚ from the vertical direction. Those 8 planes act as the etch-stop planes and thus define the final shape of the under etched cavity since the etching speed in (111) directions is so slow that for all practical purposes can be ignored in the crystallographic directions such as (100) or (110) [10]. Thus, if a pre-patterned structure containing a certain height in (111) SCS is wet etched, the etchant attacks it in all directions. However, due to the huge difference of etching speed, the material is effectively only dissolved laterally from the sidewalls. If the upper portion of the sidewalls is protected by use of a passivation layer, such as silicon oxide or silicon nitride, the lower part of structure is only attacked laterally and the upper part is not attacked at all. This makes it possible to release the device layer within (111) SCS [11-14].
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Since slab PhC structures mainly consist of periodically placed holes (circular, triangular, etc.) in a dielectric slab, both the inner sidewalls of the holes and the outer sidewalls of the slab are subjected to the attack of the wet etch, at the location of the unprotected areas. Which of the two, the inside-outside process or the outside-inside process that dominates the release process depends on the 3D shape of defects as well as the structure body. If the defects are circular cylinders, the under etched cavity will have the shape of a polyhedron, which completely encloses the initial cylinder, such that all its faces lie in (111) planes. Depending on the proportions of the cylinder, there are essentially two possible distinct shapes of the resulting polyhedron. If the height of the original cylinder, T, is less then 2 times its diameter, D, then the top and bottom sides of the polyhedron are hexagons, and the situation is depicted in Fig. 8(a). If the height is more than 2 times the diameter, the resulting polyhedron is shown in Fig. 8(c), where the top and bottom faces are triangles while the remaining faces are pentagons. The intermediate between the two is a regular octahedron shown in Fig. 8(b). These polyhedrons are obtained from the limiting case of an infinitely thin cylinder having a certain height, which is shown in Fig. 8(d), by symmetrically chopping off the top and the bottom vertices. If the body of the structure is surrounded by open areas, under etch happens at all convex corners as well as at sidewalls that are not aligned with the (111) planes. In this case, the structure can often be released by outside-inside process. If the thickness of the exposed sidewalls is smaller than the minimum thickness is necessary to connect all the under etched cavities, outsideinside process is the only possible mechanism of release. On the other hand, if the thickness is larger than that thickness, which can be determined using above figures and the particular design features, inside-outside process will generally dominate the releasing process since it happens at all the unprotected sidewalls simultaneously and thus shorter time is needed. Figure 9 illustrates the flow of the fabrication process, which begins with double side polished (111) SCS wafer. First, a silicon oxide layer is thermally grown in an oxidation furnace after a standard RCA cleaning step, as shown in Fig. 9(a). For photolithography, we chose AZ5214 photoresist and processed it with image reversal and lift-off techniques to pattern a thin layer of Cr on top of the silicon oxide layer, as shown in Fig. 9(b). The Cr etch mask, which can also be replaced by thicker photoresist, Figure 8. Shapes of under etched cavities. was used to make the subsequent etch into the silicon (a) Under etched cavity if T / D < 2 . dioxide faster and more anisotropic since higher energy can (b) Under etched cavity if T / D = 2 . be employed in the dry etching steps that follow. Thus, the pattern is transferred to the silicon dioxide layer and the (c) Under etched cavity if T / D > 2 . , where silicon substrate by dry etching in a RIE system, as shown (d) Under etched cavity if D = 0 in Fig. 9(c) and (d), which is similar to the process D is the diameter of holes, T is the discussed in Sec. 2. This process forms the major structure, thickness of exposed sidewalls. and the etch depth here determines the thickness of the resulting slab. After stripping the Cr layer, to avoid contamination of the oxidation furnace, the RCA cleaned sample is dry oxidized at 1100˚C in order to create a 150nm layer of high-density silicon dioxide, as shown in Fig. 9(f). The oxide layer produced here should be thick enough to protect the sidewalls Proc. of SPIE Vol. 4984
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during wet chemical etching. The process, as described in step (c) is repeated for a shorter time to expose the bottom silicon surface for further dry etching, as shown in Fig. 9(g). In order to expose sidewalls for the wet etch release, the structure is deepened using a similar multi-step dry etch process as described in step (d), except that low energy, high pressure isotropic dry etching is used instead of high energy, high pressure to preserve the less robust silicon dioxide that had taken the place of Cr as the etch mask. This deepening of the structure determines the gap between the bottom surface of the slab and the silicon substrate. After the desired depth is obtained, Fig. 9(h), the structure is ready to be released. At this point, the sample is immersed in a 33%wt KOH solution at 80˚C, and thus released as shown in Fig. 9(i). Finally, as shown in Fig. 9(j), the sample is dipped in buffered oxide etchant (BOE) to strip off the silicon oxide layer, rinsed in DI water, and dried. To demonstrate this process, we fabricated a suspended PhC structure designed to operate in the THz regime of λ ~ 10µm, which includes a photonic crystal slab with a triangular lattice of air holes and a 60˚ angle bended waveguide that is formed by a line defect. The period of the lattice and the diameter of holes are 3.89µm and 2.95µm respectively. The photonic crystal lattice is 40 periods deep and is about 150µm long. The resulting device had a threedimensional bandgap between 8.59µm and 12.08µm. The fabricated device is shown in Fig. 10. The slab PhC structure is supported by a tapered waveguide that has been completely released from the substrate after KOH wet etching. The smooth bottom surface is formed by a (111) plane, which can be seen in the figure. The fabricated structure is about 6µm thick and is suspended 7µm above the substrate. Both the slab thickness and the gap are controlled during the etch process. With the deep RIE technique developed above, we feel that the structure and the separation can range from less than a micron to tens of microns. At the beginning of the wet etch, the etch-front starts from convex corners and dominates the release. As long as the under etch process inside holes connects these etched cavities together, both mechanisms Figure 9. Illustration of the various steps in the contribute to the release. Straight waveguides fabrication process for suspended silicon slab surrounded by open areas remain thereby attaching PhCs in a bulk silicon wafer. the released slab to the substrate for mechanical support.
5. SUMMARY In this paper we have introduced and described several new and novel methods for the realization of photonic crystal devices in silicon slab waveguides. To this end, we discussed a high fill-factor dry etch process based on sidewall passivation. Then we talked about grayscale lithography and etch processes to realize high efficiency tapered horn coupling structures and finally we discussed two alternate methods 98
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for realizing suspended PhC silicon slabs for the fabrication of photonic crystal devices, namely a copolymer based approached and a combined dry/wet etch process. While the later two processes are still being refined, initial results indicate that they may represent more cost efficient processes for the manufacturing of photonic crystal devices and circuits.
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Figure 10. (a) Front view of the suspended structure, (b) Side view of the suspended structure, and (c) zoom-in picture of photonic crystal lattice.
6. REFERENCES
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