Novel Random Sequence Generation and Validation ...

Proceedings of the International Conference on Communications, Networking and Signal Processing (ICCNASP-2013), VIT University, Vellore, India. 19-21, September 2013.

Novel Random Sequence Generation and Validation using FPGA Thottempudi Pardhu1, Usha Rani Nelakuditi1 and P. Suresh1 Abstract— Random numbers with various probability distributions plays a key role in many applications of various engineering streams. Especially in communications and radar applications random numbers with Gaussian distribution are more used for functional simulation and validation of designed systems. But most of the random numbers are statistically independent and likely probable. Hence their distributions are uniform. Hence in this paper validation and simulation of pseudo random sequence with Gaussian distribution is explained. This is implemented using “Improved Tausworthe architecture with CORDIC IP” core and is also validated with chipscope pro hardware debugging validation tool. The results are also compared and checked against existing Box-Muller technique which is implemented in NI LABVIEW. Keywords— PRNG, Tausworthe, Chipscope, NI LABVIEW 1

I. INTRODUCTION In many communication engineering applications, developed digital systems are tested by using sequence of numbers. A random number generator (RNG) is a device designed to generate a sequence of numbers or symbols that don‘t have any pattern. Hardware-based systems for random number generation are widely used. Methods for generating random sequences have existed since ancient times, including dice, coin flipping, the shuffling of playing cards, the use of yarrow stalks and many other techniques.[2] In general there are two principal methods used to generate random numbers. One measures some physical phenomenon that is expected to be random and then compensates for possible biases in the measurement process. The other uses mathematical algorithms that produce long sequences of apparently random numbers, which are in fact completely determined by an initial value, known as a seed. The former one is known as True Random Number Generator (TRNG) [2] and he later is known as Pseudo Random number Generator (PRNG). A pseudorandom number generator (PRNG) is an algorithm for generating a sequence of numbers that approximates the properties of random numbers. The sequence is not truly random but are close to true random numbers can be generated using hardware random 1

number generators.These are important in the simulations many applications like cryptography algorithms etc. [3] A PRNG can be started from an arbitrary starting state using a seed s. It will always produce the same sequence thereafter when initialized with that state. The maximum length of the sequence before it begins to repeat is determined by the size of the state. However, since the length of the maximum period doubles with each bit of 'state' added, it is easy to build PRNGs with periods long enough for many practical applications. Some of the algorithms that generate pseudo random numbers are Blum Blum Shub, Inversive congruential generator, ISAAC (cipher), Lagged Fibonacci generator, Linear congruential generator, Linear feedback shift register, Mersenne twister, Multiply-with-carry, WellEquidistributed-Long-period Linear, Xorshift.[4] Fast algorithms with various distributions are desirable for generating pseudo random numbers. In communication and radar simulation environment random numbers with gauss distribution are usually used. In statistical computation random numbers with uniform distribution are commonly used.[1]. The many applications of randomness have led to many different methods for generating random data. These methods may vary as to how unpredictable or random they are, and how quickly they can generate random numbers. This paper is organized as follows. In sectionII Conventiontional Pseudo Random Number Generation is presented. Section III gives the detailed description about generation of Random numbers using Improved Tausworthe architecture. Implementation of the problem is explained in section IV. Finally section V covers results and conclusion. II. GENERATION OF RANDOM NUMBER USING LFSR Linear Feedback Shift Register (LFSR) as shown in figure.1 is used to generate a random number. LFSR is a shift register whose input bit is a linear function of its previous state. Thus, an LFSR is most often a shift register whose input bit is driven by the exclusive-or (XOR) of some bits of the overall shift register value. Any long LFSR counter generates a long pseudo-random sequence of zeros and ones. The sequence is not exactly random since it repeats eventually, and it also follows a mathematically predictable sequence. But for most practical purposes it can be considered random. A 63-bit LFSR counter has a repetition time of (263-1) clock

Vignan University, Vadlamudi, Guntur (Dist)

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Novel Random Sequence Generation and Validation using FPGA

periods. Running at 50 MHz, such a counter repeats after more than five thousand years (5,849 years to be more precise), which is long enough to be irrelevant for most practical purposes. Based on the LFSR length different XNOR feedback taps are required to generate a maximum-length random numbers. The XNOR feedback tap points to some LFSR are shown in Table. 1

In this paper Tausworthe architecture is implemented using Xilinx ise 12.4 v using VHDL.The generated output is compared with the existing Box-Muller algorithm

Table 1

No of bits in LFSR 3 4 5 6 7 8 9 10 16 32 64 128

Fig. 2: Improved Tausworthe generator architecture.

Bit positions for XNOR tap points

which is described below for two random variables. Let and be the uniform random variables belong to interval [0,1), and be the Gaussian distributed sequence with zero mean and unit variance. Then, the generated sequences are in the form of Gaussian format, which are described by equation 1

3,2 4,3 5,3 6,5 7,6 8,6,5,4 9,5 10,7 16,15,13,4 32,22,12,1 64,63,61,60 128,126,101,99

(1) and can be generated by the architecture illustrated in figure 2.[5] IV. IMPLEMENATION start

L-bit random number

1

...... ..

N+1

….. .

q

……

N+L

…..

HDL program

p

P2 Synthesis

XOR Fig. 1: Random number generation using LFSR

.bit file generation

Though LFSR is good for different applications for generating various patterns. Speed and randomnessexisted with this pattern is less

Download into FPGA

III. GENERATION OF RANDOM NUMERS USING IMPROVED TAUSWORTHE ARCHITECTURE

.cdc file generation

To improve the randomness and the speed of sequence generation Tausworthe architecture is used as shown in Figure.2. In this one p-bit long shift register with L -bit output somewhere between the first and pth bit, and a two-input XOR element feeding the result to1 the first bit would be required. Such architecture would be slow, because L clock cycles are needed to update completely the output bit position which is as shown in Figure.2 as show below. Using this improved architecture, the throughput can be increased to L times of the conventional LFSR, where L indicates the output bit length.

Verification in chipscope

End Fig. 3: VLSI implementation of PRNG using Tausworthe Architecture.

In this paper conventional pseudo random sequence generation is implemented using conventional LFSR, Tausworthe architecture and Box-Muller techniques are

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Proceedings of the International Conference on Communications, Networking and Signal Processing (ICCNASP-2013)

implemented. For proper sequence generation CORDIC IP core is included with Tausworthe architecture and simulated. In this work Tauswothe architecture is implemented in Xilinx ise 12.4 v and validated in chipscope pro. Box-muller technique is implemented in NI LABVIEW. Both the results are compared. Figure.3,Figure.4 shows the VLSI implementation flow of Tausworthe architecture and LABVIEW implementation of PRNG using Box-Muller Technique. HDL code is generated, simulated and synthesized bit file is generated using VHDL.It is dumped into FPGA. By adding. cdc file, code code is verified using Chipscope Pro. In the similar manner, existing similar Box-Muller algorithm is tested using NI LABVIEW and simulated.

Fig. 6: Implementation of PRNG using BoxMuller Part-II

Start

GUI Implementation Fig. 7: Simulation result of Random number using CORDIC IP

Simulation

End Fig. 4: LABVIEW implementation of PRNG.

V. RESULTS & CONCLUSION VHDL code for random number generation is dunpeds into Virtex-V FPGA.We used CODIC IP and Chip scope Pro to analyze the design.Figure.5, Figure.6, Figure.7, Figure.8 represents the Implementation of PRNG using Box-Muller part-I,II, CORDIC IP implantation of random number, output using chipscope. The LAb-view implementation is shown in Figure.5 and 6 respectively.

Fig. 8: Validation result of Random number using Chipscope Pro.

The simulation result is shown in Figure.7. The validation result using chip scope is shown in figure.8. VI. CONCLUSION

Fig. 5: Implementation of PRNG using BoxMuller part-I

In this paper random sequence generator used for many engineering applications are implemented in 3 ways. In the first method it is implemented using LFSR method. It is found the randomness existed with the generated sequence is less. It is corrected by using Tausworthe architecture. It is implemented in VHDL and analyzed with Chipscope Pro. It is observed that randomness existed with this is high and also throughput is high.The functionality of Tausworthe architecture is also cross checked by the implementation of CORDIC 297

Novel Random Sequence Generation and Validation using FPGA

algorithm- It is concluded that Tausworthe architecture throughput and randomness is high. But the speed performance is not improved much.

[3] [4] [5]

REFERENCES [1]

[2]

C.Wei, C.He and H.Y.Qiu, “VLSI implementation of universal rand number generator,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., pp. 465-470, 2002.

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http://en.wikipedia.org/wiki/Random_number_generation #cite_ref-0. http://en.wikipedia.org/wiki/Pseudorandom_number_ generator#cite_note-0 http://en.wikipedia.org/wiki/List_of_random_number_generators D.U.Lee, J.D.Villasenor, W.Luk, P.H.W.Leong,” A hardwae Gaussion noise generator using Boxmuller method and its error analysis,” IEEE Trans. Com put., vol. 55, no. 6, pp. 659-671, Jun. 2006.