OFDM Transceiver using Verilog

BRADLEY UNIVERSITY

OFDM Transceiver using Verilog Project Proposal By: Paul Pethsomvong Zach Asal

Advisors: In Soo Ahn Yufeng Lu

Senior Project Fall 2013

Functional Description of Project OFDM has been widely used in a variety of digital communication systems such as digital video broadcasting, IEEE-802.11, IEEE-802.15, IEEE-802.16, and 4G cellular technology. The communication systems using OFDM are resilient to multipath fading in wireless environments and have low intersymbol interference. Fast Fourier transform (FFT) is the critical operation in OFDM. There are many existing high-throughput and computation-efficient algorithms for the implementation of FFT. With parallel processing in hardware, FPGA provides higher processing power than digital signal processing (DSP) chip sets. For fast changing standards in communication it is more cost effective to implement a new system by reprogramming FPGAs. Verilog, one of the dominant design tools in the industry, is used to implement the OFDM system on a FPGA. The project aims to design and verify a complete orthogonal frequency division multiplexing (OFDM) system on field programmable gate arrays (FPGA) using Verilog hardware description language. A system consisting of a transmitter and receiver will be implemented using OFDM techniques. System Block Diagram A system block diagram is shown in Figure 1. It includes IFFT, cyclic prefix, modulator in the transmitter, and FFT, cyclic prefix removal, demodulator blocks in the receiver.

Figure 1 High level system block diagram of OFDM system

Transmitter An OFDM signal consist of a sum of orthogonal subcarriers. The subcarriers are modulated independently using amplitude modulation. The cyclic prefix is used as a guard interval in order to reduce the intersymbol interference. The cyclic prefix will be added before modulation and removed after the demodulation. Parallel-to-serial conversions are required to transmit data through the system after taking the IFFT. Receiver The transmitted signal will be received and then demodulated. As seen in the transmitter, serial-toparallel conversions are required to manipulate data through the system. To obtain the original signal the cyclic prefix must be removed and then the FFT must be taken. Simulations

Figure 2: OFDM after IFFT

Figure 1 shows the matlab simulation of the ofdm after IFFT. OFDM is inherently sinusoidal so the output is expected.

Figure 3 OFDM after IFFT two frequencies

Figure 2 shows the simulation after IFFT using two frequencies. It can be seen that the two sinusoidal wave forms combine. Simulink Model with input output

Figure 4 OFDM Simulink Model

Figure 5 Input/output of Simulink model

When the sound file is sent through the OFDM transceiver with simple channel noise, figure 4 is the results. Performance Specifications The specifications for the OFDM transceiver is listed. The values have been modified to match the equipment available. Specifications will have a tolerance of 5%. FPGA board (XtremeDSP Development Kit-IV) FPGA boards will be reprogrammed to implement the system. One board will be used for the transmitter and the other will be used for the receiver. Analog-to-digital converter (ADC) and Digital-to-analog converter (DAC) The analog data must be converted to digital to be used by the FPGA and the digital data from the FPGA will be converted to analog for display on oscilloscope. The FPGA board has two independent ADC and DAC channels. Specifications Channel Bandwidth Channel Spacing Symbol Rate Sub Carriers Sub Carrier Spacing Symbol time FFT size Table 1: Specification list

IEEE 802.11a 5 GHz 20 MHz 2048Kbits/sec 1024 312.5 K 4.88 * 10^-7 64

Chosen Specifications 5 MHz 20 KHz 128 bits/sec 32 312.5 Hz 7.81 * 10^-3 16

Channel bandwidth 5MHz is chosen because the range of equipment for IEEE 802.11a is approximately 4.9 – 6.1 GHz. A result of %MHz is obtained from 5Ghz divided by 1000.

Channel Spacing 20 MHz is the standard channel spacing for IEEE 802.11a In order to match our equipment 20MHz is divided by 1000 which results in 20KHz. Symbol Rate The IEEE 802.11a standard is a range of 6-54 MBits/sec. A symbol rate of 128 bits/sec is chosen. Number of sub carriers The number of sub carriers must be less than the symbol rate so 32 is chosen. Sub carrier Spacing 312.5 is chosen for Sub-carrier spacing Symbol time Symbol time is (1/symbol rate) => [1/ (2048Kbits/second)] = (7.81 * 10^-3) FFT size 64 is standard FFT size for IEEE 802.11a Schedule

Table 2: Schedule of tasks Paul Pethsomvong will do the Transmitter and Zach Asal will do the Receiver. Equipment The equipment required will be an FPGA board – XtremeDSP Development Kit-IV, Xillinx software to code Verilog, and an oscilloscope.

References 1. Couch, Leon W. Digital and Analog Communication Systems. New York: Macmillan, 1983. Print. 2. Gaught, Anthony. Reconfigurable Communication System Design. October 2012. 4 Nov. 2013 3. "Orthogonal Frequency-division Multiplexing." Wikipedia. Wikimedia Foundation, 11 Jan. 2013. Web. 04 Nov. 2013. 4. Thacker, Corey McKinney. An Initial Design of an OFDM Transceiver. N.p., May 2010. 4 Nov. 2013.