IEEE TRANSACTIONS ON MAGNETICS, VOL. 49, NO. 1, JANUARY 2013
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Offset Compensation Based on Distributed Hall Cell Architecture Pavel Kejik
, Pierre-François Bourdelle , Serge Reymond , Fabrice Salvi , and Pierre-André Farine Institute of Microelectronics, EPFL, Lausanne 1015, Switzerland Sensima technology SA, Gland 1196, Switzerland LEM SA, Plan-les-Ouates 1228, Switzerland
A new offset reduction strategy for CMOS Hall devices is proposed. The novelty is to fragment the Hall device into multiple Hall blocks, distributed over the silicon area and easy to interconnect. The suitable number of Hall blocks and the bias current level in each block can be adjusted according to the requirements in terms of offset, offset drift and signal to noise ratio. A chip was fabricated in 0.35 m CMOS standard technology to demonstrate the potential of this architecture. The chip shows promising results, and in particular, a very low offset drift was observed at the front-end output stage (of the order of 10 nT/ C). Index Terms—CMOS, Hall device, noise, offset, spinning current technique.
I. INTRODUCTION
T
HE Hall cells intended for industrial applications are mainly produced in silicon integrated circuit technology. Recently, the increased use of other technologies, such as GaAs, InAs and InSb, have been reported [1]. However, a single chip solution comprising the Hall cell and the accompanying electronics has only been realized in silicon technology. A poor mobility of the silicon comparing to other III–V high mobility materials makes the sensitivity of a Hall device integrated in a traditional CMOS process low and therefore offset susceptible. Typical offset level of a Hall plate device is in the range of 10 mT, or 500 uV if converted with a typical voltage related sensitivity of 0.05 V/VT and a bias voltage of 1 V. The most efficient method to suppress the offset of the Hall device itself is the spinning current technique [2]. Its efficiency depends on the Hall device bias conditions and the suppression factor is in the range of 50 to 500. It means that the front-end electronics has to treat the signals in the submicro volt range. We show here that such low residual offset can be obtained by fragmenting the Hall device into small elementary blocks. II. DISTRIBUTED HALL CELL ARCHITECTURE
The limiting factor of the residual offset is the device nonlinearity, i.e., the fact that local resistance in the Hall sensor depends on the current density. According to the reverse field reciprocity principle [3], the spinning current method completely cancels the offset in a linear system. As the system becomes nonlinear, the efficiency of the spinning current method decreases, and therefore a residual offset remains. It is now well understood that the major cause of nonlinearity is either the junction field effect [4] or the carrier velocity saturation [5], depending on the device geometry. In both cases the nonlinearity increases with the device bias voltage. In order to design a Hall micro-sensor with low offset and offset drift, the first step is to keep the bias voltage across the Manuscript received July 11, 2012; revised September 03, 2012; accepted September 04, 2012. Date of current version December 19, 2012. Corresponding author: P. Kejik (e-mail:
[email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMAG.2012.2219615
Hall micro-sensor low. Typical offset values, as a function of the voltage applied on a cross-shaped CMOS integrated Hall cell, are shown in Fig. 1. The residual offset was obtained as an average value after applying four-phase spinning current method at zero magnetic field. Note that the residual voltage is divided by the sensitivity to be expressed in magnetic field units. As Fig. 1 shows the importance of keeping the bias voltage low. However, reducing the bias voltage degrades the signal-to-noise ratio, since it is the thermal noise that is almost independent on the bias voltage and at a certain level becomes dominating. The solution to recover the signal-to-noise ratio is to integrate an array of Hall cells, each one weakly biased. Such an array should be scalable and easy to integrate without layout limitations. A good candidate to realize this is a differential difference amplifier (DDA) topology [6], offering flexibility in choosing the number of inputs. An example of DDA with two differential inputs is shown in Fig. 2. The output of the circuit is proportional a sum of the differential inputs and can be expressed as
where is the open-loop gain of the DDA. Two Hall cell are connected to differential input pairs 1 and 2 in order to generate the signal, whereas a feedback pair is used for the gain stabilization. For a simple Hall cell array realization, the number of inputs of the DDA can be arbitrarily increased and wired to Hall cells. However when reaching certain number of inputs, the floor plan becomes complicated. In addition, since all routing lines have to converge to an off-centered DDA block, the layout symmetry is broken. We propose to associate each Hall cell with the bias circuit and a part of the amplification stage that, conveniently allows a parallel connection. These elements form an elementary block (EB), as shown in Fig. 3. More precisely, the EB consists of a Hall device, a switch box, a current source and the differential pair of the input stage of the DDA. The switchbox is driven by logic signals A, B, C and D to perform four-phase spinning current. The differential pair converts the Hall sensing voltage to a current signal, easily summed by parallel connection of and in Fig. 3(b). The EB terminals are placed on the sides symmetrically along y-axis to easily
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Fig. 3. Elementary block (EB), building unit for “distributed Hall cell architecture”; block (a) and schematic (b) interpretation.
Fig. 1. Typical residual offset as a function of the bias voltage applied on an integrated Hall cell.
Fig. 2. Example of a single ended DDA topology with two differential inputs. The number of inputs can be increased by connecting other differential pairs in parallel.
Fig. 4. Floorplan of two channel Hall microsystem based on the Distributed Hall Cell Architecture.
III. CIRCUIT REALIZATION build up a row containing N EB’s. The Hall cells in the row are then operating in parallel. Since the Hall signals are correlated, the sum of currents represents the useful signal, whereas the intrinsic offsets of Hall cells are uncorrelated and averaged over N. The current signal is reconverted into a voltage in the second stage of the DDA, which terminates the row. The complete row with its DDA 2nd stage block forms one front-end channel. As depicted in Fig. 4, the front-end channel can be replicated by mirroring along the x-axis in order to obtain a differential output and suppress undesirable systematic offsets generated by the electronics. Hence, the topology of such system is “distributed” and symmetrical with respect to one centre-line. This architecture allows selecting a good trade-off between offset reduction, sensitivity and current consumption. Here, the system is completed by demodulators based on switched-capacitor circuit, output buffers and conditioning circuits for each channel to obtain a stand-alone magnetic micro-sensor. The back-end circuit is similar to the system reported in [7].
We have realized the system in 0.35 m CMOS standard technology. The test system is built of 16 EB’s, equally distributed in the central part of the layout. The Hall signal is processed in a differential way and can be monitored in modulated form at the output of each DDA, or demodulated using switched capacitor technique with variable clock frequency, depending on the required signal bandwidth. The DDA input pair was optimized to match the thermal noise performances of the Hall device. The logic circuit is either driven by the internal clock: a 2.6 MHz RC relaxation oscillator with frequency dividers, or externally controlled. This allows testing the circuit from the kHz range up to 1.3 MHz of modulation frequency. The bias current of Hall cells can be externally controlled by a current source for testing purposes. The layout size is of 1.6 1.6 mm . The photograph of the chip is shows Fig. 5. The third EB of the upper row is zoomed out and the Hall device location is schematized by a cross shape. The total current consumption depends on the value of the Hall cell bias current: when applying 500 A on
KEJIK et al.: OFFSET COMPENSATION BASED ON DISTRIBUTED HALL CELL ARCHITECTURE
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Fig. 5. Photograph of the microsystem mounted on a PCB.
each Hall cell, the overall current consumption is of 25 mA at 3.3 V supply voltage.
IV. RESULTS AND DISCUSSION
Fig. 6. Differential residual offset vs. temperature for sample #1. The Hall cell bias current was swept from 100 A to 600 A, a difference at the outputs of the front-end channel 1 and channel 2 was measured for each temperature step. (The order of curves in the graph corresponds to the order in the legend.)
TABLE I OFFSET DRIFT SUMMARY
To study the residual offset behavior and its origin in the system, we use an experimental setup where the temperature and the Hall cell bias current can be swept. A 6-layer permalloy magnetic shielding was used to protect the system from environmental noise and suppress the external magnetic field. The tests were performed on three randomly selected samples. We monitored the differential offset between the channels (this is the final offset of the system), but also the individual offset of each channel. The system sensitivity depends on Hall cell bias current, for instance with a 500 A bias current per Hall cell, the measured overall sensitivity was 21 V/T. A. Characterization on Front-End Part When realizing a low offset system it is crucial to know the offset origin in the system. For this purpose the modulated signal at the output of the DDA was monitored and demodulated with an external lock-in amplifier, synchronized by a logic signal coming from the system. A relatively low modulation frequency of 5 kHz was selected to neglect the settling time of the DDA and the spikes generated by switches. The Hall bias current was swept from 100 A to 600 A for each temperature step. Since the Hall voltage is modulated at the input of the DDA, the residual Hall offset can be separated from the DDA offset by the demodulation and extracted from the measurement. The offset drift was measured in a temperature range from to 100 C. Fig. 6 shows the differential offset drift for various Hall bias current measured on sample #1. For bias currents less than 200 A, the offset drift is hidden by the noise. For Hall bias currents
higher than 300 A, the offset drift shows an increase similar to the behavior shown in Fig. 1. A summary of the offset drift for samples #1, 2, and 3 is presented in Table I.
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Fig. 8. Input referred noise of the system including back-end part, Hall cells bias current is of 500 A per cell. The modulation frequency is of 1.3 MHz. Fig. 7. Differential residual offset drift in temperature for three different Hall bias currents measured on sample #1, including back-end part of the system. The modulation frequency was 5 kHz.
B. Full System Characterization The system was also tested with the back-end part for the signal demodulation. It was observed that the individual and differential offset drift strongly varies from sample to sample for high modulation frequencies (above 100 kHz). The variation decreases at lower frequency. Therefore, the modulation frequencies selected for the tests were 1.3 MHz as an upper limit determined by the simulation, and 5 kHz, the same frequency used in front-end part characterization for comparison purposes. The offset behavior of sample #1 for three different Hall bias currents at 5 kHz of modulation frequency is presented in Fig. 7. It is evident that the system offset expressed in teslas improves with the higher Hall cell bias current, or higher signal from front-end part of the system. It comes to this, that the residual offset of Hall cells is completely hidden by the offset generated by back-end part. The differential offset at the output of the system is more than one order of magnitude worse than the differential offset of the front-end part only when running the system at 5 kHz. For a 1.3 MHz modulation frequency the offset degradation is even worse. The suspected sources of offset and offset drift in this case are temperature instability of: 1) settling time of the DDA; 2) current leakage of the CMOS switches discharging the capacitors in SC circuit; and 3) parasitic spikes generated by charge injection. C. Noise Measurement Fig. 8 shows the input referred noise spectrum density measured at the output of the system for 500 A of Hall bias current. The fact that the system is composed of 16 Hall cells, the signal-to-noise ratio is improved by a factor of sqrt(16), i.e., four times, compared to a single Hall cell system with the same bias conditions. The spectrum is essentially free from 1/f, the noise level is about 100 Hz, resulting in better noise behavior compared to a micro-tesla resolution system reported in [8].
V. CONCLUSION The new approach for offset compensation of Hall cell based micorsystems was described and silicon proven. We demonstrated a strong potential of this technique on a front-end block with 16 Hall cells distributed over the CMOS circuit. The offset was reduced down to nanotesla range per degree Celsius, while keeping high magnetic sensitivity of the system. The technique enables reducing the offset drift on the front-end part, whereas traditional back-end solutions based on switched-capacitor circuit seems not to be well compatible with our solution and need to be optimized. Other features of the presented technique are compactness and scalability. The solution is well adapted for monolithic integrated circuits for applications where extremely low offset drift is required, such as contactless current measurement or precise proximity detection based on Hall technology. ACKNOWLEDGMENT This work was supported by the Swiss CTI Grant 9591.1. REFERENCES [1] I. Shibasak et al., “Properties and applications of InSb single crystal thin film Hall elements,” in Proc. Techn. Digest 18th Sensor Symp., 2001, pp. 233–238. [2] P. Munter, “A low-offset spinning-current Hall plate,” Sens. Actuators A, Phys., vol. 21–23, pp. 743–746, 1990. [3] H. H. Sample et al., “Reverse field reciprocity for conducting specimens in magnetic fields,” J. Appl. Phys., vol. 61, p. 1079, 1987. [4] R. S. Popović and B. Hälg, “Nonlinearity in Hall devices and its compensation,” Solid-State Electron., vol. 31, no. 12, pp. 1681–1688, Dec. 1988. [5] S. A. Solin et al., “Thin, horizontal-plane Hall sensors for read heads in magnetic recording,” Meas. Sci. Technol., vol. 8, pp. 1174–1181, 1997. [6] H. Alzaher and M. Ismail, “A CMOS fully balanced differential difference amplifier and its applications,” IEEE Trans. Circuits Syst. II Briefs, vol. 48, no. 6, pp. 614–620, Jun. 2001. [7] P. Kejik, E. Schurig, F. Bergsma, and R. S. Popovic, “First fully CMOS integrated 3D Hall probe,” Transducers’05, pp. 317–320, June 5–9, 2005. [8] V. Frick, L. Hebrard, P. Poure, and F. Braun, “CMOS microsystem front-end for microtesla resolution magnetic field measurement,” in Proc. ICECS 2001, Sep. 2001, vol. 1, pp. 129–132.
