Operation Of A Novel Negative Differential Conductance Transistor ...

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IEEE ELECTRON DEVICE LETTERS, VOL. 18, NO. 9, SEPTEMBER 1997

Operation of a Novel Negative Differential Conductance Transistor Fabricated in a Strained Si Quantum Well S. J. Koester, K. Ismail, K. Y. Lee, and J. O. Chu

Abstract—The operation of a negative differential conductance (NDC) transistor fabricated on a high-mobility Si/Si10x Gex heterostructure wafer is described. The drain characteristic of this device shows a large NDC with current peak-to-valley ratios as high as 600 (100) at T = 0:4 K (T = 1:3 K). The NDC can be modulated over a wide range of current levels by either of two separately-contacted gate electrodes. The device shows bistable switching behavior in both current- and voltage-controlled circuit configurations. The novel operating principle of this transistor is described, along with its potential for future logic and memory applications.

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T HAS LONG been appreciated that semiconductor devices that give rise to a negative differential conductance (NDC) have potential to produce analog and digital circuits with greatly reduced complexity compared to conventional transistor circuits [1]. With the continued miniaturization of integrated circuits (IC’s), such devices could play an important role in further increasing the computation capacity and speed of future IC generations. The most common NDC devices that are presently being considered for such applications are resonant tunneling diodes (RTD’s) [2], [3] and (resonant) interband tunneling diodes (ITD’s) [4]. However, these devices have several undesirable features including the difficulty of adding a third control terminal [5], [6], performance degradation when lateral dimensions are reduced [5], [7], and incompatibility with conventional Si technology. Very little progress has been made regarding the latter issue, and it is only recently that weak NDC has been observed in three-terminal Si tunneling devices [8], [9]. In this letter, we describe the operation of a novel, laterally-patterned, three-terminal NDC device fabricated in a strained Si quantum well. This device produces current peak-to-valley ratios (PVR’s) as high as 600 (100) at K ( K). Furthermore, the NDC can be modulated over a wide current range using either of two separately-contacted gate electrodes. We describe some applications of this device for logic and memory circuits, and suggest that the device operation is due to a physical mechanism that is entirely different from conventional RTD’s and ITD’s. The starting point for the device design is a Si/Si Ge quantum well grown on a Si wafer by ultra-high vacuum Manuscript received March 4, 1997; revised May 1, 1997. The authors are with the IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 USA. Publisher Item Identifier S 0741-3106(97)06680-9.

Fig. 1. Source current versus drain-to-source voltage for a double-barrier device at T : K, for different values of the dot voltage, Vdot and a fixed : V. Inset: Schematic plan view of device barrier voltage of Vbar geometry, drawn to scale. The hatched regions depict areas that have been etched.

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chemical vapor deposition; the growth details are described elsewhere [10]. The layer structure consists of a 10-nm thick Si quantum well under tensile strain, grown on a relaxed pseudo-substrate. The upper barrier is composed Si Ge layer, the top 10 nm of which of a 25-nm thick Si Ge are doped n-type, followed by a 4 nm Si capping layer. K The 2D electron concentration and mobility at are cm and cm /Vs, respectively. A schematic plan view of the device is shown in the inset of Fig. 1. It was patterned entirely by electronbeam lithography; the processing details have been previously described [11]. The device consists of a double point-contact geometry defined using low-damage reactive-ion etching, with Al gate electrodes covering the point-contact barriers and the central “dot” region. The etch depth is roughly 30–40 nm, rendering the etched regions completely insulating. The drain and source Ohmic contacts are located about 100 m from either side of the device (top and bottom in the figure), and characteristic. No have no anomalous structure in their

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KOESTER et al.: OPERATION OF NOVEL NDC TRANSISTOR

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Fig. 2. Bistable current switching characteristic for a double-barrier device : K. The drain-to-source and barrier voltages are fixed at values of at T Vds : V, and Vbar : V, respectively.

Fig. 3. (a) Diagram of circuit configuration used to demonstrate bistable voltage switching. (b)–(d) Input-output characteristic for a double-barrier : K, for (b) Vdd : V (c) Vdd : V, and device at T : V. The barrier voltage is held at a constant value of (d) Vdd Vbar : V.

appreciable gate-leakage current ( 1 pA) is measurable at the temperatures and bias voltages described in this letter. measured as a Fig. 1 shows a plot of the source current, function of drain-to-source voltage, , taken at K. The barrier voltage is held at a constant value of V, while the dot voltage is changed from to V, in 0.2 V increments. For V, the device is off, indicating that the point contacts are forming barriers to electron transport. This is expected since the point-contact width is only 80 nm, a value less than the previouslydetermined “dead-layer” width of 130 nm [12]. At V, the device turns on abruptly, and shows a very strong NDC with increasing . We also observe a hysteresis between up and down sweeps of near the turn-on threshold. The NDC shows a strong dependence on the dot voltage, and for a given , there exists a particular value of where the value of PVR is maximum. Under optimum conditions, PVR’s as large as 600 (100) are obtained at K( K), and the NDC persists to temperatures as high as 30 K. We have previously attributed the NDC in our double-barrier device geometry to phonon emission by electrons injected into the dot region [13]. This process leads to an NDC in the following manner. At low , the point-contact barriers block all current flow. At sufficiently high , drain-induced lowering of the barrier closest to the source causes electrons to be ballistically injected across the device, leading to a peak in the current. For higher , an electron can gain enough energy to emit a phonon. If the energy of the electron after phonon emission is lower than the barrier produced by the drain-side point contact, electrons will become trapped in the dot and the current will be reduced. Further increasing causes the current to increase again due to drain-induced lowering of the point-contact barriers, and the increased energy of injected electrons. The abrupt turn on at V is believed to be due to a positive feedback mechanism where charge accumulation in the dot causes a lowering of the pointcontact barriers and a subsequent increase in the current. The

hysteresis in occurs because the excess charge stored in the dot shifts the voltage at which the point contacts block the current flow. It is evident from the family of curves shown in Fig. 1 that . bistable current switching can be obtained by sweeping at K, for constant Fig. 2 shows a plot of versus V and V. As expected, a values of pronounced current bistability is observed for values of the dot V. Within these voltage in the range limits, the current can be either in the “off-state” where pA, or the “on-state” of – nA. The values of the two stable current states differ by about five orders of magnitude. The transition between states is very abrupt, particularly when the device is switched on. However, the current bistability is not very robust, as the off-state current increases rapidly with increasing temperature, and the switching characteristic K. disappears for The data in Fig. 1 also indicate that the double-barrier device can produce bistable voltage switching given a suitable load line. The diagram in Fig. 3(a) shows such a circuit configuration, where a 10 M resistor is placed in series with the device. A particularly large series resistor was chosen in order to produce a relatively flat load line, and demonstrate the property of bistable voltage switching. For a real implementation, the resistor would be replaced by a suitable active load, such as a transistor or a similar double-barrier device. The switching behavior for a device biased in this configuration is shown in Figs. 3(b)–(d). In these figures, the V, is barrier voltage is held constant at swept between 0.1 V and 0.6 V, and the output voltage, is plotted versus , for three different values of the . For the condition where V supply voltage, [Fig. 3(b)], the output is bistable for values of the dot voltage V. The output “high” has in the range a value that varies from 0.17 to 0.22 V, and the output “low” state varies from 0.09 to 0.11 V. Therefore, the

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voltage difference between the “high” and “low” output states is roughly 0.1 V. The output state is inverted with respect to is switched high when is low, and the input, since shifts the vice versa. As seen in Fig. 3(c)–(d), decreasing , and reduces the voltage hysteresis loop to lower values of swing required to switch the output state. Decreasing the value has the opposite effect on the bistability, shifting the of , and increasing the hysteresis loop to higher values of voltage swing required for switching. The voltage bistability , has been observed over an order of magnitude change in and can be observed to temperatures as high as the NDC persists (30 K for this device.) The type of voltage bistability just described makes this device well suited for use in static random access memories (SRAM’s). In fact, the circuit shown in Fig. 3(a) is essentially is either high a single SRAM cell, since the value of . The wide or low depending upon the previous value of hysteresis loop makes the memory very stable in the standby can be adjusted to make the loop smaller mode, and when writing bit information into a cell. This type of threeterminal NDC device also has applications for logic circuits. The device has the important feature that both the input and output are voltage signals of approximately the same magnitude, making it possible to drive subsequent stages of the circuit without level shifting. The two separatelycontacted gates could be used to perform a NAND operation, and must be high in order to switch the where both device into the low output state. The device also has analog applications, such as a frequency doubler or a high-frequency oscillator. For these purposes, it would be especially important to the reduce RC time constants, and we have observed NDC in different device geometries with much lower resistance than the one described in this letter. As noted previously, the NDC has been observed to 30 K. We do not believe that this is an upper limit, and recent results indicate that the temperature performance is enhanced in alternate device geometries. The energy of the phonon involved in the emission process will ultimately limit the temperature of operation, since phonon absorption would likely disrupt the electron trapping. Based on the present knowledge of the phonon energies and scattering rates in Si [14], we believe that operation at 77 K and possibly higher temperatures can be achieved. In conclusion, we have described the operation of an Ge NDC transistor fabricated on a high-mobility Si/Si heterostructure wafer. The drain characteristic of this device (100) at K shows a large NDC (PVR K)) that can be modulated over a wide range ( of current levels by either of two independent gate electrodes.

IEEE ELECTRON DEVICE LETTERS, VOL. 18, NO. 9, SEPTEMBER 1997

The device displays bistable behavior in either current- or voltage-controlled modes of operation, and has potential for future SRAM, logic and analog circuit applications. Additional studies are needed to determine the fundamental limitations and capabilities of this new class of device. ACKNOWLEDGMENT The authors would like to acknowledge M. V. Fischetti for useful discussions, P. Saunders for help with the ion implantations, and S. Rishton for assistance with the electronbeam lithography. REFERENCES [1] W. Shockley, “Negative resistance arising from transit time in semiconductor diodes,” Bell Syst. Tech. J., vol. 33, pp. 799–826, 1954. [2] K. Maezawa and T. Mizutani, “A new resonant tunneling logic gate employing monostable-bistable transition,” Jpn. J. Appl. Phys., vol. 32, pp. L42–L44, 1993. [3] F. Capasso, F. Beltram, S. Sen, A. Palevski, and A. Y. Cho, “Quantum electron devices: Physics and applications,” in High-Speed Heterostructure Devices, R. A. Kiehl and T. C. L. G. Sollner, Eds. Boston, MA: Academic, 1994, pp. 1–77. [4] J. Shen, G. Kramer, S. Tehrani, H. Goronkin, and R. Tsui, “Static random access memories based on resonant interband tunneling diodes in the InAs/GaSb/AlSb material system,” IEEE Electron Device Lett., vol. 16, pp. 178–180, 1995. [5] P. H. Beton, M. W. Dellow, P. C. Main, T. J. Foster, L. Eaves, A. F. Jezierski, M. Henini, S. P. Beaumont, and C. D. W. Wilkinson, “Edge effects in a gated submicron resonant tunneling diode,” Appl. Phys. Lett., vol. 60, pp. 2508–2510, 1992. [6] W. C. B. Peatman, E. R. Brown, M. J. Rooks, P. Maki, W. J. Grimm, and M. Shur, “Novel resonant tunneling transistor with high transconductance at room temperature,” IEEE Electron Device Lett., vol. 15, pp. 236–238, 1994. [7] T. Schmidt, M. Tewordt, R. J. Haug, K. von Klitzing, B. Sch¨onherr, P. Grambow, A. F¨orster, and H. L¨uth, “Peak-to-valley ratio of small resonant-tunneling diodes with various barrier-thickness asymmetries,” Appl. Phys. Lett., vol. 68, pp. 838–840, 1996. [8] A. Zaslavsky, K. R. Milkove, Y. H. Lee, K. K. Chan, F. Stern, D. A. Grutzmacher, S. A. Rishton, C. Stanis, and T. O. Sedgwick, “Fabrication of three-terminal resonant tunneling devices in silicon-based material,” Appl. Phys. Lett., vol. 64, pp. 1699–1701, 1994. [9] J. Koga and A. Toriumi, “Negative differential conductance in threeterminal silicon tunneling device,” Appl. Phys. Lett., vol. 69, pp. 1435–1437, 1996. [10] K. Ismail, M. Arafa, K. L. Saenger, J. O. Chu, and B. S. Meyerson, “Extremely high electron mobility in Si/SiGe modulation-doped heterostructures,” Appl. Phys. Lett., vol. 66, pp. 1077–1079, 1995. [11] K. Y. Lee, S. J. Koester, K. Ismail, and J. O. Chu, “Electrical characterization of Si/Si0:7 Ge0:3 quantum well wires fabricated by low damage CF4 reactive ion etching,” Microelectron. Eng., vol. 35, pp. 33–36, 1997. [12] S. J. Koester, K. Ismail, K. Y. Lee, and J. O. Chu, “Weak localization in back-gated Si/Si0:7 Ge0:3 quantum-well wires fabricated by reactive ion etching,” Phys. Rev. B, vol. 54, pp. 10604–10608, 1996. [13] , “Negative differential conductance in lateral double-barrier transistors fabricated in strained Si quantum wells,” Appl. Phys. Lett., vol. 70, pp. 2422–2424, 1997. [14] C. Jacoboni and L. Reggiani, “The Monte Carlo method for the solution of charge transport in semiconductors with applications to covalent materials,” Rev. Mod. Phys., vol. 55, pp. 645–705, 1983.