Optical logic gate, Optical parallel adder, Optical

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binary division by using all optical parallel shift register, optical logic gates and optical parallel adder. ... is carried out in electronics while the payload remains in the .... [8] M.Morris Mano. ... Mano. ” Computer system architecture”.3rd edition,.
International Journal of Optics and Applications 2012, 2(1): 22-26 DOI: 10.5923/j.optics.20120201.03

All Optical Binary Divider Tamer A. Moniem Faculty of engineering, MSA, Cairo-Egypt

Abstract This paper demonstrates numerically an all-optical binary divider and its optical control circuit for unsigned binary division by using all optical parallel shift register, optical logic gates and optical parallel adder. The concept is designed at an operation speed of 100 MHz for registers and 10 MHz for binary divider, which is limited by long laser cavities formed by the optical fiber. Keywords Optical logic gate, Optical parallel adder, Optical central processing unit, optical flip flop, logic divider, SOA

1. Introduction The emergence of increasingly high speed, digital optical system, and optical processing demands an all optical divider to executing a set of optical arithmetic micro-operations. The performing of signal processing operations entirely within the optical domain would exploit the speed and parallelism inherent to optics[1, 2]. All-optical signal processing technologies are considered as a possible long-term route in the evolution of current telecommunication network and high-speed signal processing system[1]. In all-optical signal processing, all-optical binary divider is very important, which can have ultra-fast operating speed and eliminate the need of conversions between electronics and optics. The all optical Divider can be constructed with an optical arithmetic unit depicted in ref.[2], and an optical parallel-shift register[3,5] based on cascaded optical flip-flop memories driven by common optical clock pluses. The optical flip-flop memory consists of two coupled polarization switches[4,5] sharing an all-optical DeMultiplexer (DMUX 1*2), Multiplexer, all optical ADC[6], optical ALU[2,10], optical multiplier[5], and all optical divider depicted in this paper can be used in the arithmetic operation to perform a fast central processing unit using optical hardware components. Ultra-compact optical flip-flops with a switching speed greater than 100 GHz were demonstrated[7]. This means that this concept has potential to be integrated and to perform at high speed.

the quotient digits are either 0 or 1 and there is no need to estimate how many times the dividend or partial remainder fits into the divisor. When the division is implemented in a digital computer, it is convenient to change the process slightly. Instead of shifting the divisor to the right, the dividend, or partial remainder, is shifted to the left, thus leaving the two numbers in the required relative position[8].

2. Theoretical Description of Division Binary division is simpler than decimal division because * Corresponding author: [email protected] (Tamer A. Moniem) Published online at http://journal.sapub.org/optics Copyright © 2012 Scientific & Academic Publishing. All Rights Reserved

Figure 1. The ASM flowchart of unsigned binary number

The unsigned binary division process is illustrated by the ASM flowchart depicted in figure 1. The divisor is stored in register (M), the dividend is stored in register (Q) and remainder is formed in register (A). The register (A) formed by

International Journal of Optics and Applications 2012, 2(1): 22-26

the parallel-shift register according to the binary multiplier in refs.[5] and[8]. The contents of two register A and Q are shifted left and the most significant bit A3 is tested after the subtraction between the contents of registers A and M. If A3