Optical sources, integrated optical detectors and

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The respective refractive indices for the various layers (1 .... IpA). Table 2: coupling results for various optocoupler configurations as realised in CMOS integrated ...

Invited Paper

Optical sources, integrated optical detectors and optical waveguides in

standard silicon CMOS integrated circuitry Lukas W.Snyman a Herzl Aharoni 2 b Alice Biberc, Alfons Bogaleckia, Lyndsay Canninga, Monuko du Plessisa and Petrus Mareea

aCarl and Emily Fuchs Institute for Micro-electronics (CEFIM), Department of Electrical and Electronics Engineering, University ofPretoria, 0002 Pretoria, South Africa. bDepamet of Electrical and Computer Engineering, Ben Gurion University ofthe Negev,Beer-Sheva 84105 Israel. cCentre de Microtechnique de Suisse, CH2007 Neuchatel, Switzerland. ABSTRACT A series of light emitting devices were designed and realized with a standard 2 micron CMOS technology, 1 .2 micron CMOS technology and 0.8 micron Bi-CMOS integrated circuit fabrication technology. The devices operated in the reverse breakdown avalanche mode, at voltage levels of 8-20 V and in the current range 80 pA —10 mA. The devices emit visible light in the 450 — 750 nm wavelength region at intensity levels of up to 1 nWim2 (10 mW.cm2) . A series of optimized optical detectors were developed using the same technologies in order to detect lateral and glancing incidence visible and infrared radiation optimally. A series of waveguiding structures of up to 100 micron in length were designed and realized with CMOS technologies by utilizing the field oxide, the inter-metallic oxides and the aluminum metal layers as construction

elements. Signal levels ranging from 60 nA to 1 micro-amperes could be detected at the detectors of waveguiding structures of up to 100 micron in length. Finally, a complete optoelectronic integrated circuit was designed and simulated with 0.8 micron Bi-CMOS technology with some of the developed light sources, detectors, waveguiding structures and

added driving and amplification circuitry. In particular a very powerful high gain wide-bandwidth MOSFET signal amplifiers was developed that could be successfully integrated in the optoelectronic integrated circuit. The developed technologies show potential for application of optoelectronic circuits in next generation silicon CMOS integrated circuits.

Keywords: Optoelectronics, silicon light emitting devices, LED's, optical waveguides, CMOS integrated circuitry.

1. INTRODUCTION The need for optical signal transmission, had been spurred by ever-increasing information demands in computer and data processor networks covering shorter distances. High speed, high bandwidth, noise and interference immunity and electrical isolation are just some facets that suggested the superiority of optical data transmission and processing over electrical implementations 1-4 The 111-V semiconductors, like Gallium Arsenide (GaAs) and associated compounds, already form the present basis of a such a mature and popular technology. An ever-increasing potential has been identified for the integration of optical components into the mainstream silicon-based integrated circuitry technology 1-4. Procedures, for combining 111-V optoelectronic components with state-of-the-art silicon complementary-metal-oxide-semiconductor (CMOS) technology, however, still seems to be quite complex and requires

mechanical and thermo-compression procedures like flip-chip-bonding and fusing, leaving expensive technology and questionable issues with regard to mass-manufacture, durability, reliability and stability.4 Silicon pn-junctions have been known to emit visible electro-luminescence under reverse biased and avalanching


Correspondence: E-mail: lukas.Snymaneng.up.ac.za; www:http:// ee.up.ac.za.html; Tel: 27-12-4202950; Fax: 27-123625115. 2 Visiting professor at the Carl and Emily Fuchs Institute, South Africa: 1994, 1996.


In Silicon-based Opt oelectronics II, David J. Robbins, Derek C. Houghton, Editors, Proceedings of SPIE Vol. 3953 (2000) • 0277-786X100/$15.00


conditions 5,6,7

but due to it being an indirect band-gap semiconductor; silicon is traditionally considered as an inefficient light emitter. Concerns have been expressed about the practicality of Si light sources e.g. the external luminescence quantum conversion efficiency as compared to rn-v emitters.

The advantages of silicon-based light emission, however, do not lie in competing with their Ill-V relatives, but rather in cheap integration with other silicon electronics should they


soN.:: Passlvat8on


nltrld—4 _______ -ozido _________________






prove to have some viable and reliable applications.

Substantial progress has recently been made in the fundamental

studies of light emission via porous Si-based structures, Si

p-bulk (uztrato)



superlattice siructures and first iteration CMOS devices. 7-13 Our

group at CEFIM in South Africa has through recent years extensively researched silicon light sources operating in the

Fire 1: Structures andmetallurgical layers that can be reverse breakdown and avalanche mode, and has made some usedfor generating optoelectronic components in Si CMOS progresses with regard to improving the external quantum intefn-ated circuitry. conversion efficiency and realizing practical CMOS integrated 14 —23 A circuit central theme of our approach has been to utilize the various structural components as offered by the current state of the art silicon CMOS technology (Figure. 1) and design procedures as suitable "building elements" in realizing silicon light emitting devices ( Si LED's). The purpose of this article is to report on recent achievements with regard to the design and development of optical sources, integrated optical detectors and optical waveguides, using state of the art 1.2 micron, 2 micron technology with a bipolar

capability and 0.8 micron Bi-CMOS technology. The viability of application of these components into standard silicon CMOS optoelectronic integrated circuits (Si OEIC's) is also evaluated.



In a first approach (design type A), use was made of light Light emission

generation from a planar shallow np junction interface which were placed only 0.3 micron below the surface of the

silicon and a Si-Si02 interface. (Figure. 2 (a)). The "nactive" layer as offered by the Orbit CMOS 1.2 micron design technology which were embedded in a "p-well" served this purpose well. Upon reverse biasing the n+p interface into the avalanche mode, the highest fl-field region, avalanching and light emitting region is maintained close to the surface of the device. Absorption of the visible light into

Metal contacts


Bonding pad leaving a thin residual Si02 layer

Si nlayer Depletion region

is therefore minimized to only 0.2 to 0.3 micron of Si and emission of the generated light vertically outwards of the Si p-well device is maximized. The absorption vertically outwards is further maximized by defining a "bonding pad" definition area above the active light emitting regions which also etches away all silicon nitride surface passivation layers in Figure 2: Crossection of a planar, light emitting device as these regions, leaving only a transparent and thin residual designed with silicon CMOS intgreated circuit oxide surface layer on the silicon. A major further design technology. philosophy was to choose the detailed device geometry such that the dynamic potential drops created in the lower resistivity substrate region ensures a uniform electric field distribution over the whole extend of the planar n-i-p junction, thereby enhancing uniformity in eventual light emission from the planar interfaces. Appropriate "n-well" regions were also


place at the peripheries of the n+ planar region in order to act as "guard ring" structures to prevent preferential breakdown at the these peripheries. Because of the freedom in lateral two-dimensional design possibilities with this structure,

virtually any shaped planar light emitting structure can be generated in CMOS integrated circuitry with these design approaches. Figure 3 (a) and (b) shows the realization of this design concept into large area seven segment display arrangement. Upon reverse biasing of 3lV, the structures yield 1-10 nW of optical power for each 100 by 4(X) micron segment area for current values of 1-10 mA per segment The illustrated photo—micrographs illustrates the excellent uniformity in emission that were achieved. In a further design (type B) , appropriate cavities were placed in the planar n layer in order to ensure a perforated n+ layers

such that section of the depletion region and light emitting regions could actually reach the the Si-Si02. This design considerately enhanced the total light emission per unite area from the device and it was subsequently used to generate a

first-iteration optical fiber interface structure (Fig. 3 (c)). The emitted wavelength range was in the 45() 750 nm region with a broad emission spectrum (see later Figure 6). Figure 3: Examples of silicon light e,nitting


devices as realised in

silicon 1.2 micron M0S technology. (a) Integrated circuit layout for a seven segment display arrangement: (b) operation of this device under .rubdued lighting

conditions; and, (c), realisation of a first iteration Si-LE!) optical fiber interface.



In a third design approach (design type C) (Figure 4 (a)), use was made of a lateral surfce breakdown technique which occur coplanar with the conductive bodies. These Si-Si02 interface between a n and bodies were placed in a "p-base" layer as was offered by the 2 micron Orbit process and which had a bipolar capability. The p-base layer


"7 7 ? Light emission Si02 ____________________________________

1 n(+Vi

was again embedded in a lower doped "p-well" region . Upon


This implies that the maximum doping gradient between the

n+ and p-base region is experienced at the Si-Si02 intertice (Figure 4(h)). Hence, the highest E-field region is experienced at narrow region


Depletion region p (2x1017cm3) exhibiting lateral surface and Zener breakdown effects ________________________________________

I0 cm-3 to about 2 X10'7 cm at 0.5 micron depth from the Si surface.



reverse basing the np interface regions, depletion regions mainly extend laterally and adjacent to the Si-Si02 interface. Since the pbase region is a diffused layer, the doping density rapidly decay from


I on man.

near to Si-Si02 interface on the Si side, and the avalanche and light emitting processes is confined to this region. Because of the specific doping densities and gradient in these regions. the junction

break-down mechanism is Zcner a pre-dominantly breakdown mechanism. The therefore are devices characterized by a "surface" breakdown mechanism, with


Figure 4:: Illustration oft/u' lateral Si-


SIO, surftwe breakdown mechanism used

for maxiniising the vertical light enission from a CMOS silicon light emitting device fabricated in 2 micron CMOS technology. A lateral elect nc field and current density is applied between two highly conductive n+ andp+ regions in a lower doped psubstrate.

p y


p-base layer

Figure 5: Illustration of the layout and design of a point source light emitting device as realised in silicon 2 micron CMOS

integrated circuit technology . (a) Plan layout of the device; (b) cross—section oft/u' device illustrating structural composition ; (c) point source light emission characteristics at 8Vand 80 mcroampere: and (d) directional light emission characteristics at 8V and 2 mA. With a second nearhvjunctionforward biased.

virtually all light generated at

the Si-Si02 interface, and no absorption losses or current conduction in the deeper silicon suhsurfiice regions. High densities of interface states which are present at the Si-Si02 interface regions may presumably also add to a surface breakdown mechanism. The most efficient vertical emittance of the generated light could be used for the development of a number of

very efficient vertically (surface) emitting line and point source devices.

In Figure 5. the realization of point source and directional emitting devices is illustrated. Electro-luminescence was generated from a CMOS wedge-shaped np deign with a wedge-shaped n+

body embedded in a p layer of 2x10'7 cm (Fig. 5 (a) and (h)). When a reverse-biasing voltage is applied between the tip of the n wedge-shaped region edge and the p+ contacts as embedded in the p-base substrate, an electric field confinement is created at the np tip (Fig 5 (a)), with the depletion region extending laterally and coplanarly with the Si/Si02 interface. Initial avalanche breakdown is confined to the highest F-field region in a very small conlined area at the wedge-shaped tip, resulting in light emission from the surface from only a 2 jim diameter light emitting region (Fig. 5 (d))



2 3 4 5 6 7 8 9 10 Current (mA)

A luminescence intensity of about I nW per jim2 at V and at only 80j.tA of current was observed. This measurement was done by using a calibrated charge coupled device (CCD) sensor fitted to a high resolution optical microscope with all filters removed in the optical path. Using the above design concepts, appropriate line sources (Figure

Figure 6: Optical output power as a function of operating current for a line source silicon CMOS light emitting device fabricated in 2 micron CMOS technology with a bipolar capability. The spectral characteristics is also indicaLeiL.

7) were also designed (design type D). Appropriate n jj DnacveDpactive 0 p-base p+ strips were placed in either a p-base layer to cause a lateral electrical field concentration at the np interface facing the


The optical output versus current for the developed line and

point sources is presented in Figure 6.

The quantum

conversion efficiency value as measured for the point source

devices of 1.5x105 is two and a half orders of magnitude higher than earlier published values for quantum conversion

efficiencies for Si devices utilizing avalanching and hotcarrier luminescence.11 The light emitting intensity of 1nW/.i.m2 (10 mW/cm2) is according to our measurement

Figure 7: Design of a line source light emitting source as realised in 1.2 micron silicon CMOS integrated circuitry and which was used for coupling light into field oxide waveguiding structures.

and calculations comparable to amorphous based silicon light emitting sources (- lmW/cni2).12

Figure 6 also presents the spectral characteristics for the developed line and point sources. Analyses show that the characteristic peaks at 550nm and 450 nm correspond well with the characteristic threshold energy needed for the ionization of silicon host atoms by hot electron and holes, 1.8 eV and 2.3 eV, respectively. We have also related the higher obtained efficiencies with higher energy transitions that occur in the conduction and valence bands. It may also be related to

excitation of a nano-stuctured Si-Si02 interface region by means of the specific current conduction process employed here. Stability measurements showed that the emission from the device was stable over a prolonged operation period of 24 hours.

Substrate I bulk

2.3 LATERAL LIGHT- EMITTING SOURCES Appropriate line sources were designed (design type E which

primarily focus on coupling radiation with laterally placed structures like disthnt detectors or transparent field oxide layers. Appropriate n and p strips were placed in a p-well to cause a lateral electrical field concentration at the np-wel1 interface facing the p+ strip. Due to the lower doping level, the depletion layer extends deeper into the Si substrate of the p-well (2x1016 cm3 ). Optical radiation subsequently occurs much deeper into the

Figure 8: Structure of an embedded silicon light emitting

device as realised in 0.8 micron bi-CMOS technology

which couples light into a nearby field-oxide based waveguiding configuration..

£3 Metal 2




IMc" I IContact Poy-silicon I ['PoIy 2 1

silicon and propagate more radially in the Si subsurface regions.

In a further design approach (source design type F), suitable light emitting junctions were placed to locate the region of brightest light emission slightly below the apex of an adjacent transparent Si02 optical guide (figure 8). This ensures a more effective coupling of light into the guide itself and also increased the

light emitting interface area with the


Figure 9: Design layout of silicon light emitting device as realised in 0.8 micron biCMOS technology which utilised point sources e,nbedded at the apexes of lazeralfield oxide-based waveguiding structures..

" optical guide. The field oxide as it occurs in CMOS integrated circuits with its natural "birds peak shape and which results from native oxidation of the silicon during processing, ideally serves as a suitable lateral optical transmission medium for the laterally emitted light Using this concept, special silicon light sources were developed for optimally coupling light into 5i02 oto-coupler and waveguiding configurations using 0.8 micron Bi-CMOS technology. Some plan views of these designs are schematically illustrated in Figure 9: using (a) a n ("n- plus") emitter on p ("p- minus") base and (b) n well configurations. Triangular light emitting tips were especially designed in order to couple light with a large solid angle into the surrounding transparent Si02 regions.

Design type Table 1: Characteristicsfor the developed CMOS optical sources:

Typa A Type B Type C Type C

Characteristics Planar, surface emitting Planar, surface emitting Point, surface emitting Line,1OjJm ,

current lOmA

Optical outpput (450-650nm) 15 nW per 100 x


5 mA

400 pm area 10 nW per 60 m


0.8 mA

1 nW per m2


0.8 mA

1 nW per pin



-1 nW per pm




diameter area

surface emitting

Type D


Line, 1Oim, lateral emitting Line, lateral emitting



voltage 30V




,. ... ,, • .,

.. .

kinds of detectors were designed: for optimum

detection of the spectrum as shown in Figure 6, or


alternatively for the corrected wavelength specirum when the

radiation had traveled some distance through the silicon

substrate. These detectors were basically realized by incorporating structures of the p-n , p-i-n photodiodes and photoiransistor type into conventional 1.2 micron CMOS technology and 0.8 micron Bi-CMOS technology. In a first design (Figure 10) (detector type A) , use was made

to of a photodiode arrangement. The detector was designed to optimize detection of lateral and glancing incident radiation from an adjacent or distant light source positioned on the


same chip. For this purpose use was made of an array of parallel n+ strips which were connected together at the sides of the device (plan view, Figure 10). The usage of parallel n

strips facilitated the creation of a maximum and laterally elongated depletion layer volume when the np-we1l junction are reverse biased at reverse bias voltages of 5 - 30V. Using

detailed calculated depletion layer sizes and assuming an absorption coefficient of 4 x iO for the longest radiation


2m 2m 2m . _1 \\\ N \\ .

\\ \\



\ \\\\\\\ \

t\ \\ \\


components ( 750nm ) for the silicon light sources (Figure 6),

a maximum lateral absorption distance of about 10 micron were required in order to ensure a 90% absorption efficiency for all incident wavelengths ass present in the light source spectrum. The eventual detector layout sizes were about 20

Figure 10: Design layout of a silicon CMOS optical detector optimised to detect lateral and glancing incident widebandwidth optical radiation.


micron long and up to 50 micron wide relative to the incident radiation.

E:JWelctC pw& In a second design approach (Figure 1 1 (a))(detectors type B), n arrays were placed in a n- well onto the lightly doped p-substrate. Upon reverse bias, an elongated depletion region is generated at the np interface (Fig. 1 1 (b)), ensuring a very large depletion region volume at this interface which can ideally collect laterally propagated optical radiation either from origins external to the silicon or internally in the silicon.


In a third design (detector type C), it was attempted to integrate the detector active regions more closely into the optically transparent

field oxide regions as provided by CMOS technology. Use was made of a phototransistor type design as shown in Figure 12 (a) and

(b) using a p, a n-well and a p-substrate configuration. The collector region of the transistor was elongated in a lateral direction

in order to match the base length of the transistor with the maximum absorption length of the incident radiation. The radiation penetrate the elongated base region and stimulates transistorized injection of majority carrier from the n surface regions when the device was suitably biased into the transistor

Figure 12: Design layout of a complete silicon CMOS opto-coupler arrangement showing the Si light source and the Si detector laterally arranged next to each other.

active mode. Hence, the reverse biased pn junction or active base region was positioned in the area of largest photosensitivity below the apex of the terminating light guide. This promised better light detection, especially due to the internal reflection of 'a) light towards the

substrate at the end of the guide.

Figure 1 2(b) displays an improved triangular photo-transistor

Figure 11 : Design layout of a silicon CMOS optical photo-transistor arrangement with an elongated base regionfor optimum detection of wide-bandwidth radiation.


arrangement, with the active base region extending in triangular shape right around the terminating optically transparent Si-SiO2 waveguide. A two-terminal phototransistor were created by placing the base directly beneath the end of the light guide. The p-substrate b) functions as the collector, the n-well as the base and the p implants as the emitter.


The detectability limit of the detectors were determined by calculating the generation and reverse bias leakage current at room temperature for each device, according to equation taking into account the electronic charge, q, as 1.6x1019 C, the intrinsic doping concentration of silicon ,n, (1010 cm3), is the minority carrier lifetime of electrons in the p well, t (106 s),; and the area of the detector (2Otm x 5O.nn = 1000pm), A, and is the width of the

depletion region ,w(VR), (1im).

Igen = 2.-r



Using this approach, a theoretical leakage current of 0.8 pA.is derived for a photodetector as discussed in Figure 10. This led us to the most important conclusion that, that the optical power as emitted by our developed Si CMOS light sources (Table 1), are up to four orders of magnitude higher than the detectabilty limit of our specific CMOS detectors.


4. GENERATION OF SILICON CMOS OPTOCOUPLERS AND OPTICAL WAVEGUIDES An analysis was done by us24'25 of possible components of a typical CMOS integrated circuit structure (Figure. 1) that could contribute towards a possible lateral conduction of optical radiation along the chip surface. The following candidates were identified:: (1) The silicon substrate itself is transparent for longer infrared wavelength radiation , altough detection of such radiation is problematic. (2) The field oxide with its natural "birds peak " shape, which results during native oxidation of the silicon, can act as a suitable lateral optical transmission medium for visible light. (3)The intermetallic oxide as present between the "metal 1" and "metal 2" metallisation layers in the CMOS structure. (4) The natural curvatures which occur at especially "contact" and "via" holes in the metal 1 and metal 2 aluminum layer structures may act as suitable reflecting curvatures and aid towards lateral photonic conduction processes.

Figure 1 1 show the plan view of a typical opto-coupler arrangement comprising of a silicon line light source of type C and an adjacent detector as just described. The detectors were placed as near as possible to the source or optical conduction medium. A p ohmic contact strips or pf squares were always placed near to this contact region in order to eliminate any linear voltage gradients in the silicon substrate between the source and the detector. Source and detector pn regions were

normally placed in opposing ordered configurations in order to avoid any transistorized coupling effects between the source and the detector. Additionally, junctions were

p a(tve




centact [j p weR

n weU


occasionally also placed between the source and the detector in order to maximize the electrical isolation between the respective devices.

Maximum detection capability and minimum layout size

associated with the developed Si CMOS integrated detectors, however, indicated towards utilizing the field

and intermetallic oxides as optical conduction media between the light sources and the detectors. And also for the purpose of constructing possible lateral "optical

waveguides" structures in silicon CMOS integrated circuitry. Line light sources of type D and E and point light sources of type C were identified as the best candidates for constructing opto—coupler structures, consisting of a light source, an optical conducting and detector all integrated together as one integrated unit on the chip. Especially the lateral emitting light sources of type E that couples directly into field oxide layers (see

Figure 8) seemed especially viable. The "birds peak" structure could form the natural apex of a SiO2 optical guide , increase the coupling interface area, and feed


:qht emtscn occurs

it thc

oIthewavLuid section



:i dCttve s used to den th* des ot the wdveqtnth

large quantities of light directly into the field oxide layer. The respective refractive indices for the various layers (1 for air, — 1.5 for field oxide and 3.5 for Si, ensures that SeCbOfi X X internal reflection will occur for most angles of emission. Reasonable opto—coupling between sources and distant detectors as well as "lateral waveguiding" may therefore Figure 13: (a) Plan view of a silicon CMOS optocoupler and be achieved with such structures. waveguiding arrangement with n+ and p± highly doped regions

Figure 13 shows a first iteration design in an attempt to realize the above philosophies in realizing a prototype "CMOS field oxide based optical waveguide" The field oxide edges are defined by means of elongated n strips

used to define the edges of field oxide SiO2 regions. (b) XX' cross-section showing a side view of the field oxide, light source

and detector regions; and . (c) YY' cross-section through the field oxide showing the side surface definition of the waveguide.


on the Si p-substrate placed about 10 micron apart. (Fig. 12 (a)) The far-end edges of the guide are again defined by p strips where it forms part of the light source and the CMOS detector structures, respectively. On top of the lateral n strips, appropriate bonding pad definitions were defined which extended over the whole length of the guide such that sharp

fl n active E substrate

sitcon doxde

edges are defined on the sides of the guide; and a layers of intermetallic oxide and passivation nitride be left on top of the field oxide strip.

Since the refractive indice of Si (3.5) is much higher than the assumed refractive indice of the

field oxide, it can be expected that some refraction of the propagating waves occur at the Si-Si02 interface into the substrate. Considering interface 1, and using Snell's law , with n1 = 1.5 and n2 = 1, the critical angle for interface 1

Figure 14: Geometrical arrangement for a silicon field oxide optocoupler and waveguiding arrangement which were used for mathematical modelling.

is 41.8°. From this it can be concluded that all the light with an angle of incidence, O, between 45°

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