Optimised decoding of odd-weight single error correction double error detection codes with 64 bits P. Reviriego, S. Pontarelli and J.A. Maestro Error correction codes are commonly used in memories to ensure that data are not corrupted. Single error correction double error detection (SEC-DED) codes are among the most widely used codes to protect memories. One common technique to implement SEC-DED codes is to construct a parity check matrix with odd-weight columns. This ensures that double errors have an even weight syndrome and therefore are not confused with single errors thus providing the DED feature. Recently, a technique that reduces the decoding complexity for oddweight SEC-DED codes has been proposed. This technique can be used only for small data block sizes being the practical limit 32 bits. However, memories with 64 bits are commonly found in modern computing systems. Therefore, it would be advantageous to also reduce the decoding complexity for larger block sizes. A scheme to optimise the decoding of odd-weight SEC-DED codes with block sizes of 64 bits is presented and evaluated. The results show that the new scheme can provide significant reductions in the decoder circuitry area and delay.
Introduction: To protect the memories from errors, error correction codes (ECCs) are commonly used in memories [1]. Among different ECCs, single error correction double error detection (SEC-DED) codes are a popular choice. A classical construction of SEC-DED codes is to design the parity check matrix such that all the columns have an odd-weight [2]. This ensures that double bit errors produce an even weight syndrome and are not confused with single bit errors that produce an odd-weight syndrome. The use of SEC-DED codes in memories has an impact as additional bits are required to store the parity check bits and the encoder and decoder circuitries increase the area and the delay. The most complex element is typically the decoder that is composed of a syndrome computation block that recomputes the parity checks and compares them with the stored values and the error location/correction block that compares the syndrome with each of the columns in the parity check matrix to identify the bit in error that is to be corrected. Several techniques have been proposed to reduce the overhead required to implement SEC-DED codes [3, 4]. In particular, the technique presented in [4] can be used when all the columns of the parity check matrix that correspond to the data bits have the same weight and only the error in the data bits needs to be corrected. When that occurs, the decoding can be simplified as the error location can be found by comparing the syndrome only with the positions that have a one in each column. This reduces the decoder complexity and delay significantly as shown in [4]. Traditional odd-weight SEC-DED codes with data block sizes of 16 or 32 bit columns have a weight of three [2] and therefore the technique can be used. However, this is no longer the case for larger block lengths. For example, for 64 bits, some columns have a weight of five. The case of the 64 bits blocks is of practical interest as it is found in many modern computing systems. In this Letter, a technique to reduce the decoding complexity of oddweight SEC-DED codes with data blocks of 64 bits is presented. The scheme has also been implemented in HDL and synthesised in a 45 nm library to validate the reductions in the decoding circuitry area and delay. The following Section describes the proposed scheme and is followed by a Section that presents the implementation results. The conclusions and ideas for future work are summarised at the end of the Letter. Optimised decoding: The odd-weight SEC-DED codes with 64 bits data block size require eight parity check bits. Each data bit participates in an odd number of parity checks. To minimise the encoding and the decoding complexities, this number is minimised. In particular, 56 (the possible combinations of eight elements taken in groups of three) data bits participate in three parity check equations and the remaining eight in five equations. The decoding of the SEC-DED code is done in two basic steps. First, the parity check equations are recomputed and compared against the stored parity check bits. The result is known as the syndrome. In the second step, the syndrome is compared against the syndromes that would produce an error on each of the data bits. For example, if the first data bit participates in the first three parity check equations, an error in that bit is located when the syndrome
takes the value 11100000. Therefore, the syndrome is compared against that value and when they are the same the first bit is corrected. This comparison can be implemented with an eight-input AND gate. A similar comparison is made for each of the remaining 63 data bits. This second step can be optimised when the code is such that all the data bits participate in the same number of parity check equations [4]. In that case, the comparison can be reduced to check only that the ‘1’ in the syndrome matches the ‘1’ for the data bit. In the previous example, this means comparing only the first three bits which are ‘1’ in the value 11100000. This can be implemented with a three-input AND gate, thus reducing the circuit area and the delay. Unfortunately, this scheme cannot be used for the code with 64 data block size as some columns have weight three and others five. Suppose, for example, that one bit has a syndrome 11100000 and another bit 11111000. Then, if we only compare the ones in the syndrome an error in the second bit will also match the comparison for the first causing a miscorrection. The proposed decoding optimisation is based on identifying when an error affects one of the data bits that participate in the five parity check equations. Then, the bits that have a weight of three can be decoded by checking only their three ones and that there is no error on the bits with weight five. This reduces the decoding complexity as only a fraction of the eight bits of the syndrome has to be checked. To implement the idea, we first select the eight combinations of weight five such that four of them have the first four bits of the columns equal to one and the remaining four have the last four bits of the columns equal to one. This enables a simple identification of the single bit errors with weight five. For example, the following combinations can be used: 1 1 1 1 1 0 0 0
1 1 1 1 0 1 0 0
1 1 1 1 0 0 1 0
1 1 1 1 0 0 0 1
0 0 0 1 1 1 1 1
0 0 1 0 1 1 1 1
0 1 0 0 1 1 1 1
1 0 0 0 1 1 1 1
Once the weight five combinations have been selected in this way, the decoding can be done by checking for the eight columns of weight five looking only at the ones. For the 56 columns of weight three, in addition to looking at the ones we check that there are no four ones in either the first four or the last four syndrome bits. The resulting decoding scheme is shown in Fig. 1 where only the second step starting from the syndrome (s0–s7) is shown for one data bit with weight three and another with weight five. si1, si2 and si3 are the ones in the syndrome for the data bit di and s4, s5, s6, s7 and sj5 are the ones for the data bit j. It can be observed that the location of the bit in the error requires a four input AND gate for the 56 weight three data bits which are the majority of the 64 data bits. This reduces the decoder circuitry area and the delay as will be seen in the following Section where an evaluation is presented. s0
si1 si2 si3
s1 s2 s3
di
weight three bit
weight five error
s4 dj
s5 s6 s7
sj5 weight five bit
Fig. 1 Illustration of proposed decoding scheme
The proposed decoding optimisation can be used when only the errors in the data bits need to be corrected as is commonly the case [4]. Evaluation: The proposed decoding scheme has been implemented in HDL and synthesised for a 45 nm library [5]. The traditional decoding algorithm has also been implemented for comparison. The synthesis
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has been done using Synopsis DC. Two configurations were used for the synthesis, maximum effort to optimise area and maximum effort to optimise delay. The first one is useful for designs in which area is critical and the second for high-speed circuits. The results are summarised in Tables 1 and 2. It can be observed that the proposed method reduces significantly the area and the delay for both synthesis configurations. The best results are for maximum effort in area, which show reductions of over 20% for area and of over 30% for delay. These results validate the reduction in the decoding complexity of the proposed scheme.
Table 1: Area estimates in µm2 for decoder implementations Max. effort in area Max. effort in delay
Traditional Proposed Reduction (%) 3839 2978 22.4 4221 3576 15.3
Table 2: Delay estimates in nanoseconds for decoder implementations Max. effort in area Max. effort in delay
Traditional Proposed Reduction (%) 1.80 1.23 31.7 0.82
0.66
19.5
Conclusion: In this Letter, a scheme to reduce the decoding complexity of odd-weight SEC-DED codes with a block size of 64 bits has been presented. The proposed scheme can reduce significantly the area and the delay of the decoder circuitry as shown by the evaluation result presented for a 45 nm library. This makes the scheme advantageous for practical designs as block sizes of 64 bits are common in modern computing applications. Future work will consider the application of the ideas used to optimise the decoding for the 64 bit code to larger data block sizes. Acknowledgments: This work was supported by the Spanish Ministry of Science and Education under grant AYA2009-13300-C03. This Letter is
part of a collaboration in the framework of COST ICT Action 1103 ‘Manufacturable and Dependable Multicore Architectures at Nanoscale’. © The Institution of Engineering and Technology 2013 31 August 2013 doi: 10.1049/el.2013.2897 P. Reviriego and J.A. Maestro (Departamento de Ingeniería Informática, Universidad Antonio de Nebrija, C. Pirineos 55, Madrid, Spain) E-mail:
[email protected] S. Pontarelli (Department of Electronic Engineering, University of Rome, ‘Tor Vergata’, Rome, Italy) References 1 Chen, C.L., and Hsiao, M.Y.: ‘Error-correcting codes for semiconductor memory applications: a state-of-the-art review’, IBM J. Res. Dev., 1984, 28, (2), pp. 124–134 2 Hsiao, M.Y.: ‘A class of optimal minimum odd-weight column SEC-DED code’, IBM J. Res. Dev., 1970, 14, (4), pp. 395–301 3 Gherman, V., Evain, S., Seymour, N., and Bonhomme, Y.: ‘Generalized parity-check matrices for SEC-DED codes with fixed parity’. IEEE 17th Int. On-Line Testing Symp. (IOLTS), Athens, Greece, July 2011, pp. 198–201 4 Reviriego, P., Pontarelli, S., Maestro, J.A., and Ottavi, M.: ‘A method to construct low delay single error correction codes for protecting data bits only’, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013, 32, (3), pp. 479–483 5 Stine, J.E., Castellanos, I., and Wood, M., et al.: ‘Free PDK: an opensource variation-aware design kit’. Proc. IEEE Int. Conf. Microelectronic Systems Education (MSE’07), San Diego, CA, USA, June 2007, pp. 173–174
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