Optimized QPSK Modulator for DVB-S Applications G. C. Cardarilli, A. Del Re, M. Re
L. Simone
Dept. of Electr. Engineering University of Rome “Tor Vergata” Rome, Italy
[email protected]
Alenia Spazio Rome, Italy
[email protected]
Abstract—In this paper the implementation of a multirate QPSK modulator is presented. The modulator architecture has been optimized to reduce the hardware complexity and maximize the carrier frequency in order to meet the requirements of deep space and satellite applications. Finally, the performance has been evaluated by implementing the modulator on a Xilinx XC2V3000 FPGA.
I. INTRODUCTION In the last years, great innovations have been introduced in communication systems, including new protocols and services definition. These changes often require the upgrading and the modification of the hardware. For these reasons, the interest in reconfigurable hardware platform is increasing, in particular for satellite systems, where the hardware upgrading is unfeasible. In this paper, the implementation of a flexible and programmable, fully digital QPSK modulator is presented. It is a component of the reconfigurable digital platform proposed in [3]. The modulator is able to cope with multiple symbol rates and signal bandwidths, using a single output analog section (composed by filters and up-converters). This modulator is applicable in the field of broadband Multimedia Communication Payloads, in Telemetry Tracking and Command links and also in Deep Space communications [1, 2]. In fact, it is worth to note that these different application fields have common aspects to be addressed. On the other hand, when state-of-the-art performance is required, it might be needed to separate the design approach on the basis of the specific application. In particular, some optimizations can be made for the use in Digital Video Broadcasting (DVB) systems. Up to the present time, modulators have been manufactured using analog technology in most of their subsystems. This is the case of the SKYPLEX transmit section (manufactured by Alenia for Eutelsat HB5 satellite) or the Alenia EuroSkyWay TX section. Such a strategy has required design of ad-hoc analog sections and has prevented reuse of the designed sections in other programs. Moreover, thanks to the progress of the space IC technology in terms of speed, integration level and flexibility, fully digital
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modulators appear more and more appealing. Among the advantages of this class of architectures there is the generation of the signal on a single analog line, removing any problem of unbalancing. Moreover, an inverse sin(x) / x filter can be introduced to pre-compensate for the DAC distortion. II.
MODULATOR ARCHITECTURE
A general architecture of a digital modulator was presented in [4] and it is shown in Figure 1. SRRC Interpolator Filter S/P
DAC SRRC Interpolator Filter
DDS Figure 1 General Digital Modulator Architecture
The input sequence, coming from the information source, is split into two streams and sent to the Square Root Raised Cosine (SRRC) filters. They acts as configurable interpolator, too. An effective way to implement these filters is by using a polyphase interpolator [6, 9, 10], where the input signal is fed directly into the branch filters H0(z)…HL1(z), and output samples are taken at the output of Hi(z) filters, at L times the input rate, as shown in Figure 2. A Direct Digital Synthesizer (DDS) is used to generate two in-quadrature carriers at a frequency configurable by the user [7]. The general architecture of a DDS is illustrated in Figure 3. The input tuning word sets the phase step and, therefore, the period of the sine wave, which is given by:
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FOUT =
TW ⋅ FCLK 2N
ISCAS 2006
III.
MODULATOR IMPLEMENTATION FOR DVB-S APPLICATIONS
Three different input data rates 55, 82.5 and 110 Mbps are foreseen by the standard for DVB transmissions. The resulting symbol rate is equal to 27.5, 41.25 and 55 Msymbols/s, respectively. If the same clock frequency is used for the three data rates, it is given by the least common multiple of symbol rates that is equal to 165 MHz. A very thin implementation has been developed, based on the selection of the system clock frequency equal to 165 MHz and assuming that FCLK=4FIF, resulting in a carrier frequency of 41.25 MHz. Under this condition, the samples of sine and cosine functions assume values in the set -1, 0, 1, allowing the elimination of multipliers and of the frequency synthesizer, resulting in a more hardware efficient implementation. The corresponding block diagram is shown in Figure 4. The reduction of flexibility resulting from a fixed carrier frequency in the digital modulator is negligible for this class of applications, for two main reasons: 1) several up-sampling blocks are present in the transmission chain before the RF transmitter is reached; 2) the frequency plan must be compliant with the DVB standard.
Figure 2 Polyphase Interpolator Filter
Figure 3 General DDS Architecture
1 0 -1 0
The phase-amplitude converter can be implemented in many different ways, according to the design constraints. If high spectral purity and high clock frequency are required a LUT based approach is preferred, but this approach may be very expensive in terms of memory requirements and a CORDIC or linear interpolation phase-amplitude converter can be used, instead [5]. Finally, the combined signal obtained by the multipliers output signals is fed to the analog converter. The architecture in Figure 1 is very flexible, since both the input sampling rate and the output center frequency can be configured, but it requires the implementation of reconfigurable SRRC interpolator filters and a DDS. Even if their implementation has been carefully refined, these blocks can be very expensive in terms of silicon area and power consumption, in particular if the actual application does not require a so high level of flexibility as that offered by the shown architecture. Accordingly with the requirements of the actual application, important simplifications can be adopted in order to reduce the hardware complexity. In the following section, the optimized implementation of the proposed modulator when used for DVB-S applications is discussed.
SRRC Interpolator Filter S/P
DAC SRRC Interpolator Filter 0 1 0 -1
Figure 4 Fixed Carrier Frequency Modulator Architecture
At each clock cycle either the sine function or the cosine function assumes the value zero. This fact suggests a second hardware simplification, consisting in the use of a single SRRC interpolation filter as illustrated in Figure 5.
1 1 -1 -1 SRRC Interpolator Filter
DAC
Figure 5 Simplified Fixed Carrier Modulator Architecture
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Accordingly with this solution, a programmable interpolation block, with factor of 6, 4 and 3 respectively, has been designed. We started from the design of three different low-pass SRRC shaped prototype filters, with 39, 25 and 19 taps, respectively, in order to obtain branch filters composed by 7 taps for all the three interpolation factors; in fact:
3.
39 25 19 6 = 4 = 3 = 7 At every clock cycle, only one branch filter produces an output, given by the combination of its coefficients. Considering that, the input signal can assume values in the set –1, 1, we have 27 different outputs for each filter and a total of 13x27 possible outputs for the entire configurable interpolator block. Moreover, since the output of the interpolator is multiplied for –1 or 1, we have a total of 2x13x27=3328 possible outputs for the modulator overall. In order to achieve the maximum clock frequency, the modulator outputs have been pre-computed for every possible configuration of input signals and parameter settings, and the values have been stored in a Read Only Memory (12 bits have been used for amplitude representation). The resulting architecture is illustrated in Figure. 6. Shift Register
ENABLE
CLK
EN
3
TABLE I.
INTERPOLATION ENABLE CTRL
10
POLYPHASE CTRL
12 11 10 8 7
4096 X 4
PLACE & ROUTE REPORT
Resource IOB RAM Blocks SLICEs BUFG
Usage 17 of 720 3 of 96 24 of 14336 1 of 16
Max. Freq.
214.6 MHz
y(n)
% 2% 3% 1% 6%
From the analysis of Tab. 1, it can be noted that a very limited amount of resources have been used for the modulator implementation and that the clock frequency of 165 MHz is easily supported. The modulator has been tested by using a Xilinx Virtex II Proto Board. The test bed setup is shown in Figure 7.
6
2 1
1
EXPERIMENTAL RESULTS
The architecture shown in Figure. 6 has been implemented into a Xilinx Virtex II XC2V3000 FPGA using a VHDL description. The results obtained by the place and route report are shown in the following table:
CLK
CLK
11
IV.
CLK
12
4.
more recent input bits, used to generate the 7 least significant bits of the memory address bus. Note that only the odd register outputs are considered at each clock cycle, since we have to separate the I and the Q components. Polyphase Control: it has in charge the selection of the memory area corresponding to the chosen interpolation factor, in order to generate the correct branch filter outputs. For each input sample it produces a number of outputs equal to the interpolation factor. Interpolation Control: it is the top level control unit, hosting the state machine which provides enable and control signals. Moreover, it generates the most significant bits of the memory address bus taking into account the selected interpolation factor and the signal dataflow. In particular, it is responsible to select the memory area where data corresponding to –1 and +1 multiplication are stored.
0
Polyphase SRRC (L=3, L=4, L=6) x(n)
Figure. 6: Optimized Modulator Architecture
In Figure. 6, four main blocks can be identified: 1. ROM: it is used to store the output samples of the modulator for all the possible modulator configuration and input combinations. Since we need 3328 memory location of 12 bits, the ROM has been organized in 3 blocks of 4096x4 bits, taking in mind the Xilinx XC2V3000 FPGA Select RAM blocks [8]. 2. Input shift register: it is used as a serial to parallel converter. At each clock cycle it contains the 7
AGILENT PATTERN GENERATOR
XILINX FPGA BOARD
AGILENT LOGIC STATE ANALYZER
MATLAB
Figure 7: Hardware Testbed Architecture
Input bits, randomly generated by a Matlab program, have been stored into an Agilent Pattern Generator
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(16720A) [11] that has been connected to the modulator input. Output data have been collected by using an Agilent Logic State Analyzer (16717A) and analyzed by a Matlab program. In the following figures some results are presented, showing the comparison between hardware implementation and Matlab simulation.
From the analysis of the above figure, it can be noted a perfect matching between the experimental results and the fixed point Matlab model. V.
CONCLUSIONS
In this paper, the design and the implementation of an optimized programmable, fully digital QPSK modulator has been presented. It is a component of the reconfigurable digital platform proposed in [3]. Starrting from a general fully digital modulator architecture, a very optimized implementation of the modulator, suitable for using in DVB-S systems, has been shown. The FPGA Place & Route report and measurements results have been given, highlighting the perfect matching with the assigned specifications. REFERENCES [1]
Consultative Committee for Space Data Systems, “Radio Frequency and Modulation Systems”, CCSDS 401.0.B. [2] European Co-operation for Space Standardisation, “Space Engineering: Radio Frequency and Modulation”, ECSSS E50-05 Draft 7. [3] G. C. Cardarilli, A. Del Re, M. Re “IP Based Reconfigurable Digital Platform for Satellite Communications” – Proc. of IEEE International Symposium on Circuits and Systems, pp. 37-40 vol. 2, Bangkok May 25-28, 2003. [4] G.C. Cardarilli, A. Del Re, D. Giancristofaro, M. Re and L. Simone, “Digital Modulator Architectures for Satellite and Space Applications”, Proc. of 1st International Conference on Circuits and Systems for Communications, pp. 166-169, St. Petersburg, Russia, 26-28 June 2002. [5] G. Boscagli, L. Simone, C. M. Comparini, D. Gelfusa, M. Re, A. Del Re, G. C. Cardarilli, "Direct Digital Frequency Synthesis Techniques in the View of Implementation on FPGA" – 2nd ESA Workshop on Tracking Telemetry And Command Systems for Space Applications TTC 2001, October 29-31, 2001, ESTEC Noordwijk – The Netherlands. [6] P. P. Vaidyanathan, “Multirate Systems and Filter Banks”, Englewood Cliffs, NJ Prentice-Hall, 1993. [7] Analog Devices: A Technical Tutorial on Digital Signal Synthesis, 1999. [8] http://www.xilinx.com [9] R. E. Crochiere, L. R. Rabiner, “Multirate Digital Signal Processing”, Englewood Cliffs, NJ Prentice-Hall, 1983. [10] P. P. Vaidyanathan, “Multirate Digital Filters, Filter Banks, Polyphase Networks and Application: A Tutorial”, Proc. IEEE, vol. 78, pp. 56-93, Jan. 1990. [11] http://www.agilent.com
Figure 8 Comparison Between Hardware Measurements and Matlab Results for all the Modulator Configurations (55 - 41.25 - 27.5 Msamples/s)
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