Organic vertical-channel transistors structured using ...

Organic vertical-channel transistors structured using excimer laser R. Parashkov, E. Becker, G. Ginev, T. Riedl, M. Brandes et al. Citation: Appl. Phys. Lett. 85, 5751 (2004); doi: 10.1063/1.1833551 View online: http://dx.doi.org/10.1063/1.1833551 View Table of Contents: http://apl.aip.org/resource/1/APPLAB/v85/i23 Published by the AIP Publishing LLC.

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APPLIED PHYSICS LETTERS

VOLUME 85, NUMBER 23

6 DECEMBER 2004

Organic vertical-channel transistors structured using excimer laser R. Parashkov,a) E. Becker, G. Ginev, T. Riedl, M. Brandes, H.-H. Johannes, and W. Kowalsky Institut für Hochfrequenztechnik, Technische Universität Braunschweig, 38092 Braunschweig, Germany.

(Received 28 June 2004; accepted 27 October 2004) Low-cost, large-area patterning of organic field-effect transistors with high-resolution is a subject of ongoing investigations. Here, we present a concept of patterning vertical-channels organic transistors using excimer laser. The channel length is controlled by the thickness of the dielectric polymer layer between the drain and source electrodes. We demonstrate that, by using this method, patterning of transistors with either metal or polymer contacts with resolutions as high as 2 ␮m is possible. Experimental data of vertical-channel pentacene transistors with either gold or poly (3,4-ethylenedioxythiophene) as drain-source contacts are reported. Field effect mobilities of 1 ⫻ 10−3 and 3 ⫻ 10−4 cm2 / V s, respectively, have been measured in these devices. © 2004 American Institute of Physics. [DOI: 10.1063/1.1833551] The fabrication process of the vertical-channel transistors starts with the preparation of drain electrodes. A photoresist (AZ 5214) is first spun onto a glass substrate, exposed through a dark-field chrome mask, and after development a negative image of the drain electrode pattern is produced. Films of poly (ethylene dioxythiophene)/poly (styrene sulfonate) (PEDOT/PSS) Baytron P dispersion or gold are then deposited on the top of the substrates by spincoating or e-beam evaporation, respectively. By submersing the substrates in acetone, the photoresist dissolves, leaving the desired 3 ⫻ 3 mm patterns of PEDOT/PSS with an average thickness of 150 nm and patterns of gold with average thickness of 100 nm. The resolution of the patterns (3 mm) is also easily achievable by any kind of printing technique. For improvement of the gold adhesion onto the glass substrate 5 nm of chromium were previously evaporated. The insulating layer between drain and source electrodes was spincoated from a solution of polyvinylphenol (PVP) in propylene glycol monomethyl ether. As crosslinking agent we used melamine. After the deposition the insulating layer was cured at 200 °C for 10 min. The surface roughness of the separating layer determined by profilometry was in the range of 1

Electronic devices based on the organic materials possess several advantages as low-cost processing, mechanical flexibility, and the possibility to coat large area. Even though the device performance of organic electronics is still too poor compared to that offered by silicone technology, several possible applications of organic electronic in the field of electronic papers,1 active matrix displays,2 integrated circuits,3 sensors,4 have already been presented. In the last years considerable efforts have been made in order to reduce the cost of manufacturing and dimensional resolution of the organic electronic. This is achievable, e.g., by using additive printing techniques. Printing over a wide range of cheap substrates like metals, laminates, plastic, glass, etc., is possible. Highresolution pattering processes for organic electronics using photolithography,5 microcontact printing,6 thermal imaging,7 micromolding in capillaries,8 are well known. Conventional printing methods like inkjet,9 screen,10 and offset,11 printing, are also useful for the patterning of organic electronic, but the achievable resolution is not satisfactory. In all cases highresolution patterning in the case of the planar devices, for now is highly depended on the lithographical processes (even in the case of microcontact printing the stamp is usually prepared by using high-resolution lithography step). The resolution of all patterning techniques and especially of the conventional printing techniques can be considerably improved by changing the device architecture from planar to vertical. In the case of vertical-channel transistor structure channel length is defined by the thickness of insulator layer between drain and source electrodes. Only two methods for fabrication of vertical-channel organic field-effect transistors have been demonstrated. The definition of the vertical sidewalls has been achieved by microcutting,12 or low-resolution lithography.13 Resolutions in the submicron range without using any high-resolution patterning step can be obtained. Here we demonstrate the concept for fabrication of organic vertical-channel transistors on glass substrate by using excimer laser ablation for the patterning. The presented concept provides a low-cost patterning technique, applicable on large-areas, and suitable for organic and inorganic materials.

FIG. 1. Schematic of the vertical-channel fabrication process: (a) Drain electrode deposition; (b) insulating layer spincoating; (c) source electrode deposition; (d) formation of the vertical channel by excimer laser ablation through Cu mask; (e) schematic of the vertical channel; W-channel width, L-channel length.

a)

Author to whom correspondence should be addressed; electronic mail: [email protected]

0003-6951/2004/85(23)/5751/3/$22.00

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© 2004 American Institute of Physics

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FIG. 2. AFM images of the fabricated vertical channels: (a) vertical channel with PEDOT/PSS drain and source electrodes; (b) vertical channel with gold drain and source electrodes.

nm. This curing step does not affect the conducting properties of PEDOT. The measured resistance of the patterns before and after the heat treatment was the same. Source electrodes were patterned by casting stripes of the conducting polymer PEDOT/PSS, or alternatively by evaporating gold through a shadow mask. The channel is controlled by the width of the source electrodes. Source electrodes with a width in the range of 0.2–1 mm were fabricated. For definition of the vertical-channels a KrF excimer laser 共␭ = 248 mm兲 was used. The channels were defined by exposition of the substrate to the laser beam (20 kHz/140 mJ) through a copper shadow mask. The open area of the shadow mask was aligned with the region of best homogeneity of the laser emission profile. The schematic of the vertical-channel preparation process is presented in Fig. 1. The channels lengths and morphology were determined by atomic force microscopy (AFM). Excellent channel edges were achieved by the above described technique. The channel length of the produced transistors was estimated to be 2.3 ␮m. The vertical-channel length in the demonstrated devices was limited by the dielectric layer thickness. We were forced to use relatively thick films of PVP 共1.3 ␮m兲 because of the high average roughness of the evaporated gold films. The root mean square deviation in the roughness of the e-beam deposited gold films was found to be in the range of 130 nm. Only five shots with the excimer laser at above described conditions were sufficient for the fabrication of the devices either with conducting polymer or gold contacts. The AFM images of thus formed channels for all-organic vertical-channel tran-

Parashkov et al.

sistors, and for transistors with gold contacts are presented in Fig. 2. No considerable difference is observed for both types of channels. According to some of our preliminary experiments channels with excellent morphology and characteristics can be structured in polyvinyl alcohol (PVOH), polyimide, and SiO2 as dielectric material. The limitation in the channel length is either due to the minimum thickness of the dielectric layer free of pinholes or to the roughness of the contact electrode layers. After formation of the drain and source contacts a thermally evaporated pentacene layer at a deposition rate near 2 nm/min, with a thickness of 20 nm was used as a semiconductor in our devices. Pentacene was purchased from Aldrich and used as received. As gate dielectric layer PVOH was used. The dielectric layer was prepared by spin coating a solution of polyvinyl alcohol in water, and photosensitized with ammonium dichromate. The dielectric was subsequently cured by exposure to the light of a 350 W UV-lamp 共12 mW/ cm2兲 for 32 s.14 A gate dielectric thickness of 600 nm on a flat surface and a surface roughness of 0.6 nm were determined by profilometry. Swelling and destruction of underlying layers can be prevented by the proper choice of the solvents and process parameters. Access to the drain and source electrodes was created mechanically. As a final production step in our transistor fabrication process, the gate electrode was applied. Casting PEDOT/PSS Baytron P dispersion along the vertical channel formed the gate. The thickness of the gate contact in the range of 200 nm was determined by profilometry. Figures 3(a) and 3(b) present electrical characteristics of our all-organic vertical-channel TFT with channel length of 2.3 ␮m and channel width of 1 mm. The transistor field effect mobility was estimated to be in the range of 3.42 ⫻ 10−4 cm2 / Vs assuming a dielectric constant 共␧ = 3兲 of the polyvinyl alcohol layer.15 Electrical characteristics of device with channel length and width of 2.3 and 200 ␮m, respectively, but built with gold source and drain electrodes are presented in Figs. 3(c) and 3(d). The transistor field effect mobility of this device was determined to be in the range of 1 ⫻ 10−3 cm2 / Vs. The estimations of the carrier mobilities were made for the saturation regime according previously described method.16 Threshold voltages of 13.2 and 22 V were obtained for the all-organic and the device with metal

FIG. 3. Electrical characteristics of the organic verticalchannel transistors: (a)–(b) all-organic transistor; (c)– (d) transistor with metal drain and source electrodes.

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Appl. Phys. Lett., Vol. 85, No. 23, 6 December 2004

drain-source electrodes, respectively. The on–off current ratios for both types of devices were in the range of 4. As seen from Fig. 3 the electrical characteristics of our nonoptimized devices shows that this technology for the fabrication of an organic vertical-channel transistors is suitable for structuring devices with organic and inorganic contacts. The gate leakage currents observable in the case of all-organic devices could be due to the diffusion of the PEDOT water dispersion in the dielectric layers, which after optimization and proper choice of the dielectric materials can be avoided. In summary we have demonstrated a functional organic vertical-channel transistors with both organic and metal source and drain contacts. The resolution of the obtained channels is in micrometer range, and they are fabricated by a simple and potentially inexpensive technology. Performance of the devices is not yet satisfactory and has now to be optimized. The future work will be concentrated also on downscaling of the channel length. Improvement of carrier mobility and threshold voltage can be achieved after optimization of the semiconductor deposition process.17 Optimization of the excimer laser ablation process by using beam homogenizer which is common in the material machining is also considered. The authors gratefully acknowledge financial support by the Bundesministerium für Bildung and Forschung (BMBF) and Deutsche Forschung Gesellschaft (DFG). 1

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