Time ↔ space tradeoff. ⬋ Fast circuits usually require more logic. 3. CSE370,
Lecture 13. Binary half adder. ◇ 1-bit half adder. ▫ Computes sum, carry-out.
Overview
Arithmetic circuits
! Last lecture " PLDs " ROMs " Tristates " Design examples
! General-purpose building blocks " Critical components in processor datapaths # Adders # Multipliers (integer, floating-point) # ALUs
Perform most computer instructions Time ↔ space tradeoff
"
! Today " Adders
"
# Fast circuits usually require more logic
# Ripple-carry # Carry-lookahead # Carry-select
The conclusion of combinational logic!!!
"
CSE370, Lecture 13
1
Binary half adder A 0 0 1 1
# No carry-in
Sum = A'B + AB' = A xor B Cout = AB
"
2
Binary full adder
! 1-bit half adder " Computes sum, carry-out "
CSE370, Lecture 13
B 0 1 0 1
S 0 1 1 0
! 1-bit full adder " Computes sum, carry-out
Cout 0 0 0 1
A 0 0 0 0 1 1 1 1
# Carry-in allows cascaded adders
Sum = Cin xor A xor B Cout = ACin + BCin + AB
" "
XOR
A B
XOR
A B
Sum 34
A B
AND2
A B
XOR
32
Sum
Cin
Sum Cout
Half Adder
33
B Cin A Cin
35
11 AND2
OR3
12
14
A B Cin
Cout AND2
A B
3
Full adder: Alternative implementation ! Multilevel logic " Slower " Less gates # 2 XORs, 2 ANDs, 1 OR
Sum = (A ⊕ B) ⊕ Cin Cout = ACin + BCin + AB = (A ⊕ B)Cin + AB
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
Cin 0 1 0 1 0 1 0 1
S 0 1 1 0 1 0 0 1
Cout 0 0 0 1 0 1 1 1
A
Sum
B
Cout
Cin CSE370, Lecture 13
A xor B AB
Half Adder Sum Cout
A xor B xor Cin
S 0 1 1 0 1 0 0 1
Cout 0 0 0 1 0 1 1 1
Sum Cout
Full Adder
13
CSE370, Lecture 13
4
2-bit ripple-carry adder Cout 0 0 0 1 0 1 1 1
A
B A1 B1
A2 B2
Cin Cout
Cin Cout
Sum1
Sum2
1-Bit Adder XOR
A B
XOR
32
Sum
Cin
0
33
AND2
Cin
B Cin A Cin
Half Adder
Cin 0 1 0 1 0 1 0 1
AND2
Cout
CSE370, Lecture 13
B 0 0 1 1 0 0 1 1
Cout
11 AND2
OR3
12
14
Cout AND2
A B
Sum
13
(A xor B)Cin
Overflow
Cout
Sum 5
CSE370, Lecture 13
6
4-bit ripple-carry adder/subtractor
Problem: Ripple-carry delay
! Circuit adds or subtracts " 2s complement: A – B = A + (–B) = A + B' + 1
! Carry propagation limits adder speed Cin XOR
A2 B2B2'
A3 B3B3' 0 1
Sel
A1 B1B1'
0 1 Sel
@0 A @0 B
A0 B0B0'
0 1 Sel
32
@2N Cin
0 1 Sel
XOR
Sum @2N+1
33
B
A
B
B
A
B
A
Cout Cin
Cout Cin
Cout Cin
Cout Cin
Sum
Sum
Sum
Sum
S3
S2
0 $ Add 1 $ Subtract
@0 B @2N Cin @0 A @2N Cin
S1 @3 C2 @4
A1 B1
AND2
A
S0 @2 C1 @2
A0 B0
11 AND2
OR3
12
14
@2N+2 Cout
S2 @5 C3 @6
A2 B2
AND2
S1
@0 A @0 B
S0
Note: Can replace 2:1 muxes with XOR gates
Overflow CSE370, Lecture 13
7
13
CSE370, Lecture 13
A3 B3
Cout takes two gate delays Cin arrives late
8
Ripple-carry adder timing diagram
One solution: Carry lookahead logic
! Critical delay " Carry propagation " 1111 + 0001 = 10000 is worst case
! Compute all the carries in parallel " Derive carries from the data inputs
S0, C1 Valid
S1, C2 Valid
# Not from intermediate carries # Use two-level logic S2, C3 Valid
S3, C4 Valid
"
Compute all sums in parallel
! Cascade simple adders to make
large adders
T0
T2
T4
T6
T8
CSE370, Lecture 13
9
Full adder again Half Adder A
Sum
B
Cout
Half Adder
A xor B
Sum
AB
Cout
A xor B xor Cin
Ai Bi
S0 @2
A1 B1
S1 @4
C2 @3 A2 B2
S2 @4
! Speed improvement " 16-bit ripple-carry: ~32 gate delays " 16-bit carry-lookahead: ~8 gate delays
C3 @3 S3 @4
! Issues " Complex combinational logic
A3 B3 C4 @3
C4 @3
CSE370, Lecture 13
10
! Carry propagate: Pi = Ai xor Bi " Propagate carry-in to carry-out when (A xor B) = 1 ! Sum and Cout in terms of generate/propagate:
XOR
Pi
Si
36
38
AND2
AND2
"
Gi 37
A0 B0 C1 @3
! Carry generate: Gi = AiBi " Generate carry when A = B = 1
Sum
Cin(A xor B) Cout
XOR
Cin
Carry-lookahead logic
Cin
Ai Bi
S3 @7 Cout @8
"
39 OR2
Ci
Ci+1
Si = Ai xor Bi xor Ci = Pi xor Ci Ci+1= AiBi + Ci(Ai xor Bi) = G i + C i Pi
40
CSE370, Lecture 13
11
CSE370, Lecture 13
12
Carry-lookahead logic (cont’d) ! Re-express the carry logic C1 = G0 + P0C0 C2 = G1 + P1C1 = G1 + P1G0 + C3 = G2 + P2C2 = G2 + P2G1 + C4 = G3 + P3C3 = G3 + P3G2 +
Implementing the carry-lookahead logic
in terms of G and P P1P0C0 P2P1G0 + P2P1P0C0 P3P2G1 + P3P2P1G0 + P3P2P1P0C0
Pi @ 1 gate delay
Ci
Si @ 2 gate delays
Logic complexity increases with adder size
Gi @ 1 gate delay
! Implement each carry equation with two-level logic " Derive intermediate results directly from inputs
C0 P0 G0
# Rather than from carries "
Ai Bi
C0 P0 P1 G0 P1
Allows "sum" computations to proceed in parallel
C0 P0 P1 P2 G0 P1 P2
C1
C3
G1 P2
C2
G2
G1
C0 P0 P1 P2 P3 G0 P1 P2 P3 G1 P2 P3 G2 P3
C4
G3 CSE370, Lecture 13
CSE370, Lecture 13
13
14
Cascaded carry-lookahead adder
Another solution: Carry-select adder
! 4 four-bit adders with internal carry lookahead " Second level lookahead extends adder to 16 bits
! Redundant hardware speeds carry calculation " Compute two high-order sums while waiting for carry-in (C4) " Select correct high-order sum after receiving C4
4
4
4
4
4
4
4
4
C8 A[15-12]
B[15-12]
4-bit Adder P
A[11-8] C12
B[11-8]
4-bit Adder
G
P
P
4
4
4
S[15-12] @8
S[11-8] @8
S[7-4] @7
@2
@3
@2
P3
G3
C4
C3
B[7-4]
@3
A[3-0] C4
4-bit Adder
G
@5
C16 @4
A[7-4] C8
G
P
G2
C2
C0 @0
@2
S[3-0] @4
@3
0
4-bit adder [7:4]
1
1 0 1 0 1 0
C4
adder low
C8 @2
@3
P0
G0
adder high
@4 P1
G1
C1
C0 @0
C0
Lookahead Carry Unit P3-0 @3
1 0 1 0 five 2:1 muxes
C0
4-Bit Adder [3:0]
G3-0 @5
CSE370, Lecture 13
C8 15
We've finished combinational logic... ! What you should know " Twos complement arithmetic " Truth tables " Basic logic gates " Schematic diagrams " Timing diagrams " Minterm and maxterm expansions (canonical, minimized) " de Morgan's theorem " AND/OR to NAND/NOR logic conversion " K-maps, logic minimization, don't cares " Multiplexers/demultiplexers " PLAs/PALs " ROMs " Adders CSE370, Lecture 13
4-bit adder [7:4]
G
4
@5 P2
B[3-0]
4-bit Adder
17
CSE370, Lecture 13
S7
S6
S5
S4
S3
S2
S1
S0 16
