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ABSTRACT
_________________________________________ Today’s consumers demand wireless systems that are low-cost, power efficient, reliable and have a high integration form. High levels of integration are desired to reduce cost and achieve compact form. Hence the long term vision of goal for wireless transceiver is to merge as many components as possible to a single die in an inexpensive technology. Therefore, there is a growing interest in utilizing CMOS technologies for RF power amplifiers (PAs). Although several advances have been made recently to enable full integration of PAs into CMOS technology, it is still among the most difficult challenges in achieving a truly single-chip CMOS radio system. The total integration of RF building blocks can lower the cost and chip area, which makes the Si-based design a better choose than the multiple-dies, III-V based design. Additionally, advancements in CMOS technology for integrated power amplifier in the gigahertz range have been reported. It has shown that, with improved techniques, CMOS can become a prospected candidate for RF PA design. Efficiency enhancement of RF power amplifiers is crucial for modern wireless communication systems. Many techniques have been developed for efficiency enhancement in power amplifier design. Furthermore, linearity improvement technique using the cancellation of nonlinear terms is proposed for the CMOS power amplifier in combination with the efficiency enhancement technique. Also, power amplifier must be designed to be able to control the dc consumption to improve the overall efficiency. 3
The switching of drain quiescent current level is widely used in commercial power amplifier in order to reduce dc power consumption while keeping the linearity level within the system requirement. This can increase the average power added efficiency (PAE) of the power amplifier and prolong the battery usage time for a mobile handset with trade-offs in performances such as gain and linearity. The improvement in PAE can be achieved at the cost of increased complexity in the matching network design. Furthermore, a linearization method using the cancellation of third-order intermodulation terms of parallel FETs is combined to enhance the linearity of CMOS power amplifier. These approaches will demonstrate a better solution for advanced linear and high efficiency RF power amplifier. This dissertation focuses on the development of new efficiency enhancement schemes for Class E CMOS RF power amplifier design. The design procedure is presented in chapter 5. Also, In chapter 5, three CMOS PA cascode topologies are designed using device stacking, self-biasing technique, Diode Voltage booster. These circuits are simulated using cadence tools in chapter 6. In cascode topology the supply voltage is limited by the breakdown voltage of the common-gate transistor. So the self-bias technique is used at the common-gate to allow RF swing at the gate to boost the biasing voltage above 2Vdd. Consequently, one can have a larger signal swing at the output before encountering the breakdown. Simulations of Proposed Class-E RF Power Amplifier Using 130nm CMOS Technology are performed using cadence tools and the results are comparable with the state-of-the-art. The first proposed Class-E amplifier is the cascode configuration using self-bias to safe the gate oxide from breakdown. Simulations results using 130nm CMOS technology demonstrate 25.8dBm from 5 V power supply at 2.4GHz with the PAE of 20.4%. The second proposed Class-E amplifier is the cascode configuration using diode voltage-booster to avoid breakdown of the gate oxide. Simulations results using 130nm CMOS technology demonstrate 26.75 dBm from 5 V power supply at 2.4GHz with the PAE of 24.4%. 4
A comparison is established among these configurations to verify the best one of them which has significant properties as higher power gain, higher output power, maximum efficiency, and maximum linearity ( higher IP3), in addition to higher reverse isolation. Class-E amplifiers can operate at RF frequencies efficiently by minimizing the output capacitance loss. However, the zero voltage switching condition for compensating the output capacitance loss cannot be maintained under non-periodic driving conditions, thus Class-E amplifier cannot achieve high efficiency when driven by the delta-sigma modulated signals. So In chapter 7, Voltage-mode Class-D switching amplifiers have the potential to maintain high efficiency when the driving signals are not periodic. However, loss associated with the driving circuits (with limited bandwidth), the active devices (including shoot-through current loss) and filters (poor power recycling) can degrade the performance significantly. A new design for Class D RF power Amplifier
using CMOS technology is proposed, simulated, and optimized using cadence tools. In chapter 8, Several practical layout considerations in power amplifier designs are presented. The design of high-quality passive elements in the silicon-based radiofrequency integrated circuits (RFICs) area has been one of the key issues in wireless communication systems. Performances of several basic RF blocks depend mainly on the quality of the passive elements. Overall, an on-chip spiral inductor can be a key component among passive elements. In general, the RF micro-inductors have been fabricated on the planar substrates such as silicon or glass.
Chapter 9 introduces the conclusion and future works. So, Finally the CMOS Class-E and Class-D power amplifier operated at 2.4 GHz range are designed and have shown higher output power than the previous power amplifier designs. The design methodology presented to optimize Class-E and Class-D power
5
amplifier for maximum efficiency are made available and helpful for future research. It has been demonstrated that it is possible to include not only all device parasitics but also circuit elements parasitics using equations to maximize the power added efficiency. The methodology has been used in cadence tool to optimize the CMOS power amplifiers. It has been shown to be sufficiently flexible to optimize different variations to generalize Class-E power amplifier. High Voltage in CMOS has been explored as a way to achieve a high output power level. It has been shown that the high breakdown voltage device can be used without any change in the design process flow. Thus, this dissertation shows the analysis, simulation and optimization of implementing the CMOS Class-E and Class-D PA which are good for the further development of compact, high-efficiency power amplifier integrated circuits. Therefore, this dissertation provides a good guidelines to design the Class-D PA development, which is a significant part to the success in the RF CMOS transceivers circuit design.
Key Words___Mobile Communications, Radio Frequency, CMOS, Power Amplifier, Switching-mode, Class-E, Class-D, Linearization, Intermodulation, High efficiency techniques, power losses, Oxide Breakdown, self-bias, voltage-booster, voltage-mode, Cadence tools, spiral inductors.
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