effect on on-time delivery compared to First-In-First-Out (FIFO) dispatching. .... provide a mechanism to speed up lots before they are very close to their due dates ...
Comparison of Due-date Oriented Dispatch Rules in Semiconductor Manufacturing Oliver Rose Department of Distributed Systems Institute of Computer Science University of Würzburg 97074 Würzburg, Germany Abstract In this study we compare the cycle-time and on-time-delivery performance of the Critical Ratio (CR), the Earliest Due Date (EDD), and the Operation Due Date (ODD) dispatching rules in semiconductor wafer manufacturing. In addition, we comment on the robustness of the rules to low target flow factor values. It turns out that EDD has almost no positive effect on on-time delivery compared to First-In-First-Out (FIFO) dispatching. CR and ODD, however, reduce the tardiness of lots considerably. ODD dispatching is more robust than CR if the target cycle times for the factory are chosen smaller than the corresponding average cycle times of a factory under FIFO dispatching regime.
Keywords Semiconductor manufacturing, simulation, dispatch rules
1. Introduction In semiconductor industry, a variety of production control techniques are applied in order to increase throughput, to decrease cycle times, and to achieve on-time delivery of the products [2, 6]. Some manufacturers use scheduling approaches but still the majority of the fabs are run under the regime of dispatch rules. With respect to controlling on-time delivery, there are two classes of rules: rules that consider due dates of products, e.g., Critical Ratio (CR) or Earliest Due Date (EDD) and rules that do not consider due dates, e.g., First In First Out (FIFO) or Shortest Processing Time First (SPTF) [4]. For an overview of dispatch rules typically applied in semiconductor industry see [1]. In a recent paper [5] we showed that the setting of the target due dates for CR is not trivial. If the target due date is set appropriately an on-time delivery percentage of 100% can be achieved while the average cycle times are approximately the same as in the FIFO case. However, if the due date is set too tight the resulting on-time delivery percentage decreases and the cycle times become considerably larger than in the case of FIFO dispatching. In this paper, we present the Operation Due Date (ODD) dispatching approach, which shows essentially the same good performance for the setting where CR performs good but does not lead to sudden performance degradation for less appropriate due date targets.
2. Simulation experiments 2.1 The Operation Due Date dispatch rule This rule is not mentioned in the classic dispatching rule overviews like [1]. We heard about ODD the first time from simulation and planning practitioners from Infineon Technologies AG, a German semiconductor manufacturer. In general, the due date for a lot of a specific product is given in terms of a flow factor (FF) that is defined as the target cycle time divided by the raw processing time (RPT). For instance, a FF of 2 says that a lot spends half of its cycle time in processing state and the other half in non-processing states like waiting. Thus, the due date of a lot is the time when it enters the fab plus FF * RPT. For ODD, we also need the raw processing time RPT(i) for a
sequence of processing steps or operations from operation 1 to operation i (including operation i). The ODD of operation i is defined as the Release Time + RPT(i) * FF. For the final operation of a lot the ODD is equal to the classical due date as used in EDD or CR. In the following, we compare the behavior of the following due-date oriented dispatch rules. • Earliest Due Date (EDD): the lot with the closest due-date is ranked first. • Critical Ratio (CR): the lot with the most critical ratio of slack time and remaining processing time is ranked first. • Operation Due Date (ODD): the lot with the closest operation due date is ranked first. For CR we use the following criticality measure (1 + Due - Now) / (1 + TRPT), if Due > Now, and 1 / ((1 + Now - Due) * (1 + TRPT)), otherwise, where Due is the due date of the lot, Now the current time, and TRPT denotes the total remaining processing time. The most important decision when applying these dispatch rules is how to set the lot due dates appropriately. In a real fab situation the planning department usually provides the due date. In our case, however, we were interested whether there is a due date setting that minimizes the average cycle times of the lots while providing on-time delivery. In [5], we saw that tight due dates lead to considerable problems when CR dispatching is applied. Tight in this case means target average cycle times that are lower than the corresponding cycle times using FIFO dispatching. The CR fabs with tight due dates showed the following behavior. During warm-up more and more lots enter the fab and the average cycle time increases because of the increase of waiting times at the tools. In front of highly loaded machines the lots experience more waiting times. In addition, tools break down and the CR value of the lots shrinks again. Because of the fact that the due date for the lots is less than the average FIFO cycle time, a considerable number of lots tend to become late. The CR rule assigns higher priorities to these lots to speed them up. Then, fresh lots have to wait. Because of the large amount of lots with higher priority they are using up their slack time to the due date while still being in the first part of their route. The waiting times at the first steps grow up to a certain balance threshold. From that moment on the fab is stable but operating at a very high inventory and cycle time level. This issue arises because problems to keep the due date that arise at late operations are propagated backwards in the operations sequence over time. Because all lots are only focused on their final due date the CR dispatching does not provide a mechanism to speed up lots before they are very close to their due dates. The ODD rule does not have this problem by design. Because there are strict due dates for each operation the lots are already kept at the right pace to meet their due date from the early operations on. Slack times for young lots are shorter than in the CR case and thus they do not have to let old lots pass before they are processed. Therefore, it is not possible for ODD dispatching that problems at operations at the end of the processing sequence propagate back to the operations at the beginning. 2.2 Experimental environment To avoid the explosion of the parameter space for the simulation experiments we decided to use the same flow factors for all lots. Moreover, it is hard to decide from an academic viewpoint that FF values should be given to which products without knowing the requirements and constraints of a real planning department. As test models we used the MIMAC (Measurement and Improvement of MAnufacturing Capacities) test bed datasets 1, 3, 4, 5, 6, 7. Dataset 2 was not used because the simulation package reported problems in the dataset. Table 1 shows the basic properties of the model fabs. For further details on the datasets and their download see . The simulation runs were carried out with Factory Explorer 2.8 from WWK. The ODD rule is not provided by this simulation package but it can be customized to a certain extend with additional C++ coded routines. We implemented this dispatch rule as a user defined rule. The length of the simulation runs was 7 years of fab operation. The first two years were considered as warm-up phase and not taken into account for the statistics. We checked the
length of the initial transient both by the cycle time over lot exit time charts and the Schruben test. If there was an indication of initial bias problems the warm-up phase was increased appropriately. The measurement interval was 5 years in all cases. Table 1: MIMAC Datasets Fab
Tool Groups
Tools Products max. Steps
1
83
265
2
245
3
73
354
11
547
4
35
69
7
92
5
85
176
21
266
6
104
228
9
355
7
24
38
1
172
For all 6 test bed models we simulated the following dispatch regimes: FIFO (as reference), EDD, CR, and ODD with flow factors FF ranging from 1.0 to 4.0 in steps of 0.1.
3. Simulation results In our study, we consider the fab performance measures average cycle times, on-time delivery percentage, and average time tardy of tardy lots. We only show the summary results for all lots and no product-specific results because this does not provide additional insights in our case. EDD is always outperformed by CR and ODD, even by FIFO in almost all cases. Although this dispatch rule considers lot due dates, there is no effect upon changing the target FF. Cycle times stay constant, on-time delivery percentage and average time tardy are worse than FIFO. In addition, we discovered stability problems for EDD at nominal factory loads larger than 90%. It is not in the scope of this study to examine in detail the EDD behavior. We therefore postpone the analysis of EDD dispatching for semiconductor fabs to a new study. It is of particular interest to find out why there was no impact of the target flow factor on the average cycle times. In the remainder of this section we focus on the behavior of the CR and EDD rules. In all graphs the thin, dashed FIFO curves are provided as a reference. The fab models can be split into the following groups. For data set 4 and data set 7 it does not matter which dispatch rule is used. Both CR and EDD results almost match with the FIFO results. These two fabs, however, are not typical wafer fabs because they have a smaller tool set and the process sequences are much shorter. Data sets 1, 3, and 6 show a similar behavior. There ODD clearly outperforms CR for all considered performance measures and both rules outperform FIFO with respect to on-time delivery and tardiness. Factory 5 lies in between the two groups. The effects of the due-date oriented dispatch rules are smaller than for sets 1, 3, and 6 but visible. Therefore, the discussion of the results focuses on data sets 1, 3, and 6. Figures 1 and 2 show the results for data set 3 and Figures 3 and 4 the results for data set 6. The left graphs show the average cycle times and the right graphs the average time tardy for tardy lots. We provide curves for factory loads of 84 and 98%. Down to loads of, say, 70% the same effects are visible but to a smaller extend. We do not show the on-time delivery curves because they almost match for CR and EDD. The CR curves can be found in [5]. In all cases the CR and ODD cycle time curves change their slope for flow factors close to the average flow factor resulting from running the fab under FIFO regime at the same load. For example, the average flow factor for data set 3 at 98% load is about 1.8 and this is approximately where the cycle time curves have their minimum. Both for
fab 3 and 6, the ODD cycle times are lower for the flow factors in the neighborhood of the FIFO flow factor and above. Moreover, the ODD tolerates smaller target flow factors before it leads to an increase in cycle time and the change in behavior is much smoother than in the CR case.
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Figure 2: ODD for data set 3 With respect to the average time tardy for tardy lots, ODD outperforms CR, too. Again the ODD reaction on changing the target flow factor is smoother than the CR one. In [5], we discovered that CR dispatching causes an imbalanced line when the target flow factors are chosen too low. As mentioned above, WIP is increasing at the first critical tool group in the line. In the case of data set 6, this is furnace 11026_ASM_B2. Table 2 shows the top 10 contributors to the cycle time of product 38090964_B5C for a target flow factor of 2.3 and a fab load of 98%. Flow factor 2.3 is chosen because for this value the both CR and the ODD average cycle times are higher than the FIFO results. The center column of the table provides the CR results that indicate that about 58 % of the cycle time is spent at the furnace. In contrast, in the FIFO case (left column), this furnace is also the major contributor to the cycle time but only about one third of the CR percentage. When ODD (right column) is applied the situation considerably improves compared to CR. The line is more balanced again. The situation, however, is worse than with FIFO as indicated by a higher cycle time percentage of the top contributor.
4. Conclusion In our study we compared the performance of the three due-date oriented rules Earliest Due Date (EDD), Critical Ratio (CR), and Operation Due Date (ODD) in dispatching semiconductor wafer fabs. For our comparison we
considered average cycle times, on-time delivery percentages, and average tardy times of tardy lots. FIFO dispatching was used as a reference. 80
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Figure 4: ODD for data set 6 Table 2: Cycle time contribution by tool groups FIFO 11026_ASM_B2 12553_POSI_GP 20540_CAN_0.43_MII 15121_LTS_3 13024_AME_4+5+7+8 11024_ASM_A4_G3_G4 16221_IMP-MC_1+2 17421_HOTIN 15131_LZZZZ 15627_HIT_S6000
CR 18.8% 13.2% 9.6% 3.2% 3.1% 2.7% 2.7% 2.6% 2.5%
11026_ASM_B2 20540_CAN_0.43_MII 12553_POSI_GP 13024_AME_4+5+7+8 16221_IMP-MC_1+2 17421_HOTIN 15121_LTS_3 11024_ASM_A4_G3_G4 17221_K-SMU236
2.3% 11027_ASM_B3_B4_D4
ODD 57.5% 3.8% 3.3% 1.8% 1.7% 1.7% 1.5% 1.5% 1.4%
11026_ASM_B2 20540_CAN_0.43_MII 12553_POSI_GP 11024_ASM_A4_G3_G4 13024_AME_4+5+7+8 15121_LTS_3 17421_HOTIN 16221_IMP-MC_1+2 11027_ASM_B3_B4_D4
1.4% 15627_HIT_S6000
28.9% 7.6% 5.0% 3.4% 3.3% 2.8% 2.7% 2.6% 2.6% 2.2%
For all applied performance measures FIFO outperformed EDD. This was surprising to us and requires attention by a further study. CR tended to sudden performance degradations if the target flow factor was set too low. If we applied ODD the
robustness problems of CR were successfully avoided while providing better performance measures. ODD is a simple rule where each operation has its own due date that is defined as the release time plus the sum of processing times up to this operation times the target flow factor. Besides the target flow factor no additional parameters are required. Under ODD regime the factory reacted smoother on decreasing the flow factor than in the CR case. In particular, ODD keeps the line balanced and avoids the piling up of inventory in front the first critical tool group. Further research should be dedicated to other approaches to determine the operation due dates.
Acknowledgements The author would like to thank Stefan Menth for his valuable simulation efforts and fruitful discussions.
References 1. 2. 3. 4. 5. 6.
Atherton, L. and R. Atherton. 1995. Wafer Fabrication: Factory Performance and Analysis. Boston: Kluwer. Fowler, J. and J. Robinson. 1995. Measurement and improvement of manufacturing capacities (MIMAC): Final report. Technical Report 95062861A-TR, SEMATECH, Austin, TX. Kleinrock, L. 1975. Queueing Systems Volume I: Theory. Wiley, New York. Rose, O. 2001.The Shortest Processing Time First (SPTF) Dispatch Rule and Some Variants in Semiconductor Manufacturing. In Proceedings of the 2001 Winter Simulation Conference, pp. 1220-1224. Rose, O. 2002. Some Issues of the Critical Ratio Dispatch Rule in Semiconductor Manufacturing. In Proceedings of the 2002 Winter Simulation Conference, pp. 1401-1405. Wein, L.M. 1988. Scheduling semiconductor wafer fabrication. IEEE Transactions on Semiconductor Manufacturing, 1(3):115-130.
