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MASM2005

Transient Behavior During Single Product Start Peaks in a Semiconductor Fabrication Facility Oliver Rose Dresden University of Technology, Institute of Applied Computer Science, 01062 Dresden, Germany [email protected]

Abstract In this study, we examine how wafer start peaks affect the performance of a semiconductor wafer fabrication facility. In contrast to other publications, we use a real factory model. In addition, we created two new types of analysis particularly suited for transient phases. The t-test diagram and the disturbance index provide useful support in finding disturbances in the factory and measuring the amount of disturbance.

Introduction To succeed in the global market, capacity planning is essential. The production process in the semiconductor business is one of the most complicated to predict. This has several reasons that originate from the fact that the machines used to process wafers and the clean room technology used are very expensive. As a result, a fabrication facility, in short fab, is used to produce a wide range of products and most of the machines are reused for several steps of each product. Some machines are dedicated to a few products, but most of them are not. As a consequence, disturbances that affect one product can propagate to another product. The semiconductor production process includes several repetitions of steps, for example lithographic steps. Again, machines are reused for theses steps. The reuse of machines, the resulting loops, and the production of multiple products in one facility result in a behavior of semiconductor fabs that is very hard to estimate. For instance, it is not possible to determine exactly when a started wafer will be finished. In this paper, we analyze the effects of wafer start peaks or surges in a semiconductor fab. The analysis is accomplished using special simulation software and a model of the 200mm fab of Infineon Technologies at Dresden. Wafer start peaks are sudden increases in wafers starts for a single or multiple products. This is an option for the company to satisfy customer orders or to react on a special market situation. The effects on the semiconductor fab are temporary and a steady state analysis can not provide useful results. A similar problem has been analyzed in Rose (1998) or Dümmler and Rose (2000). Our work adds the following new aspects to the findings of these publications. The simulation model represents a real Infineon fab. This increases the complexity of the model compared to the models used in the papers above. It comprises more machines, more products and longer recipes. This results in increased simulation time and increased complexity of the analysis. But the results can be used directly by Infineon planners and can possibly be transferred to other semiconductor fabs. The analyzed wafer start peaks are peaks of a single product. Two representative products of the product mix were chosen to represent the two major product types, logic and memory chips.

The simulation model The model For this study, we used AutoSched AP 7.3 (ASAP) simulation package from Brooks Automation. Due to the enormous amount of output data we were not able to use the built-in analysis tools. We developed Perl scripts for this purpose. The simulation model was provided by Infineon Technologies. It is a model of the 200 mm semiconductor fab at Dresden, Germany. Since the fab has seen many changes in product mix and technology, it is a fab with a wide variety of machines and products. In the simulated fab, 16 different products are manufactured. Some are memory products, which are generally simpler, others are logic products that can be very complex to manufacture. The real names are changed to M1, ..., M8 for memory products and L1, ..., L8 for logic products. The MASM2005 - Paperformat

simulated fab has approximately 14000 wafer starts per week, about 3% are hot lots, and about 1.8% are rocket lots. Hot lots are lots that are to be produced about 20% faster than normal lots. Rocket lots are - as the name suggests the fastest type of lots. For these lots, stations are reserved in advance in order to produce them without delay. Table 1 shows the wafer start distribution without hot and rocket lots. The model consists of approximately 270 different station families. Most of Table 1: Wafer start distribution these station families are used on different routes for different products. Due to this, a change in one product affects several other products as well, Product Percentage of wafer starts depending on the product and type of dispatching rule chosen. Some of the M1 Below 1% tools are batch tools that can process several lots at the same time, e.g., ash M2 1% tools. They are provided with a rule when to start a process and when to wait M3 10% for other lots via a minimum and maximum batch size. Other tools are batch M4 1% interval tools that can start processing a new lot before the last lot is finished M5 16% (e.g., wet banks). Also included are station dedication, setup times, and M6 6% sampling. M7 9% Operators and stocker capacities are not modeled in this simulation. The M8 10% simulation only represents the front end, and no wafer test and no bonding L1 1% are simulated. L2 12% L3 2% Dispatching L4 1% During the simulation study, four dispatch rules were used. The dispatch L5 1% rules determine which lot in the queue for a station is processed next. Three L6 3% rules are built into the ASAP 7.3 software, one is company specific. The L7 9% rules are: L8 12% • FIFO - First In First Out •

Priority FIFO

•

SSU - Same Setup

•

OTD - Operation Time Due date

FIFO is the simplest of all rules. All lots are processed in their order of arrival. This rule was actually never used for the whole fab - only the normal lots used it. Hot and rocket lots were still on priority to increase their speed. Priority FIFO - lots are first sorted by priority, then by their order of arrival. The lot with the highest priority goes first. If the priority is the same among two lots, their order of arrival determines what is processed first. This was the main rule used. Even some of the lot types are modeled using the priority mechanism. For normal lots, the priority was set to 1 for M-products and 2 for L-products. Hot and rocket lots had higher priorities. SSU (Same Setup) is a dispatch rule for batch tools. It selects the first lot that uses the same setup the machine has at the moment. If no such lot is available, it selects the first lot that has a setup that no other machine in the station family has. Otherwise it selects the first on the list (sorted by order of arrival). OTD is an ODD (Operation Due Date) derivate (see Rose (2003)) used by Infineon. It dispatches using dates for each operation on the route of this lot. The exact rule is not published. Hot lots are simulated using priorities in the different FIFO scenarios and due dates in the OTD runs. Rocket lots were always on priority during the different runs. Additionally, rocket lots were modeled using a separate route with additional setup times to reduce the capacity of the fab to mimic the station reservation procedure in the real fab.

General behavior during peaks Design of experiments The first question to be analyzed is how surges in wafer starts affect the fab. To obtain a first impression of the fab behavior, a matrix with experiments was compiled (Table 2). The experiments in this matrix are realistic values for possible customer orders. Since the goal is to derive some general ideas of how the fab reacts during those peaks, a representative product - L8 - was chosen.

The dispatch rule for these experiments is priority FIFO, with priority 2 for logic (L) products, 1 for memory (M) products. Hot and rocket lots are modeled using priorities higher than 2.

Analysis

Table 2: Experiment matrix

200 extra WSPW 300 extra WSPW 500 extra WSPW 1000 extra WSPW

1 week 200 extra Wafers 300 extra Wafers 500 extra Wafers 1000 extra Wafers

2 weeks 400 extra Wafers 600 extra Wafers 1000 extra Wafers 2000 extra Wafers

3 weeks 600 extra Wafers 900 extra Wafers 1500 extra Wafers 3000 extra Wafers

4 weeks 800 extra Wafers 1200 extra Wafers 2000 extra Wafers 4000 extra wafers

The following figures show the WIP-levels and cycle times of product L8 in the fab during the peak. The peak starts at day 0. The dotted lines show the confidence interval of the mean value (3 runs), orange is WIP, blue is cycle time. The data is normalized to a run without a peak. This means WIP 1.2 is 20% above normal level. All 16 experiments show the same behavior. The WIP increases linearly during the period of increased wafer starts. After that, the WIP remains approximately at the same level until the first lots of the extra wafers start to appear in the fab output. Then, the WIP level decreases almost linearly with a small slope near the end. Tracking the extra lots shows that they are produced as fast as the rest of the lots on the same route. The increased cycle time close to the end of the period with increased WIP affects the production of the extra lots as well. This is no surprise since they are dispatched in the same way as the other lots on the same route and have no special priority.

Figure 1: A peak with 200 extra wafers} Figure 1 and Figure 2 show the two extreme cases of the experiment matrix. We included in these figures the actual cycle times of the peak lots. Both figures show clearly that the extra lots follow the normal product flow and that they are not dispatched differently. Otherwise the crosses for the peak lots would not follow the average cycle time curve. The short peak with only 200 wafers is not visible in the graph. In the scenario with 4000 extra wafers the peak is clearly visible and dominates the figure. The increase in WIP is followed by an increase in cycle time approximately one average cycle time of the product after the start of the peak. From these figures we estimated the time the fab is on a higher WIP level than it would have been without the extra wafers. The start of this period is the start of the wafer peak. The end is the moment the confidence intervals of the WIP during the peak and the WIP in a comparison run without peak overlap. Due to the natural fluctuation of the WIP, this point in time is hard to determine. It depends on the down times during the simulation time of the fab. Since the downtimes are given in a downtime calendar during all runs, the time until the fab returns to normal is a value specific to this downtime setting.

Figure 2: A peak with 4000 extra wafers}

As Table 3 shows, the main factor that determines the length of the disturbance is the amount of extra wafers 1 week 2 weeks 3 weeks 4 weeks started. The period to start them seems to be only a minor factor. For example the duration for 500 wafers for one 200 wafers 21 days 40 days 56 days 60 days week and 300 wafers for two weeks (equals 600 wafer) is 300 wafers 34 days 50 days 59 days 64 days almost equal, as well as the duration for 1000 extra 500 wafers 49 days 62 days 68 days 73 days 1000 wafers 65 days 75 days 91 days 101 days wafers distributed over one or two weeks (65d and 62d). To gain an overview of the disturbances on fab level the t-test was used to find differences in WIP levels. For each simulated day, the WIP for each product was determined. The WIP for each product and each day was then compared to the WIP of the same product on the same day during a simulation run without peak. The comparison uses the t-test to determine equality. If several of these t-tests fail consecutively this is a good indicator for a disturbance. Using this method the duration of disturbance on fab level was derived (Table 4). The disturbance of the fab is not the same as the Table 4: Duration of disturbance on fab level disturbance on product level. Table 4 shows this. As 1 week 2 weeks 3 weeks 4 weeks long as the wafer peak periods stay short and the increase in wafer starts stays below the capacity limit, 200 wafers 21 days 40 days 60 days 62 days the disturbance on fab level is equal to the disturbance 300 wafers 34 days 50 days 65 days 72 days 500 wafers 49 days 64 days 93 days 110 days on product level. For longer surges the disturbance 1000 wafers 72 days 112 days 121 days 128 days propagates itself to other products (mainly similar ones). This increases the recovery time for the fab. If an increased WIP level returns to normal, it stays there. Figure 3 shows the mean time to finish the extra lots. For hiding the actual cycle times, the mean time to finish is divided by the fastest mean time to finish in that table (200 wafers over one week). The time to finish the extra lots is the length of the period beginning with the start of the first extra wafer until the last one leaves the fab. The mean time to finish is the mean value of all 3 runs. As the diagram shows, spreading the same amount of wafers over a longer period of time increases the time to finish the product. It is even faster to produce 1000 wafers started over one week than to produce 600 wafers started over three weeks. Spreading the wafer starts over more weeks is a penalty that can not be caught up despite possibly less disturbance. Table 3: Duration of disturbance on product level

Figure 3: Mean time to finish

Comparison of different dispatch rules Design of experiments The main goal of this analysis is to determine the differences between the three different dispatch rules (FIFO, Priority-FIFO and OTD) concerning the behavior during wafer start peaks. As representative product, L8 was chosen and as scenarios, 2 experiments from the matrix in Table 2 were chosen. The experiments are: 500 extra WSPW over 4 weeks and 1000 extra WSPW over 2 weeks. The priorities for Priority-FIFO are set as described above. In one experiment, the priority is set to 1 for all products except the peak lots, which had priority 2. Hot and rocket lots still have their higher priorities.

Analysis Cycle time analysis Figure 4 shows the output of the extra wafers. The x-axis is the time from the first extra wafer started (divided by the mean cycle time of the FIFO run), the y-axis is the cycle time (again divided by the mean cycle time of the FIFO run). The approach of prioritizing only the peak lots is the fastest one (for the peak lots). The peak lots remain in a narrow band and most of the lots are produced faster than the fastest lot of the other dispatch rules. The next fastest seems to be Priority-FIFO, but that is not true. Although some of the lots are produced faster in FIFO/Priority-FIFO compared to OTD, the last lot of the extra lots is produced slower. Hence, the second best solution is OTD while having a small spread of the distribution of the peak lots. FIFO and Priority-FIFO produce almost the same results with FIFO being slightly slower. Figure 5 is a histogram of the cycle times of the extra lots using the different dispatch rules. It corroborates the conclusions derived before. The priority only for the peak lots dramatically speeds up the peak lots at the expense of the other lots on all routes. OTD reduces the spread of the cycle time distribution. This has some other interesting effects on the fab as we will see in the next section.

Figure 4: Output of extra wafers

Figure 5: Cycle time histogram of the extra wafers

Consequences for the fab Since there is no drastic speed up of one lot type without losses in the performance of other lot types, the question is how much the different dispatch rules affect the rest of the fab. Since disturbances in the WIP flow are good indicators for disturbances, we concentrated on finding them. The t-test is a good way to detect deviation from normal WIP levels. The WIP of each product (M1 - M8, L1 - L8) is measured for each day of the analysis period (approximately 1 year, starting 10 days before the wafer start peak). The values from the three runs are then compared with the values from three comparison runs without peak of the

appropriate day using a simple t-test (Falk et al. (2002)).We use a 95% confidence interval of the mean. That also means that approximately 5% of the t-tests fail (5% x 344 x 16 = 275.2) although the hypothesis (mean values are equal) is correct. This creates a certain level of background noise in the graphs. An example for this type of analysis is shown in Figure 6. To simplify the comparison between the different rules, we defined the disturbance index which is the number of failed t-tests during the simulation period. The 5% false positives on average are no problem since the number of t-tests is the same for each scenario. Otherwise a comparison would not be possible. It has to be taken in account as well that the WIP flow in the OTD fab is much smoother. This means that the t-tests will fail earlier in the OTD fab compared to the fab dispatching with FIFO or Priority-FIFO. Apart from that, the index turns out to be a good indicator for the amount of disturbance in the fab.

Figure 6: T-test diagram Table 5: Disturbance index for the different dispatch rules

The first notable aspect in Table 5 is the large value of 680 for OTD. The disturbance index is nearly twice the value of the disturbance indices of any other dispatch Dispatch rule Disturbance index rule tested. This has two main reasons. The first reason FIFO 359 is that the way OTD dispatches is counterproductive in FIFO with priority on peak lots 380 this peak situation. The lots on the route with the wafer Priority FIFO 345 start peak are delayed at the bottleneck. This “lateness” OTD 680 gives them a priority on the rest of the route since OTD tries to catch up “lateness”. On non-bottleneck work stations where other products are also processed, these other products now have to wait until they have the same lateness or all late lots are processed. This way, other routes build up WIP as well. This leads to an increase in the disturbance index. The other reason is the smoother WIP flow of OTD which causes the t-test to fail earlier. A quick visual comparison of Priority-FIFO graph and OTD graph confirms the explanation above. The OTD graph shows much more “holes” than the Priority-FIFO and more products are affected in the OTD scenario compared to Priority-FIFO. This is a trade off for the benefits OTD provides. In this case, the smaller spread for the cycle time distribution is “bought” by the increased number of disturbed products and the increased disturbance in the fab as a whole.

Conclusions There are several conclusions to be drawn from this study. First of all, this type of analysis is very time consuming due to the number of runs to be made. But they are worth it because they provide insight in the way the fab works and how the method of dispatching affects the daily business.

A general result that can be transferred to other semiconductor fabs is the effect of OTD. Bottlenecks on one route increase the WIP on other routes as well. This is a result of OTD trying to catch up the lateness from the bottleneck. Prioritizing of late products increases waiting time and thus WIP and cycle time for other products. The magnitude of this disturbance depends on the fab, its load, the routes, etc. In our opinion, it is not possible to determine the magnitude of this disturbance in advance for arbitrary scenarios and models. The study shows how much this type of analysis depends on the fab model, the product mix, and the load situation. The general analysis of peaks dispatched with the priority FIFO dispatching rule showed that these peaks can be permitted in a fab. The time the fab is disturbed is very long. In particular, if the peak is a major wafer surge, it begins to affect other products. This is certainly not desirable and has to be taken into account for the decision if a wafer start peak should be allowed or not. The limit at which the peak seriously affects other products depends on the dispatching rule and the fab model itself, in particular, the free capacity on shared tools. An interesting result for semiconductor companies working with ODD and derivates like OTD is that the cycle time distribution spread remains low even during peaks. And the fluctuation in WIP is smaller with this kind of rules. This is especially important for planning the wafer test that follows the front end. The more predictable the input for the wafer test the better the better it is for the overall performance. The two methods we developed to find and measure the extent of disturbances in the fab, the t-test diagram and the derived disturbance index, proved to be valuable tools to understand the WIP flow. One problem of these tools is the fact that the t-test can only test for equality. Inequality can not be tested and the difference can not be determined either. The t-test can only be an indicator that the WIP level is above or below normal. Despite their weaknesses, both tools were a valuable help in finding the differences between the normal simulation runs and the ones with the peaks. The t-test diagram revealed differences in WIP levels that the human eye can not differentiate. The disturbance index summarizes the diagram into a single number that is handy for presenting the results of scenario comparisons.

Acknowledgments The author would like to thank Tobias Langner for his valuable simulation efforts and fruitful discussions. The experiments were made during his internship at the Dresden fab of Infineon Technologies. We would like to thank all the people at Infineon Technologies for their support, in particular, Wolfgang Scholl, Jörg Domaschke, and Thomas Jähnig.

References 1. Dümmler, M., and Rose, O., “Analysis of the Short Term Impact of Changes in Product Mix,” Proceedings of the MASM 2000. 2. Falk, M., Marohn, F., and Tewese, B., Foundations of Statistical Analyses and Applications with SAS, Birkhäuser Verlag (2002). 3. Rose, O., “WIP evolution of a semiconductor factory after a bottleneck workcenter breakdown,” Proceedings of the 1998 Winter Simulation Conference. 4. Rose, O., “Accelerating products under due-date oriented dispatching rules in semiconductor manufacturing,” Proceedings of the 2003 Winter Simulation Conference.