PARALLEL AUTOMATON AND ITS HARDWARE IMPLEMENTATION Bernd Steinbach1 , Arkadij Zakrevskij2 1 Freiberg University of Mining and Technology, Germany e-mail:
[email protected] 2 Institute of Engineering Cybernetics NAS, Belarus e-mail:
[email protected]
Abstract. Logical control devices are intended for maintaining proper interaction between components of complicated engineering complexes. In general case, they are asynchronous systems carrying out control for several processes proceeding in parallel. Their design begins with working out parallel algorithms for logical control (PALC). A formal language PRALU is suggested for that, as well as its standard form interpreted as the parallel automaton which unlike the conventional one can be placed simultaneously in several places called partial. A method of its hardware implementation is developed including stages of checking for correctness, partial states assignment, obtaining a sequent automaton and a corresponding set of Boolean functions in disjunctive normal form which can be easily realized on a PLA.
1
Introduction
Regarding various complex engineering systems, we see that they consist of many parts that exist and work in parallel. The same could be said about digital control devices which are constructed to provide these systems with a proper control: their components (flip-flops, logic gates, etc.) also exist and work in parallel. The logic design based on using the classical FSM-model in a sense ignores these circumstances and operates with strictly sequential models where all events occur one by one. Meanwhile, with increasing the number of states of a finite automaton it becomes too difficult to describe its behavior and to transform the obtained complicated description into a system of Boolean equations which is necessary for logic design. The next task of the design is to reduce that complexity [10], for example by means of several decomposition methods [9]. That is why some new models were suggested to deal with systems where some events can occur in parallel. There was proposed a formal language PRALU [14] for description of parallel algorithms for logical control (PALC) of complicated engineering systems such as modern computers, industrial systems, robotic complexes, etc. This control is performed by logical control devices that could be regarded as discrete dynamic asynchronous systems controlling concurrent processes. They exchange information with control objects via Boolean variables constituting two sets: the input set X and the output set Y which can intersect in the case of feed-backs. A standard form of PRALU-algorithms was proposed, named a parallel automaton [13] which differs greatly from the classic finite automaton. This abstract model described below is rather general and can be used at different stages of logical design, beginning from the stage of formulating a PALC and its checking for correctness. There are described in this paper original methods for solving several tasks of logical design on the base of the proposed model of parallel automaton: definition of the property of correctness of a PALC and its checking, a parallel automaton state assignment, obtaining a corresponding system of simple sequents, synthesizing a programmable logic array (PLA) which implements a given PALC.
2
Parallel automaton and α-net
Any algorithm is represented in PRALU as a set of chains (linear algorithms composed of waiting and acting operations) that can be executed one by one or in parallel under the control of a mechanism of the Petri net type. A standard form for PRALU-algorithms has been introduced interpreted as the parallel automaton which unlike the classic one, can be placed simultaneously in several states. A parallel automaton can be regarded as an unordered set of restricted chains αi , each having the form µi : −k i ′ →k i″ →νi
(1)
where k i ′ and k i″ are elementary conjunctions using some variables from X and Y respectively, µi and νi are initial and terminal labels represented by some subsets of the set M = {1, 2, …, m} the elements of which are called partial states. Unlike the conventional sequential automaton, the parallel automaton can be placed in several (partial) states at the same time. They constitute a global state N which takes value Nt at the current moment t. Expression −ki ′ is called waiting operation and is interpreted as "wait until k i′ = 1". Expression →k i″ is called acting operation and is interpreted as "provide term k i ″ with value 1". Expression →νi is called transition operation and is interpreted below. Chain αi is executed if µi ⊆ Nt and ki ′ = 1 (if the automaton is in the states listed in label µi (and, perhaps, in some others) and if the variables in conjunction term k i′ assume the values at which ki ′ = 1). In that case the variables from term k i ″ accept the values at which k i″ = 1, and the partial states forming label µi are substituted by the states from label νi . Thus a transition is made between groups of states rather than between separate states. The states not listed in µi and νi are not affected by this transition: if the automaton finds itself in any of them, it will remain there, otherwise it will not enter this state. Analogously, assume that all variables from k i ″ preserve their new values until some other operations change them. An automaton with such a property is called inertial. Note that several chains can be executed simultaneously - they are called parallel. This model differs basically from the classic sequential automaton model. In the case of synchronous interpretation, it may be reduced to the latter, yet practically it could be made by far not always: for example, a parallel automaton with 3n partial states may generate a sequential automaton with 3n states. In the case of asynchronous interpretation reflecting local interactions between some variables (such interactions can take place when the transients corresponding to changing values of other variables have not yet been attenuated) such reduction is not possible at all. Two mechanisms of interaction between chains are used in the model. One of them is a simplified version of the ordinary Petri net and is called α-net [12]. It is defined as a system consisting of the set N0 (initial global state) and the set of pairs µi - νi called transitions and denoted as τi . By analogy with the Petri net it is interpreted as a dynamic model with the set of places M, the initial state N0 and a current state Nt that is changeable at transitions. It is supposed that transitions τi may occur, one by one, when the conditions µi ⊆ Nt are satisfied, and that execution of τi consists in replacing the current value Nt by (Nt \ µi ) ∪ νi . Example 1. There are shown a parallel automaton and corresponding α-net 1: 9: 2: 10: 11: 2: 3: 4: 12: 4: 5: 6.7.8: 13:
−u →ab →9 −u′ →2.3 −v′w →b′ c →10 −w′ →b →11 →c′ →2 −v →a′ c →4.5 −uw →d →6 −u′ v′ →a →12 −u →a′ →4 −u →ab′ →7 −v′w →c′ →8 →a′ d →13 −w′ →1
1-9 9 - 2.3 2 - 10 10 - 11 11 - 2 2 - 4.5 3-6 4 - 12 12 - 4 4-7 5-8 6.7.8 - 13 13 - 1
Note that the absence of operation −k i′ in chain αi is equivalent to the presence of operation −1. Let us call an α-net safe if for any reachable (from N0 ) state Nt and for any transition τi the condition (µi ⊆ Nt ) → ((Nt \ µi ) ∩ ν i = ∅)
(2)
is satisfied. And we call it live when after executing any sequence of transitions each transition can take place again (maybe some time later). Besides, according to some constraints in PRALU language the following condition should be satisfied for every α-net: (i ≠ j) & (µi ∩ µj ≠ ∅) → (µi = µj )
(3)
The following affirmation establishes a relationship between α-nets and expanded nets of free choice (EFC-nets) investigated by Hack [5]. Affirmation 1. Safe α-nets are equivalent to safe expanded nets of free choice. The second mechanism of possible interaction between chains of a parallel automaton is presented by pairs of operations −k i′ →k i″. Such a pair is similar to the sequent k i′ |− ki″ , specifying the conditionevent relationship between simple events represented by conjunction terms k i′ and ki ″ : the event ki ′ (ki ′ takes value 1) gives rise to the event ki ″ (ki ″ also takes value 1). Different chains can have some common variables. The chain αi is able to control chain αj if σi ″∩ σj ′ ≠ ∅ where σi ″ and σj ′ denote the sets of Boolean variables in k i ″ and k j′. If σi ″∩ σj ′ ≠ ∅ and σj ″∩ σi ′ ≠ ∅ , then chains αi and αj will be able to carry on a dialog.
3
Checking parallel automata for correctness
Constructing PALCs is tightly connected with their verification including checking algorithms for correctness. We shall call any algorithm correct if it possesses the following five qualities [14]. The algorithm is irredundant if it contains no chains that can never be executed. The algorithm is recoverable if it can return to its initial state from any reachable state (that demand is evident for a cyclic algorithm to which every algorithm can be easily reduced by its closing - adding one transition leading from the terminal state to the initial one). The algorithm is consistent if any of its parallel chains αi and αj are compatible. In particular, in this case the condition ki ″ & kj″ ≠ 0 should be satisfied. The algorithm is persistent if the completion of one of the parallel chains being performed does not destroy conditions for executing the others (conditions ki ′ & kj″ ≠ 0 and ki ″ & kj′ ≠ 0 for parallel chains). The algorithm is selfcoordinated if none of its chains can be reinitiated during its execution. Note that irredundancy and recoverability requirements are applicable both to parallel and purely sequential algorithms, whilst consistency, persistency and self-coordination are the specific properties of correct parallel algorithms. Checking an algorithm for correctness is reduced to a great extent to checking the corresponding α-net for liveness and safety. The verification of liveness is known to be easier and can be performed by a method suggested for ordinary Petri nets and reducing the problem to solving logical equations [14]. It is more difficult to verify the safety property. The direct method of integrated checking algorithms for these two qualities is known to be applicable both to α-nets and Petri nets of a much wider class. This method involves the construction of a set of all reachable states and can be used practically only in the case of small nets. More promising seem to be reduction methods using local simplification operations, which decrease the complexity of the regarded nets [2]. An efficient reduction algorithm of that kind was suggested in [15].
4
State assignment
Conventionally, the state assignment procedure is regarded as the first step on the way to hardware implementation of an automaton. For a traditional sequential automaton, when all the states are incompatible and any of them can appear only alone, each state may be represented by a Boolean vector that can be realized, for example, as a combination of states of flip-flops forming a register. But in the
case of a parallel automaton with partial states which could coexist (be parallel) this method is inadequate. That is why it was suggested in early eighties [1, 11] to use for coding partial states ternary vectors, with components taking values from the set {0, 1, -}, where symbol "-" is interpreted as an arbitrary value (0 or 1). Such vectors should be non-orthogonal for parallel states, so that the latter ones could be implemented by a single Boolean vector. Note that two ternary vectors are called orthogonal if there exists a component where one vector takes value 1 and the other value 0. For instance, if 1-0-0, -10-- and ---10 are the coding ternary vectors for three parallel states, then vector 11010 does implement all of them. To minimize the code, it is reasonable to use orthogonal ternary vectors for non-parallel (incompatible) states. Another good quality of the code could be reached by that, which is called superseding quality. In that case the execution of any transition can be reduced to the automaton displacement into the partial states forming the set νi \ µi ; as to the states from µi \ νi , the automaton leaves them automatically. The code with such a property has been called the superseding ternary code (ST-code). Suppose that when constructing ST-code we do not use the entire information contained in the α-net but consider only the set of all global states admitting direct transitions between any of them. An ST-code found in that case is called universal (UST-code). Note that it can exist only for a correct parallel automaton. An important theorem was proved in [12]. Affirmation 2. Assigning orthogonal ternary vectors to every pair of non-parallel partial states and nonorthogonal vectors to parallel ones, we get an UST-code for any correct parallel automaton. Its prove is based on the two following auxiliary affirmations. Affirmation 3 . UST-code for a parallel automaton exists iff every global state of the latter is c-maximal, i.e. corresponds to a maximal complete subgraph of the graph G(A) representing the relation of parallelism on the set of partial states of automaton A. Affirmation 4. Every reachable marking of a live and safe EFC-net is c-maximal. The latter affirmation, in its turn, follows from the known theorem by Hack [5] which tells that when some EFC-net is live and safe, the set of all places can be covered with its subsets each having exactly one common element with every reachable marking. Finding a minimum UST-code for a given parallel automaton is a hard combinatorial problem. Practically efficient algorithms for solving it were suggested in [14, 16]. Some additional gain in the number of coding variables can be reached by using for coding as well control variables which preserve their values in any inertial parallel automaton, changing only by means of acting operations. To accelerate the coding process in the case of large automata, the block coding method was developed that decomposes the set of all partial states into blocks containing usually non-parallel states and codes separately blocks and states inside blocks, concatenating them afterwards [11]. 4.1 Algorithms for partial state assignment The problem of partial state assignment can be formulated as follows. Let P be a set of partial states and R is a symmetrical n × n Boolean matrix which presents the orthogonality relation: ri j = 1 if states p i and p j are not parallel (and so their codes should be orthogonal). The problem is to assign a ternary vector with m components for each state. By that non-parallel states should receive orthogonal vectors, parallel states should get non-orthogonal vectors. The components of the regarded ternary vectors correspond to coding Boolean variables, and their number m plays the role of optimization criteria - the less it is, the better. Note that this problem can be formulated as well in terms of graph theory. In that case the regarded relation of orthogonality is presented by a graph with vertices corresponding to partial states, and the set of its edges (representing the elements of the relation) must be covered by minimum number of complete bipartite subgraphs.
Affirmation 5. The construction of a minimum UST-code for a correct parallel automaton A can be reduced to covering the graph supplementary to G(A) by minimum number of complete bipartite subgraphs. The obtained ternary vectors constitute a coding matrix C: the columns of the latter correspond to partial states and represent codes for them, the rows correspond to coding variables and may be interpreted as partial partitions on set P. Example 2. Matrices R and C are given below for an automaton with P = {a, b, c, d , e, f}. a b c d e f 0 R = 1 0 1 0 1
1 0 0 0 1 1
0 0 0 0 1 1
1 0 0 0 1 0
0 1 1 1 0 0
1 1 1 0 0 0
a b c a b c d e f
C=
d e
f
- 1 1 - 0 0 0 1 - 1 0 1 - - - - 0
The solution presented here by matrix C is optimal. But how to find it? Note that each ternary row ci of coding matrix C covers some 1s of matrix R. That means that if ci j = 0 and ci k = 1 or ci j = 1 and ci k = 0, then rj k = rkj = 1. The set of such 1s produced by row ci constitutes a symmetrical pair of 1-minors in R (minors of R consisting of 1s only) - they are demonstrated below. The three rows cover together all 1s in matrix R. − 1 1 − 0 0
0 1 − 1 0 −
1− − − − 0
0 0 0 0 0 0
0 1 0 1 0 0
0 0 0 0 0 1
0 0 0 0 1 1
0 0 0 0 1 1
0 0 0 0 0 0
0 1 1 0 0 0
0 1 1 0 0 0
1 0 0 0 1 0
0 0 0 0 0 0
1 0 0 0 1 0
0 1 0 1 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
1 0 0 0 0 0
It follows from here that the problem can be reduced to finding a minimum set of such symmetrical pairs for covering all 1s in the given matrix R. Various algorithms were suggested to solve this problem [7, 14, 16 and others]. For example, rather complicated Exact algorithm reduces the problem to finding a shortest row cover for a certain Boolean matrix produced from the orthogonality matrix R by conjunctive closure of the set of its rows [14]. Unfortunately, this new matrix grows very fast with increasing the size of R. The time spent to cover it becomes too large, and that limits the area of applicability of Exact algorithm. Some heuristic algorithms were suggested. The simplest of them is Star algorithm. It covers the set of edges E of the orthogonality graph by a minimum number of so called stars: subsets of E comprising some edges having a common vertex. The number of such subsets is comparatively small, so the algorithm is fast. A quick heuristic algorithm of the minimax type (Quick) was developed [16]. It constructs one by one rows of the coding ternary matrix C and reduces by that matrix R changing covered 1s for symbol "-" and deleting rows and columns which lost all 1s. Two tasks are solved at each step. For a given value of orthogonality matrix R the algorithm finds first a promising 1-element - that can be covered by possibly minimum number of maximal 1-minors. Second, there is selected from them a minor covering possibly maximal number of 1s (uncovered so far). Some heuristic taking into account that regarded minors form symmetrical pairs is used for solving each of these two tasks. The process continues until all 1s in the orthogonality matrix are covered. The mentioned above three algorithms were subjected to computer experiments (PC Pentium 100, C++) based on generation of a sequence of pseudo-random orthogonality matrices R with various percentage p = m/n(n-1) of 1-values. Here n is the number of rows (and columns) in the square matrix R, m - the total number of 1-values.
The results of the experiments testify a high quality of solutions obtained by Exact algorithm. But it could be recommended only for rather high percentage p of 1s in matrix R (definitely more than 50%, and that is typical for real parallel logical control algorithms) and for comparatively small matrices R (when n does not exceed 20-30). For two other algorithms the influence of percentage p on runtime t is rather small. But with increasing of p (75% and more) the quality of Quick algorithm solutions becomes considerably better compared with Star algorithm. Note that for p = 100% these solutions are optimal. So Quick algorithm could be recommended for big matrices R with high percentage of 1s. But for smaller p (50% and less) the Star algorithm as a rule produces better solutions and could be recommended for application, the more so it has the lowest runtime.
5
Sequent automaton
There was proposed in [4] and developed later a formal language for description of logical devices with great number of Boolean input and output variables (which was impossible when using the conventional finite automaton model). The new model was named the sequent automaton. Formally it can be regarded as a set S of elements si called sequents. They are presented by expressions fi |− ki where fi is a Boolean function and k i - some elementary conjunction. Semantics of such an expression is defined by the following interpretation: if at a current moment function fi equals 1, then immediately after that term k i should take value 1 (all variables in k i must be properly assigned). Let us say that sequent si is executed in such a way. Several sequents could be executed simultaneously, in such a case they are called parallel. Some conditions should be satisfied for sequent automata to secure their consistency, for example condition ki &kj ≠ 0 for any parallel sequents si and sj - otherwise some Boolean variable must receive values 1 and 0 simultaneously. It will be sufficient for us to consider below only simple sequents - expressions k i* |− ki** representing pairs of conjunction terms connected by the "cause-effect" relation: if k i * , then ki** . A set of simple sequents can be regarded as a simple sequent automaton. It can be presented conveniently in matrix form, by a pair of ternary matrices: a cause matrix A and an effect matrix B. Example 3. The same simple sequent automaton is presented both by a symbolic expression (left) and by matrices (right): abcpqr pqruvwz aq′ |− qvz, b′cp |− r′uw′, a′bqr |− pq′vz′, c′r′ |− p′w, c′pq′ |− qru′w
A=
1− − − 0− −0 11− − 0 1 − −1 1 − − 0 − −0 −−010 −
B=
−1−−1−1 −−01 −0− 10−−1 −0 0− − −− 1− −11 0−1 −
Having coded all partial states we can convert a parallel automaton into a sequent automaton. If we have got an UST-code, we can pass from every chain αi expressed as µi : −k i ′ →k i″ →νi to a corresponding simple sequent k i* |− ki** implementing it. This can be performed in the following way: - labels µi and νi are changed for the ternary vectors presenting the result of "intersection" of the vectors coding the labels components; - the obtained vectors are interpreted as conjunction terms γi ′ and γi ″ ; - the sequent terms are found by the formulae k i * = γi′ k i′ , ki ** = k i″ γi ″ . (4) Example 4. Consider the chain 5.6: −ac' →u'vx →4.6.9 . Suppose that the partial states indicated in the chain labels are coded by the ternary vectors, which components show the values of coding variables z1 , z2 , z3 , z4 : 4 = − 1 − 1, 5 = 1 − − −, 6 = − 1 − −, 9 = 0 − 0 −. Then vector 1 1 − − is assigned to the initial chain label, and vector 0 1 0 1 - to the terminal one. On the whole, the chain is implemented by the simple sequent z1 z2 a c' |− u' v x z1 ' z3 ' z4 - note that literal z2 was deleted from the right part as unnecessary.
6
PLA implementation
Having changed each chain in a regarded parallel automaton for a sequent, it is not difficult to find a corresponding system of Boolean equations for design of a logical control device. Particularly, if the size of a simple sequent automaton is not too big, it is rather easy to implement it by a PLA as is demonstrated below. Example 5. A sequent automaton is presented below, both in symbolic and matrix form, that corresponds to the parallel automaton regarded in Section 2. Its states assignment was performed by means of the block coding method with using control variables as well as specially introduced coding ones. Inasmuch as this automaton is considered to be an inertial one, matrix B indicates only changes of variable values.
u v
ux′y′a′ |- ab u′x′y′a |- x v′wxy′c′ |- b′c w′xy′b′c |- b xy′bc |- c′ vxy′c′ |- ya′c uwxd′ |- d u′v′xya′ |- a uxyab |- a′ uxya′ |- ab′ v′wxyc |- c′ xyab′c′d |- x′a′d′ w′x′y |- y′
w x x' y y' a a' b b' c c' d d' x x' y y' a a' b b' c c' d d'
uvwxyabcd
xyabcd
1−−000−−− 0−−001−−− −0110−−0− −−010−01− −−−10−11− −1−10−−0− 1−11−−−−0 00−110−−− 1−−1111−− 1−−110−−− −0111−−1− −−−111001 −−001−−−−
− −1 1 − − 1−−−−− −−−01− −−−1−− −−−−0− −10−1− −−−−−1 −−1−−− −−0−−− −−10−− −−−−0− 0−0−−0 −0−−−−
A
B
Fig. 1. A programmable logic array.
We can rather easily find from here a hardware solution for the regarded example, using the PLA technology. The ternary matrices A and B are changed for the corresponding Boolean matrices by splitting each ternary row into a pair of Boolean ones (by the rule 1 → 10, 0 → 01, – → 00). The result is interpreted as the structure description of an PLA with feed-backs. ones in the first Boolean matrix mark positions of transistors in the AND stage of the PLA, ones in the second matrix - in the OR stage. The obtained PLA implementing the given logical control algorithm is shown on Fig. 1 where each of the mentioned Boolean matrices turns out to be transposed:
7
Concluding remarks
Different approaches could be applied to implement parallel automata. The distributed design on the system level is comparable with the transformation of a VHDL specification into interacting FSM (IFSM) [3]. It is possible and easy to implement a parallel automaton by parts using macrocells of a complex logic device (CPLD) or complex logic blocks (CLB’s) of a field programmable gate array (FPGA). For this task a lot of software tools are available produced by Synopsys, VIEW logic, Mentor Graphics or Cadence Design Systems, and the chips can be selected for wide supply, e.g. by Altera Corp., Xilinx, Lattice Semiconductors or Actel Corp.
In this paper, we use another approach. It is possible to reduce the number of necessary macrocells or CLB’s if we merge some of the chains into one medium automaton. The source of this advantage is given by optimal coding of the states of the combined chains. In order to demonstrate this effect clear, we realize all chains of the parallel automaton by a single PLA. Note, the PLA and the register may by mapped onto a small CPLD or FPGA. Note also, that Boolean input and output variables were used in the regarded model of parallel automaton. But this restriction is not obligatory. More general models we get by using multi-valued variables for input, output and inside of an automation. Basic approaches for the design of such multi-valued systems are suggested in [7, 8].
Acknowledgement This work was supported by a Research Grant from the International Science and Technology Center. References [1] [2] [3]
[4]
[5] [6] [7]
[8]
[9]
[10] [11] [12] [13] [14] [15] [16]
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