Whoops! : a Clustered Web Cache for DSM Systems using Memory Mapped Networks Emmanuel Cecchet INRIA - SIRAC laboratory*
[email protected] Abstract In this paper, we present Whoops!, a clustered web cache prototype based on SciFS, a Distributed Shared Memory (DSM) that benefits from the high performances and the remote addressing capabilities of memory mapped networks like Scalable Coherent Interface (SCI). Whoops! uses the DSM for all web cache management and cache storage. Using a memory mapped network and a DSM programming model allow us to investigate new algorithm to distribute and handle requests. We present a new implementation of TCP handoff that directly maps remote TCP/IP stacks through the network. This technique reduces processor overhead and forwards TCP acknowledgements in few microseconds. We have also designed Parallel Pull-Based LRU (PPBL), an efficient request distribution algorithm for use with DSM systems. Unlike other distribution algorithms the decision is distributed over all nodes thus providing better scalability. PPBL supports multi-frontend environments letting the DSM handle data distribution. Finally, Whoops! implements on the fly compression when fetching document from the Web and on the fly decompression when sending documents to clients. We show how this technique can reduce paging activity in the DSM and improve overall cache performance. +
Whoops!
Socket Interface
User space
Linux VFS
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Keywords : web cache, cluster, DSM, memory mapped network, SCI, TCP handoff, on the fly compression.
1. Introduction Web caches have become the standard method to ensure an acceptable quality for Web access. For a cache implemented on a single dedicated computer, the throughput is quickly limited by the network interface. SMP computers also have to face this limitation. In contrast, cluster-based Web caches allow the throughput to be increased by simply adding nodes (and therefore network interfaces) to the cluster. Distributed Shared Memories (DSM) have been designed to allow the user to program applications like on a large SMP. However, software DSM performance has always suffered from regular network performance. Memory mapped networks, such as Scalable Coherent Interface or SCI (IEEE 1596 standard [12]) allows a processor to directly
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access a remote memory byte in read or write without involving the operating system. Communication reliability is ensured by hardware avoiding error control in the software layers. Those features combined with a very low latency (
