Optical Engineering 47共3兲, 035201 共March 2008兲
Parallel-shift register and binary multiplier using optical hardware components Tamer A. Moniem Nabil Abd Rabou E. M. Saad Faculty of Engineering Helwan University Electronics and Communication Department 1 Shereef St., Helwan City Cairo, Egypt E-mail:
[email protected]
Abstract. An optical four-bit parallel-shift register that consists of four serially connected optical flip-flop memories is driven by common clock pulses. Each optical flip-flop consists of two coupled polarization switches that share an all-optical demultiplexer, which makes the optical flip-flops easily connected with each other to form a parallel-shift register. The optical flip-flops are controlled by clock pulses. The parallel-shift register and an optical parallel adder are used to demonstrate an alloptical binary multiplier and its optical control circuit. The concept is demonstrated at an operation speed of 10 MHz for registers and 1 MHz for a multiplier, which is limited by long laser cavities formed by the optical fiber. © 2008 Society of Photo-Optical Instrumentation Engineers.
关DOI: 10.1117/1.2898632兴
Subject terms: optical logic gate; optical parallel adder; optical processor; optical flip-flop; logic multiplier; semiconductor optical amplifier. Paper 070788R received Sep. 19, 2007; revised manuscript received Nov. 12, 2007; accepted for publication Nov. 16, 2007; published online Mar. 25, 2008.
1 Introduction Optical parallel and shift registers have received considerable attention since potentially they could be applied in optical packet buffers and serial-to-parallel converters. References 1 and 2 show that a circulating optical shift register was realized using fiber buffers and Sagnac interferometers. Another example, given in Ref. 3, is based on optical flipflops that consist of two ring lasers sharing a single active element. This design makes the optical flip-flops easily cascaded with each other, where the two cascaded optical flipflops are controlled by clock pulses.3 This paper presents an optical parallel-shift register based on cascaded optical flipflop memories driven by common optical clock pulses. The optical flip-flop memory consists of two coupled polarization switches4 共PSWs兲 that share an all-optical demultiplexer 共DMUX 1*2兲,5 which makes the optical flip-flops easily connected to each other to form a parallel and shift register. The optical multiplier with optical ALU depicted in Ref. 6 can be used in an arithmetic operation to perform a fast central processor unit using optical hardware components. In Ref. 7, ultracompact optical flip-flops with a switching speed greater than 100 GHz were demonstrated. This means that this concept has potential to be integrated and to perform at high speed.
port I of a polarization beamsplitter 共PBS兲 to set the flipflop in state 1.4 The optical pulses are injected into PSW2 via port II of the PBS to reset the flip-flop in state 2.4 The ports of set and reset are connected to the output of the all-optical DMUX 1*2 with the input connected to a laser source with 1 mw power and a wavelength of 1551 nm. The selection of DMUX is considered as the input D of the
2 All-Optical D Flip-Flop The structure of the all-optical flip-flop memory is depicted in Fig. 1.4 It consists of two coupled PSWs. The first switch, PSW1, outputs light that is injected into the second switch, PSW2. Hence, the light output of PSW1 acts as a saturating control signal for semiconductor optical amplifier 2 共SOA2兲 that can suppress PSW2, and the light output of PSW2 can act as a saturating control signal for SOA1 to suppress PSW1.4 Optical pulses are injected into PSW1 via 0091-3286/2008/$25.00 © 2008 SPIE
Optical Engineering
Fig. 1 Configuration of the all-optical flip-flop based on two polarization switches.
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Fig. 2 Parallel-shift register consisting of cascaded optical D flip-flop memories and control optical MUX.
flip-flop. So, if D = 1, the laser beam is applied to the set port to set the flip-flop; and if D = 0, the laser beam is applied to the reset port to reset the flip-flop. 3 All-Optical Parallel-Shift Register This section presents the all-optical four-bit parallel-shift register, which consists of cascaded optical D flip-flop memories driven by common optical clock pluses, as shown in Fig. 2. The selected input DMUX is connected to the output of two all-optical input AND gates, which is demonstrated in Ref. 5. The first input of the AND gate is the common optical pulse of 10 MHz. The second input of the AND gate is delivered from the output of the all-optical multiplexer MUX 2*1, as demonstrated in Ref. 5. The first input 共0兲 of MUX is connected to the output of the previous flip-flop except the first MUX, which is connected to the input serial data. The second input 共1兲 of MUX is connected to external data as parallel data. The selected MUX is connected to an external common control line so that, if the control line = 0, the register operates as a serial-shift register, and if the control line= 1, the register operates as a parallel load register. The SOA and optical coupler 共50:50兲 are used with a control line and a clock pulse to be equal for all flip-flops.3,6 3.1 Simulation Result of Parallel-Shift Register The input pulses have a wavelength of 1552.9 nm, duration of 10 ns, and frequency of 10 MHz with an optical peak power of 1 mW. Figure 3 shows the simulated waveforms of the optical binary inputs for D0, D1 and D2 as examples, and outputs Q0, Q1, and Q2 for the parallel load of the Optical Engineering
register when the control line= 1. The simulation results of the serial input of the shift register for D0, Q0, D1, and Q1 showing the serial shift are depicted in Fig. 4, with the control line= 0. The optical pulses to change the state of either the parallel- or shift-register were injected every 10 ns, as shown in Figs. 3 and 4. All waveforms were scaled with arbitrary units and obtained using simulation computer-aided design 共CAD兲 with the beam propagation method. 4 All-Optical Binary Multiplier Due to the lack of reliable optical logic devices, the signalprocessing technology currently used in optical-packetswitched cross-connects and optical processors is based on a combination of electronic and optical technology. An alloptical arithmetic operation such as the multiplier is carried out in the electronics while the payload remains in the optical domain, where the overall operation is implemented using all-optical hardware components. All-optical multipliers have many potential applications in optical communication systems and optical computing, which can lead to the construction of an all-optical processor unit. This section describes an all-optical circuit that performs multiplication of two binary optical words of four bits and could be used for applications such as packet header processing and in the construction of optical central processor units. The register configuration for the binary multiplier is shown in Fig. 5. The multiplicand is stored in register B, the multiplier is stored in register C, and the partial product is formed in register A. Register A is formed by the parallel-shift register according to the binary multiplier in
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Fig. 4 Optical waveform of a serial-shift register.
mented after the formation of each partial product. When the content of the counter reaches 0, the product is formed in the double registers A and C, and the process stops at zero flag Z = 0. The optical output terminal Y is applied to the control terminal of parallel-shift register A to control the type of register operation.
Fig. 3 Optical waveform of a parallel-load register.
Ref. 8. A binary all-optical parallel adder6,9 is employed to add the content of register B to the content of register A. The single flip-flop Cout stores the carry after the addition. 4.1 Optical Hardware Control for Multiplier A flowchart in Ref. 8 shows the sequence of operations in the binary multiplier. Register A and flip-flop C are reset to 0 and the sequence counter P is loaded with a binary number n, which is equal to the number of bits in the multiplier. The multiplier bit in C0 is checked, and if it is equal to 1, the multiplicand in register B is added to the partial product in register A. The carry from the addition is transferred to flip-flop Cout. The partial product in register A is left unchanged if C0 = 0. The P counter is decremented by 1 regardless of the value in C0. Registers A and Q are then shifted once to the right to obtain a new partial product.8 The optical control circuit is depicted in Fig. 6, which controls the overall operation of the multiplier. This circuit consists of two optical D flip-flops, an optical 2*4 decoder as depicted in Ref. 5, and a set of optical AND and OR formed by the hardlimiters, as depicted in Refs. 5–10. The P counter is initially set to hold a binary number equal to the number of bits in the multiplier. The counter is decreOptical Engineering
4.2 Simulation Result of Multiplier The input pulses have a wavelength of 1550 nm, duration of 0.3 ms, and frequency of 1 MHz, with an optical peak power of 1 mW. Figure 7共a兲–7共c兲 shows the simulated waveforms of the optical binary sequence for the control circuit 共T0, T1, T2兲, register C, register A, the optical output of the control circuit, and the zero flag 共Z兲 as examples for the multiplication of 1011 and 1001. The product is formed in the double registers A and C at clock pulse number 10, which is 01100011, and the process stops at Z = 0. All waveforms were scaled with arbitrary units and obtained using simulation CAD with a beam propagation method. 5 Conclusion An all-optical parallel-shift register based on serially connected optical flip-flop memories driven by common clock pulses, and an all-optical arithmetic multiplier with its control circuit based on the design of Ref. 8, have been designed and numerically simulated 共using a beam propagation method兲 at an operation of 10 MHz for the register and 1 MHz for the multiplier. All-optical system computation eliminates the conversion from optical to electrical and vice versa. Accordingly, the latency is smaller than that using
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Fig. 5 All-optical equipment configuration of an optical multiplier.
Fig. 6 All-optical control circuit of a multiplier.
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Fig. 7 Simulation result waveform of an optical multiplier.
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electrical digital computation. The time taken by each alloptical digital device is reduced to subnanoseconds by building integrated Bragg gratings and optical fibers on SOI ridge waveguides.11 The operation speed may be increased to create a fast optical central processor unit by using the photonic integration, which would decrease the dimensions of the building blocks.4,9
International, 268–279 共1988兲. 9. T. A. Rahman, M. K. Ahmed, and E. S. M. Saad, “All-optical arithmetic unit based on the hardlimiters,” in 6th WSEAS Conference, Corfu, Greece, 64–67 共Feb. 2007兲. 10. L. Brzozowski and H. Edward, “All-optical analog to digital converters, hardlimiters, and logic gates,” J. Lightwave Technol., 19, 114– 119 共Jan. 2001兲. 11. T. Murphy, T. Hastings, and H. Smith, “Fabrication and characterization of narrow-band bragg-reflection filters in silicon on insulator ridge wave guides,” J. Lightwave Technol. 1938–1942 共Dec. 2000兲.
Acknowledgment The authors would like to express their great thanks to the late Prof. M. K. Ahmed, who was one of our supervisors, for his discussions, encouragement, advice, and support.
Tamer A. Moneim received the BSc degree in electronics and communication engineering from Helwan University, Cairo, Egypt, in may 1997. He received the master degree in electronics and communication science in 2001. He is currently pursuing the PhD degree in electronics and computer engineering at University of Helwan, Cairo, Egypt. He is currently a teaching assistant in the Electronics and Communications Department, Engineering, Faculty of University of Helwan.
References 1. N. A. Whitaker Jr., M. C. Gabriel, H. Avramopoulos, and A. Huang, “All-optical, all-fiber circulating shift register with an inverter,” Opt. Lett. 16, 1999–2001 共1991兲. 2. A. J. Poustie, R. J. Manning, and K. J. Blow, “All-optical circulating shift register using a semiconductor optical amplifier in a fiber,” Electron. Lett. 32, 1215–1216 共1996兲. 3. S. Zhang, Z. Li, Y. Liu, G. D. Khoe, and H. J. S. Dorren, “Optical shift register based on an optical flip-flop memory with a single active element,” Opt. Express 13共24兲, 9708–9713 共2005兲. 4. Y. Liu, M. T. Hill, H. de Waardt, G. D. Khoe, D. Lenstra, H. J. S. Dorren, “All optical flip-flop memory based on two polarization switches,” Electron. Lett.. 38, 904–905 共2002兲. 5. T. A. Rahman, M. K. Ahmed, and E. S. M. Saad, “All-optical digital full adder, decoder and multiplexer by using hardlimiters,” in ICSES Conference, Lodz, Poland, 775–778 共Sep. 2006兲. 6. T. A. Rahman, M. K. Ahmed, and E. S. M. Saad, “All-optical arithmetic-logic unit,” WSEAS Trans. On Computer 7共6兲, 985–990 共July 2007兲. 7. M. T. Hill, H. J. S. Dorren, T. J. de Vries, X. J. M. Leijtens, J. H. den Besten, E. Smalbrugge, Y. S. Oei, G. D. Khoe, and M. K. Smit, “A fast low-power optical memory based on coupled micro-ring lasers,” Nature (London) 432, 206–209 共2004兲. 8. M. M. Mano, Computer Engineering Hardware Design, Prentice-Hall
Optical Engineering
Nabil Abd Rabou is currently teaching in the Electronics and Communications Department, Faculty of Engineering, University of Helwan, in Cairo, Egypt.
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E. M. Saad received the BSc degree in electrical 共communication兲 engineering, Cairo University, in 1967, and the Dipl.-Ing. and Dr.-Ing. degrees from Stuttgart University in 1977 and 1981, respectively. He is a member of ECS and EEES. He is currently professor of electronic circuits, Faculty of Engineering, University of Helwan.
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