Performance and Functional Test of Flip-Flops using Ring Oscillator Structure Renato P. Ribas1, André I. Reis1, André Ivanov2 2
Federal University of Rio Grande do Sul - Brazil, 1University of British Columbia - Canada
[email protected],
[email protected],
[email protected] importance of stuck-open faults in this kind of cells. A more detailed fault analysis was presented by Al-Assadi et al. [10] for storage elements. Makar and McCluskey [11] presented the minimum length of checking experiments for different types of latches. Resistive opens were analyzed by Champac et al. [12], emphasizing the importance of appropriate test vector sequence for effective testing of latches and flip-flops. In [13], Kim and Dutton presented a measurement setup for late transition detection, i.e., for metastability evaluation. Metastability measurement setup was also indicated by Cantoni et al. [5]. Moreover, a test setup was shown for Miller effect and noise analysis by Dike and Burton [6]. A more general on-chip test circuit for measurement of timing characteristics and power consumption was proposed by Nedovic et al. [14]. However, the operation of Nedovic [14] test circuit is not straightforward, and it requires some efforts in terms of external test signals generation and considerable additional circuitry besides the cell under test, that represents area overhead. Even though all those contributions have been done, the use of the ring oscillator structure (ROS) for testing sequential cells has not been actually explored. There is still a room for further improvement.
ABSTRACT In this work the performance and functional evaluation of D-type flip-flops, considering the presence of asynchronous set and reset signals, is proposed through the use of ring oscillator structure (ROS). Ring oscillators are efficiently applied for combinational gate delay measurements. However, such test strategy cannot be directly applied to sequential cells since the output signal transition is not controlled by a single input signal. Novel ROS stages built using flip-flop are presented. Besides the speed verification, power consumption and aging effect analysis can also be performed over the circuit under test. The proposed test solution is also suitable for a fair comparison of performance between different topologies of flip-flops. This test approach has been validated at the gate level, through functional simulations (VHDL), and at the transistor level, through electrical simulations (SPICE).
1. INTRODUCTION Flip-flops are one of the most important components in high-performance VLSI systems, which usually require a large number of such storage elements on a single die. As a result, they tend to consume a large share of system power, by heavily loading the clock and, consequently, generating large current spikes during switching [1]. Therefore, besides power dissipation and chip area, such sequential cells affect various other system characteristics like the implementation of the clocking subsystem, signal integrity, global placement of cells and wire routing.
In our work, we demonstrate the performance and functional test of D-type flip-flops with asynchronous set and reset signals based on the ROS. In the normal operation of the ring oscillator proposed, all possible output signal transitions are stimulated, i.e., the ROS operating frequency depends directly on the different delay arcs related to the cell under test. Moreover, ROS based structures are very suitable for delay test. This type of test structure is quite useful to evaluate some particular types of faults described in [10] as well as for resistive opens [12]. Furthermore, reliability monitors for aging effects (HCI, BTI, TDDB) are also commonly based on ROS [8][15].
Moreover, the great majority of ASIC design is based on standard cells methodology, which uses pre-designed cells available in libraries to build more complex circuits. Cell based design implies in a mandatory pre-validation of all cells available in a target library before applying them in the final consumer’s products [2]-[4]. This previous verification may be carefully performed for every cell, taking into account different aspects, not limited to cell functionality, timing performance and power consumption. Additional aspects include metastability [5], noise immunity [6], physical and electrical behavior variations [7], and impact of aging effects [8].
In terms of functional behavior, the circuits presented herein provide a large coverage of steady states associated to the cell under test. The self-timed ROS operation can be easily converted to a synchronous execution mode by just adding a register barrier and multiplexer. It is useful for power measurements (dynamic and static) and for very low frequency operation (step-by-step execution) that allows the evaluation of long term data retention.
In the particular case of latches and flip-flops, different test circuits and strategies have been proposed in the literature. Reddy and Reddy [9] pointed out the problem and
978-1-4673-0469-6/11/$25.00 ©2011 IEEE
Finally, the proposed structures can be also applied for comparison of different design styles and topologies of the
42
that no transition at the output Q results from a transition at the input data (D). These transitions are shown in Table I. It must be carefully verified for fully validation of the functional behavior of this type of cell.
same type of sequential cell, since all delay arcs contribute to the oscillation frequency value [18]. The proposed structures can be seen as an extension of the methodology proposed by Ribas et al. [19], and prelimiary results and discussions have been presented in [20].
Table I. Possible transitions in D-flip-flop with set/reset.
The paper is organized as follows. D-type flip-flop background is briefly reviewed in Section 2 to support the discussions in the rest of the paper. In Section 3, the proposed ROS structure is described presenting the novel flip-flop stages, the initial condition for starting the circuit operation, and the self-timed and the clocked or step-bystep executions (synchronous mode). Experimental results and the functional test coverage are presented in Section 4. Conclusions are summarized in Section 5.
S 0 0 ↑ 0 ↑ ↑ ↑ ↑ 0 0 0 0
2. BACKGROUND D-type flip-flop with asynchronous set and reset signals, indicated here as ‘DFFSR’, can be considered as the most general flip-flop cell available in a standard cell library. Nevertheless, the test principle proposed can be readily extended to other types of sequencial cells.
R 0 1 0 0 1
Ck ↑ (0,1,↓) -
D (0,1) -
Ck ↑ ↑ 0 0 1 1 0 0 1 1
D 0 1 0 1 0 1 0 1 0 1
Q-1 1 0 0 1 0 0 0 0 0 0 0 0
Q ↓ ↑ ↑ ↓ ↑ ↑ ↑ ↑ ↓ ↓ ↓ ↓
3. PROPOSED ROS STRUCTURE The use of ROS test structure for characterizing sequential cells, like latches and flip-flops, is not so obvious since the output signal cannot be modified only considering just one input signal, as occur in combinational gates. For instance, the output transitioning of a conventional flip-flop depends on the active clock edge, while no output switching is expected due to the other clock edge, excepting in the case of dual-edge flip-flops.
The normal operation of DFFSR can be described as follows. With the asynchronous set (S) and reset (R) signals deactivated, the output (Q) is updated with the input data (D) value when the clock (Ck) signal presents an activation transition, usually the rising clock edge. Otherwise, the output Q is kept unaltered (data retention or storage state). The activation of the asynchronous set and reset signals has priority over data input D and clock signals, and there should not be the simultaneous activation of both S and R signals. This behavior is summarized in Fig. 1. S 1 0 0 0 1
R 0 0 0 ↑ 0 0 0 0 ↑ ↑ ↑ ↑
3.1 Stages To build a ring oscillator for testing flip-flops, three different configurations of stages are proposed, as illustrated in Fig. 2. The first configuration, named as ‘StageCkS’, shown in Fig. 1(a), represents the transitioning of the output signal according to the clock edge and the set activation. When the stage input signal goes high (clock edge) the output goes low being data input D equal to ‘0’. On the other side, when the stage input goes low the set signal is activated and the output goes high. The time for falling and rising delay arcs are as follows:
Q 1 0 D (update) Q-1 (retention) (not applied)
(a) (b) Figure 1. D-type flip-flop with asynchronous set and reset signals: (a) symbol, and (b) truth table.
Considering such behavior, the following analysis can be done for DFFSR in terms of possible output signal transitioning related to a single transition at the input signals (D, Ck, S and R). A positive transition (low-to-high) at the output Q results from the following cases:
• Td_hlStageCkS: falling delay arc from clock to output (Td_hlCk→Q) • Td_lhStageCkS: rising delay arc from set to output (Td_lhSet→Q)
the activation of set signal (S), if the output Q is low and while the asynchronous signal R is deactivated (it does not care about the state of inputs D and Ck); the active edge of clock signal (Ck), if the output Q is low and the input D is high, and when the asynchronous signals (S and R) are deactivated.
As the asynchronous set signal is activated by the logic level value, it has to be deactivated before the next input switching, which corresponds to the action of the clock edge. It is obtained by the additional gate in the stage and can be controlled by the output of such stage, or the next one, in order to avoid eventual flip-flop metastability. Being the next stage of different polarity in the same logic race this control signal must be inverted.
In the same way, a negative transition (high-to-low) at the output Q results only from the activation of the R signal and from a clock activation edge, for certain conditions. Notice
The two other stages, shown in Fig. 1, are based on the same principle of operation. The ‘StageCkR’ represents the following delay arcs:
•
•
43
• Td_hlStageCkR: falling delay arc from reset to output (Td_hlReset→Q) • Td_lhStageCkR: rising delay arc from clock to output (Td_lhCk→Q)
3.2 Circuit The ring oscillator structure requires a negative polarity of the logic path output in respect to the path input signal in order to create the negative feedback of the closed loop, and consequently the condition for signal oscillation at each circuit node. Notice that, in this sense, the ‘Stage_CkS’ is negative unate, while the other two ones present the positive polarity of delay arcs. Hence, the negative feedback can be created by instantiating an odd number of ‘Stage_CkS’, otherwise an inverter gate must be included into the path. Once this requirement is respected, the proposed stages can be instantiated as many times as desired. The impact of each delay arc in the oscillation frequency is directly proportional to the number and type of stages used.
The ‘StageSR’, in turn, represents the following delay arcs for different Ck and D input conditions. That is, four different combinations of these inputs (Ck and D) can be applied in the delay arcs evaluation related to this stage. For instance, considering Ck=0 and D=1, we have: • Td_hlStageSR: falling delay (Td_hlReset→Q/Ck=0/D=1) • Td_lhStageSR: rising delay (Td_lhSet→Q/Ck=0/D=1)
arc
from
reset
to
output
arc
from
set
to
output
Qi (or Qi+1)
S
INi 0
For instance, considering a circuit composed by four stages, as shown in Fig. 3. It comprises one ‘Stage_CkS’, one ‘Stage_CkR’ and the other two ‘Stage_SR’. The period of the oscillating signal is given by:
OUTi (Qi)
D
Q
Ck R
•
0 (a)
or, in terms of delay arcs: •
0 S
1 INi
Period = Td_lhStageCkS + Td_lhStageCkR + 2*Td_lhStageSR + Td_hlStageCkS + Td_hlStageCkR + 2*Td_hlStageSR + Td_lhXOR + Td_hlXOR
Period = 3*Td_lhSet→Q + Td_lhCk→Q + Td_hlCk→Q + 3*Td_hlReset→Q + Td_lhIn→Out + Td_hlIn→Out
OUTi (Qi) Q
D Ck R
Qi (or Qi+1) (b) (a)
INi
S
0/ 1
D
0/ 1
Ck
OUTi (Qi) Q
R
Qi (or Qi+1) (c) Figure 2. Ring oscillator stages using flip-flops: (a) StageCkS; (b) StageCkR; (c) StageSR.
(b) Figure 3. ROS topology: (a) block diagram; (b) waveform.
44
3.3 Initial Condition The initialization of the flip-flop based ring oscillator is simple and several strategies can be applied. The most straghtforward way is to choose the initial condition of one node and initialize the other ones, according to the a stable condition and the ‘inverted/no-inverted’ property of each stage. For that, each stage is slightly modified to add an external signal which forces its set and reset operation. In order to avoid the conflict of the negative feedback at the beginning of circuit operation (in standby state), an exclusive-OR (XOR) gate is added and put to an inversion behavior, as depicted in Fig. 3. Such initialization is determined by an external activation signal (IC). If IC is high the oscillation is stopped, while when it goes low the oscillation starts.
3.4 Operation Modes To demonstrate the self-timed circuit operation, the ring oscillator topology presented in Fig. 4 was simulated through HSPICE. The electrical simulation of the ROS is depicted in Fig. 5, taking into account the PTM 45 nm CMOS process parameters and 1.1V of power supply [16].
Figure 5. Electrical simulations of DFFSR ROS test structure. PTM 45 nm CMOS process parameters were used [16].
0
S 0
D
Q
C
S 1
D
S
q
di
Q
ki
C R
IC
q
R
D
q Q
C R
S di
D
ki
C
q Q
R
IC
Figure 6. DFFSR ROS additional circuitry: register barrier for clocked or step-by-step operation mode. (a)
(b) Figure 4. ROS for DFFSR testing: (a) circuit topology; (b) frequency divider for ‘di’ and ‘ki’ signals generation.
Moreover, the proposed ROS test circuit can be slightly modified to provide a step-by-step or a clocked execution. It is done by just adding a flip-flip barrier (plus a multiplexer for operation mode selection) in the feedback loop, as illustrated in Fig. 6. The behavior of synchronous mode can be seen in Fig. 7, which represents a set of VHDL functional simulations.
Figure 7. Functional simulations of DFFSR ROS controlled by an external clock signal (synchronous operation mode).
45
been done as a prof of concept, as depicted in Fig. 8. However, the results of such comparison will not be discussed here since it is out of the scope of this work.
4. RESULTS In terms of test coverage, two different situations can be analyzed: (1) the expected output transitions according to a signal transition in a single flip-flop input, and (2) the steady state values of the flip-flop inputs and the data stored. The proposed test circuit provides the verification of all these possible static and transitioning situations.
About power consumption analysis, it is interesting to notice that the monitoring of the only two first stages is enough to evaluate and validate the dynamic power dissipation, since all four timing arcs, from asynchronous signals (set and reset) and clock active edge to the output transitions are observed on those. The static power dissipation, in turn, can be measured taking into account only the last two stages, as shown in Table III.
Possible output signal transitions in DFFSR, reviewed in Table I, are identified in different instantiations (circuit stages) during the normal operation of the ROS, as indicated in Table II. It is can be also verified by analyzing the electrical simulations shown in Fig. 5.
Table III. Test coverage of DFFSR steady states considering the ring oscillator circuit stages in Fig. 4(a).
Table II. Possible output transitions in DFFSR considering the ring oscillator circuit stages in Fig. 4(a). Flip-Flop Instantiations 1, 3, 4 3, 4 3, 4 3, 4 3, 4 2, 3, 4 3, 4 3, 4 1 2
S ↑ ↑ ↑ ↑ 0 0 0 0 0 0
R 0 0 0 0 ↑ ↑ ↑ ↑ 0 0
Ck 0 0 1 1 0 0 1 1 ↑ ↑
D 0 1 0 1 0 1 1 1 0 1
Flip-Flop Status Retention Retention Retention Retention Retention Retention Retention Retention Set Set Set Set Reset Reset Reset Reset (not possible) (not possible) (not considered)
Q ↑ ↑ ↑ ↑ ↓ ↓ ↓ ↓ ↓ ↑
The steady states, described in Fig. 1, appear in different cell instantiations at different moments during the ROS operation. The test coverage of the static values that occurs in the cell under test (i.e., DFFSR cell) is indicated in Table III. It is better evaluated taken into account the ROS clocked operation mode, illustrated in Fig. 7. That is the reason in using the two last ring stages because they present different steady states at synchronous (or step-by-step) operation mode. At each duty cycle, the asynchronous set/reset signals of the third stage return to zero due to the update transitioning of the fourth stage output (q4), while one of the asynchronous signals (set or reset) of the fourth stage is kept activated, since their return-to-zero depends on the updating of the first stage output (q1). Observe in Fig. 6 the representation of a ‘delay element’ at the multiplexer output. It suggests the addition of some delay in the feedback loop signal in order to stabilize the updating process of ‘di’ and ‘ki’ signals in the third stage before it receives a new signal oscillating transition. This delay block can be build by a simple chain of inverter gates, and its application may be evaluated for the particular cell under test and the target technology. In terms of performance analysis, it is worth to mention that all timing arcs are deal with in the ROS operating frequency value. Due to this feature, besides the cell delay model verification, already discussed above, the self-timed run of the proposed test circuit becomes quite useful to evaluate and compare different implementations of the same type of flip-flop, as performed in [18]. This kind of analysis has
ROS Stage 3 1,3 2,3 3 1,3 3 3 2,3 4 4 4 4 4 4 4 4 -
S R Ck D Q 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 - - 0 0 1 - - 1 1 1 - - (?)
Figure 8. Electrical simulations of nine different DFFSR topologies [18] using the proposed ring oscillator test structure. PTM 45nm process parameters were used [16].
46
[9] M. K. Reddy and S. M. Reddy, “Detecting FET stuck-open faults in CMOS latches and flip-flops,” IEEE Design & Test, vol. 3, no. 5, Oct. 1986. pp.17-26.
5. CONCLUSIONS We presented a novel ring oscillator structure for test of clocked storage elements (flip-flops). This type of test structure is very promising for: (a) functional test coverage; (b) on silicon delay test and power consumption evaluation; (c) investigation of impact of aging effects (BTI, HCI, TDDB, radiation total dose, and so on); and (d) as a vehicle of comparison of different circuit topologies of the same cell under consideration. The investigation of ROS for other types of latches and flip-flops is in progress.
[10] W. K. Al-Assadi, Y. K. Malaiya, and A. P. Jayasumana, “Faulty behavior of storage elements and its effects on sequential circuits,” IEEE Trans. on VLSI, vol. 1, no. 4, Dec. 1993. pp.446-52. [11] S. R. Makar and E. J. McCluskey, “Checking experiments to test latches,” Proc. of IEEE VLSI Test Symp. (VTS) , pp.196201, 1995. [12] V. H. Champac, A. Zenteno, and J. L. García, “Testing of resistive opens in CMOS latches and flip-flops,” Proc. of IEEE European Test Symp. (ETS), pp.34-40, 2005.
6. ACKNOWLEDGMENTS
[13] L.-S. Kim and R. W. Dutton, “Metastability of CMOS latch / flip-flop,” IEEE J. Solid-State Circuits, vol. 25, no. 4, Aug. 1990. pp.942-51.
Research partially funded by CAPES and CNPq Brazilian agencies. The authors acknowledge UBC and NSERC.
[14] N. Nedovic, W. Walker, and V. G. Oklobdazija, “A test circuit for measurement of clocked storage element characteristics,” IEEE J. Solid-State Circuits, vol. 38, no. 8, Aug. 2004. pp.1294-304.
7. REFERENCES [1] R. Heald et al., “A third generation SPARC V9 microprocessor,” IEEE J. Solid-State Circuits, vol. 35, no. 11, Nov. 2000, pp.1526-38.
[15] T. Iizuka, T. Nakura, and K. Asada, “Buffer-ring-based alldigital on-chip monitor for PMOS and NMOS process variability and aging effects,” Proc. of IEEE Symp. on Design and Diagnostics of Electronic Circuits and Systems (DDECS), pp.167-72, 2010.
[2] W. Agatstein, K. McFaul, and P. Themins, “Validating an ASIC standard cell library,” Proc. of IEEE ASIC Seminar and Exhibit, pp.12/(6.1-6.5), 1990.
[16] Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, “New paradigm of predictive MOSFET and interconnect modeling for early circuit design,” Proc. of IEEE Custom Integrated Circuits Conf. (CICC), pp.201-04, 2000.
[3] J. Xu, R. Kundu, and F. J. Ferguson, “A systematic DFT procedure for library cells,” Proc. of IEEE VLSI Test Symp. (VTS), pp.460-66, 1999. [4] S. Maggioni, A. Veggetti, A. Bogliolo, and L. Croce, “Random sampling for on-chip characterization of standardcell propagation delay,” Proc. of Int’l Symp. on Quality Electronic Design (ISQED), pp.41-45, 2003.
[17] R. Ramanarayanan, N. Vijaykrisgnan, and M. J. Irwin, “Characterizing dynamic and leakage power behavior in flipflops,” Proc. of IEEE Int’l ASIC/SOC Conf., pp.433-37, 2002.
[5] A. Cantoni, J. Walker, and T.-D. Tomlin, “Characterization of a flip-flop metastability measurement method,” IEEE Trans. on Circuits and Systems I, vol. 54, no. 5, May 2007. pp.1032-40.
[18] M. Alioto, E. Consoli, and G. Palumbo, “Flip-flop energy / performance versus clock slope and impact on the clock network design, IEEE Trans. on Circuits and Systems I, vol. 57, no. 6, June 2010. pp.1273-86.
[6] C. Dike and E. Burton, “Miller and noise effects in a synchronizing flip-flop,” IEEE J. Solid-State Circuits, vol. 34, no. 6, June 1999. pp.849-55.
[19] R. P. Ribas, Y. Sun, A. I. Reis, and A. Ivanov, “Selfchecking test circuits for latches and flip-flops,” Proc. of IEEE Int’l On-Line Test Symp. (IOLTS), pp.210-13, 2011.
[7] C. Hess, B. E. Stine, L. H. Weiland, and K. Sawada, “Logic characterization vehicle to determine process variation impact on yield and performance of digital circuits,” Proc. of IEEE Int.’l Conf. on Microelectronic Test Structures, pp.189-96, 2002.
[20] R. P. Ribas, Y. Sun, A. I. Reis, and A. Ivanov, “Ring oscillators for functional and delay test of latches and flipflops,” Proc. of Symp. on Integrated Circuits and Systems Design (SBCCI), pp.67-72, 2011.
[8] J. Keane, X. Wang, D. Persaud, and C. Kim, “An all-in-one silicon odometer for separately monitoring HCI, BTI, and TDDB,” IEEE J. Solid-State Circuits, vol. 45, no. 4, Apr. 2010. pp.817-29.
47
