Phase splitter using digital delay locked loops

US006950487B2

(12) United States Patent Lin et al.

(54)

PHASE SPLITTER USING DIGITAL DELAY LOCKED LOOPS

(75)

Inventors: Feng Lm> 39156’ ID (Us); R- Jacob Baker>Mend1an’ID(US)

(73)

AssigneeZ Micron Technology’ Inc‘, Boise, ID

_

6,011,732 A 6,137,325 A

_

Notice:

1/2000 Harrison et al. 10/2000 Miller, Jr.

6,289,068 B1 *

9/2001

Hassoun et al.

.......... .. 375/376

6,385,126 B2 * 5/2002 Jung et al. ................ .. 365/233 6,445,231 B1 9/2002 Baker et al.

(Us) (*)

US 6,950,487 B2 Sep. 27, 2005

(10) Patent N0.: (45) Date of Patent:

Subject to any disclaimer, the term of this patent is extended or adjusted under 35

6,539,072 B1 *

3/2003 Donnelly et al. ......... .. 375/371

6,777,995 B1

8/2004 Harrison

6,839,860 B2

1/2005 Lin

4 Cited by examiner

U.S.C. 154(b) by 862 days.

(21) Appl. No.: 09/861,121

Primary Examiner—Stephen Chin

(22) Filed,

May 18, 2001

Assistant Examiner—Curtis Odom

(65)

Prior Publication Data

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_

US 2002 0172314 A1 N

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(74) Attorney, Agent, or Firm—SchWegman, Lundberg,

Woessner & Kluth, PA'

. 21 2002

(57)

(51)

/ "V ’ Int. Cl.7 ................................................ .. H03D 3/24

(52)

US. Cl.

A phase

(58)

Field of Search ............................... .. 375/371—376;

receive complementary input clock signals to generate a

327/158

plurality of output signals having different phase shifts.

.................

. . . . . . . . . . . . . . . . . . . ..

375/376

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(56)

ABSTRACT splitter using digital delay

locked loop

(DLL)

When the DLL is locked, the delay resolution of the phase

References Clted

splitter is equal to tWo delay stages of the DLL.

U.S. PATENT DOCUMENTS 5,963,069 A * 10/1999 Jefferson et al. .......... .. 327/158

56 Claims, 10 Drawing Sheets

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Sep. 27,2005

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