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POWER QUALITY ENHANCEMENT OF TIME DEPENDENT INTERHARMONIC LOADS
by A.M.Sharaf **and S.I. Abu-Azab Electrical Engineering Department, United Arab Emirates University P.O. Box 17555, Al-Ain, U.A.E.
[email protected] ** Professor of Electrical Engineering, The university of New Brunswick, P.O.Box 4400/UNB, Fredericton, N. B, Canada, E3B5A3,
[email protected] Keywords: Electric power quality, Switched capacitor compensator, Interharmonics.
Abstract The paper presents a novel switched capacitor compensation scheme (SCC) for power quality enhancement of time dependent loads generating a spectra of interharmonic current components and causing electric supply distortion and power quality problems. The simple parallel capacitor bank is modulated by a novel dynamic tracking regulator to ensure enhanced power quality, reduced supply system harmoincs and an enhanced degree of energy utilization and reduced source energy.
Introduction The mushrooming use of nonlinear electric loads and time varying RL Loads cause severe
harmonic, Power quality degradation, Lower distortion power factor and reduced energy utilization in addition to interference problem. Power supply quality [I-71 issues and persistent problems are a byproduct of the increasing use of solid state switching devices, nonlinear type loads, including switch-mode power supplies, unbalanced power system, lighting controls, computer and data processing equipment as well as industrial plant rectifiers and inverters. These electronic type loads cause quasistatic harmonic dynamic voltage distortions and inrush pulse type current phenomena with excessive harmonic content, high distortion, low power factor and low frequency voltage waveform modulation due to inrush currents, cyclic and acyclic temporal load variations. Power quality problems can cause system equipment malfunction, personal safety risks, shock hazards, voltage flickering, computer data loss and memory malfunctioning of sensitive loads such as computers, banking machine, PLC controls, protection and relaying equipment as well as erratic operation of electronic controls.
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This translates into loss of revenue, power interruptions and electric supply utility reliability and security problems, in addition to extra power and energy losses on utility grid systems. The source of electric load nonlinearity can be analog type (saturation, limiter) or nonlinear voltage-current characteristics, as in distribution transformers and arc type nonsinusoidal loads, or digital type due to point-on-wave or integral-cycle ‘odoff solid state control with switching using transistors, IGBT, MOSFET or GTO devices. And uncommon power terms and currents [8141. Disturbance and voltage flicker [ 13-16] have been major and persistent problems, usually associated with cyclic and acyclic loads with temporal arc type variations, or when starting large (KW) induction motors. Certain types of mechanical loads such as compressors, air conditioning units and reciprocating pumps also introduce this low-frequency (0.5-35 Hz) voltage waveform modulation effect. IEEE defines flicker as the “impression of fluctuations in brightness or color, occumng when the frequency of observed variations lies between a few Hz and the fusion frequency of images”. Some electrical equipment manufactures and power ulilities are utilizing flicker data logging meters and monitoring systems for display, analysis, control and mitigative correction. This paper present a novel modulated power filter scheme for power quality enhancement harmonic compensator and efficient energy utilization.
Sample Study System Figure 1 depicts the sample study system with the time-dependent RL passive (nonlinear) load fed by a sinusoidal AC source. The static capacitor compensation scheme termed (SCC) comprises two capacitor banks, one fixed (CI) and the other one (C2) is switched via
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harmonic reduction utilization.
and
energy -.
efficient
proposed based on waveform (vs, is, p,) transformation as given in the appendix ai d
Figure 1 : Per-phase equivalent system of the sample AC utilization load.
Hannonicreductionloop
BPF
Dynamic current loop Threshold=Th=O.1TNI
Figure 2: Proposed source current based (on/off) switching regulator. Figures 3a, 3b depicts the block diagrams of the Matlab/SIMULINK models utilized in the simulation system, control and capacitor bank data are given in the appendix.
Sample Simulation Results The sample nonlinear RL passive time dependent load fed by an AC sinusoidal source was simulated using the Matlab/SIMULINK software. Figures 4a,b depicts the dynamic voltage, current and power forms for the normal case without the proposed switched capacitor compensator scheme and the novel two-loop controller for linear and nonlinear load. Figures 5a,b shows the dynamic waveforms of voltage, current, power, controller signals with the additional two-stage switched capacitor compensator (SCC) and the two loop dynamic current controller in linear and nonlinear load. The proposed SCC scheme improves both energy utilization via reduction in supply current
shown in figures 4,5.
Conclusions The paper presents a novel low cost parallel capacitor compensation scheme for electric energy utilization scheme employing time dependent loads controlled by a pulse width modulated two loops novel dynamic controller. The scheme can be utilized as a combined efficient energy and power quality device for time dependent RL passive loads and to reduce flickering, harmonic noise and interference in nearby electric loads.
References
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Appendix (a) ACSUPPlY ~ s = m & ~ J ; s i n ( wt), volt, w,=3 14 radsec R,=0.35 R,Ls=5 mH. For linear fixed load WO and a&.
(b) Time dependent load R(t)=R*( 1+a,sin(2nfrt +a,)) L(t)=L*(1+alsin(2nflt +@2)) R=12!2, ~ 1 4 . 6f , ~ Hz, 7 @id6 k . 0 3 H, a ~ 0 . 5f,=7 , Hz, Q&S
(c) Switched capacitor compensator C1=100 VF,+I50
-49T,,=I msec.
(d) Monitoring Relay Transformation vsal=v, cos(2n(7)t)-iSsin(2n(7)t)
isal= v, sin(2n(7)t)+iScos(2n(7)t) psal=pSsin(2*2n(7)t) v~=v,cos(314t)-i,sin(3 1 4 ) i d v, sin(314t)+i,cos(314t) pd=ps sin(2*314t)
(e) Two loop controller PID: kp=25,ki=2.5, k ~ d . 2 5
Loop1 (Harmonic reduction): T1=1/200sec, T2=1/50sec, y d . 2 Ibase==10 A. Loop2 (Dynamic current-energy efficient utilization): T3= 1 115 sec, Delay=20 msec. k=O.1, T,=l msec, Thresholdd.05*TSw
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Sin
U’
Clock
Figure 3a: Matlab/SIMULINK block diagram model without the parallel (SCC) switching-capacitor compensation scheme.
h
+
+ +
m Delay
Controller
* O-Tsw
0
Switch
Figure 3b: MatlabISIMULINK block diagram model with the additional parallel (SCC) switchingcapacitor compensation scheme.
vc
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Figure: vs vs. time
400I
Figure: is vs. time I
40
7
200 9
0
-200 -400 0
0.2
'
-40 0
0.4
Figurgm&(%? time
0.2
I
0.4
Figurgmfi'g'.) time
200 3
0
-200
-400 0
0.2
-40 0
0.4
0.2
time (sec)
time (sec)
Figure: ps vs. pL
Figure: psal vs. time
0.4
8000
6000 E 4000
2000
400
-I
200 100.
200. 01
0-
-
I
0.
-200.
-100.
-400
-200
Figure 4a: Dynamic system response of voltage & current waveforms without the proposed switched capacitor compensation scheme for linear load.
-
52 -
time (sec)
1OTigure: ps vs. pL
-
- 1
0
1 Figure: daf vs.
400I
-I
time (sec)
Figure: psal vs. time
2
'0
isgllo4
0.2
0.4
Figure?%$%.. is&
I
200 N
I
0-200.
'
-400 -500
0 isal
I
500
500 isa2
Figure 4b: Dynamic system response of voltage & current waveforms without the proposed switched capacitor compensation scheme for nonlinear load.
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Figure: is vs. time
Figure: vs vs. time
400I
I
-
-400 0
0.2
0.4
'
-40 0
Figur$m&(%! time
400I
-400 0
0.2
-
-40 0
0.4
Figure: ps vs. pL
0
0.2
0.4
time (sec)
Figure: psal vs. time
15000
2 5000
0.4
I
time (sec)
10000
0.2 Figurgm&(@ time
1
-
0.5
ix,o -0.5 -1
400
-E!
200 0-200. -400
Figure 5a: Dynamic system response of voltage & current waveforms with the additional two-stage switched capacitor compensation scheme for linear load.
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Figure: vs vs. time
Figure: is vs. time -
400
100
200
50
2
"
0
0
-200
0
0
4
-
-50
0
0.2
-100-
0.4
0
Figudm&(%f! time
2
0.2 Figur;mK%?
400
100
200
50 2
0
0.4 time
-
0
-50
-200
' 00 0.2
-400 0
time (sec)
0.4
-1
0
1OFigure: ps vs. pL
0.2
0.4
time (sec)
Figure: psal vs. time
1
2
.-
! l o
g 1
-0.5
0 -1 0 1 400 - 1
0.5
-1
1
2 Figure: &!'I vs. isRllo4
0
0.2 Figure%e&&.
200
0.4 is&
7'
200. .-
P
0-200.
Figure 5b: Dynamic system response of voltage & current waveforms with the additional two-stage switched capacitor compensation scheme for nonlinear load.
