Practical Learnings from EM Simulation for Designing ...

JANUARY 28-31, 2013 SANTA CLARA CONVENTION CENTER

Practical Learnings from EM Simulation for Designing a 25G Serial Channel: Things that Matter the Most Vadim Heyfitch (Avago Technologies, FOPD) Section 14. Signal Propagation Analysis Techniques Wednesday, January 30 9:20-10:00am Ballroom H

Feedthrough impedance vs. pin offset from center

Optimization of via to 25Ω

TOSA45 with Flex or Pins

Optimization of Differential Via geometry PCB Channel performance

Design (Thought) process as a tree Need a void under AC-caps? Can make diff vias smaller to fit better? Do need to backdrill stubs? Do need to length-match intra-pair? What if cannot? Would zigzagging help? Is VendorA connector good enough?

Materials to meet loss budget: 1. Cost; 2. Availability @FabX (QuickTurn, Local) & FabY (HVM, Asia); 3. Lead time 4. Datasheet Dk/Df…. Available? Or do need to characterize? …no time for that…. 5. To ENIG/ENIPIG or SM?

Topics • On “the grinder” approach… • On loss… • On connectors, IC packages, and cables: vet your vendors… • On vias… • On turns and skews… • On voids beneath DC-blocks… • On dispersion as a cause of jitter… • On embellishing the eye by adding loss…

Section 1: On “the grinder” approach… Or do you prefer the term “brute force approach”?

Simulated Schematic

SWEC

Cab

DCon

SWEC HB

Each leg of the diff channel includes: 2 SWECs, 4ft cable, Molex zSFP+ (25G), and 6cm DUT CBCPW on Ro4003CLoPro(RF=2)

Tx channel PRBS13 w/out Jitter: Statistical Channel Sim FFE effect on the eye: reduced jitter

PreCursor: -0.079140 PostCursor: 0.867240, -0.053619

The pudding is in the details… • What is the expected outcome of SI analysis? • What are the details?

Improved EMI Cutouts under DC-blocks give Z~100Ω

PCB Channel performance

4.3dB improvement In Return Loss

The ripple in Return Loss 11.4dB improvement is indicative ofin D->C conversion impedance mismatches Optimized channel should have lower EMI in the channel

CXP_12G_Testboard_B

RX5… good enough @12.5G

The pudding is in the details… • What is the expected outcome of SI analysis? • What are the details?

Decompositional analysis of RX5 signal channel TL1 MPT2 MPT1

TL2 MPT3 TL3

MPT4

TL4 MPT5

MTP2 Diff Insertion Loss (IL): L8 – solid plane vs. void

Solid L8 improves Smm(D1,D2) (insertion loss) some at f>20GHz

MTP2 Diff Return Loss (RL): L8 – solid plane vs. void

Solid L8 improves Smm(D1,D1) (return loss) by 15dB

SMA connector breakout

… another example

Connector

Loopback channel circuit topology with Edge Connector

Host board

Module board

IL & RL w/out and with Connector

Connector

… adding 2 Vias on Module Board

Vias

Host board

Module board

IL & RL w/out and with 2 vias on Module board

Adding the two 95-Ohm vias on module board does not make differential RL or IL much worse.

Loopback Channel Loss vs. Masks (CEI-28G-VSR in oif2012.080.00) SDD11_Mask_CEI-28G-VSR

Channel TDR & eye @25G

OK, we passed the RL mask… Can I equalize this eye? What contributed to the closure anyways? Is it the connector? Can anything be improved further?

Section 2: On loss and corners…

Differential microstrip 8-6-8 mil (w-g-w) 3D View

Top View

Loss comparison: MCL-HE-679G (blue) vs. Ro4350 (green) Material

Loss [dB/in]

MCL-HE-679G (Hitachi)

0.11

Rogers 4350

0.8

Wideband Debye @10GHz

Dk

Df

Thickness [mil]

MCL-HE-679G (Hitachi)

3.9

0.0123

7

Rogers 4350

3.5

0.0037

6.6

Circuit topology: Baseline (no vias or connector model included)

The loss in this model can be equalized. The discontinuities from the two vias and connectors cannot be equalized. The connector is AS-IS (i.e., cannot be improved?). The (differential) via can be optimized to 100Ω. *) Input: 25Gbps PRBS13 with Tr/Tf=12ps.

Section 3: On connectors, IC packages, and cables: vet your vendors…

VendorA connector evaluation IL & RL

TDR with Tr~15ps

Bottom side

Top side

Quality of sNp model: 96.15% (Good), Passivity 99.9978%, Reciprocity 99.61%. Connector quality: Marginal (77Ω-dip)

New Molex zSFP+ vs. Old SFP+: should I buy the latest thing? SWEC+Cab+SWEC+HB+SFP74441(old)

SWEC+Cab+SWEC+HB+zSFP170382(new) No Tx Jitter

What is wrong with Gore measurement of 2ZOAJOAJ0480 cable? S-pars of Gore Cable 2ZOAJOAJ0480

Measured S11/S22 model cannot be Fitted with RCM (Rational Compact Model)

Original Fitted RCM

Gore measurement-based s2p model of 2ZOAJOAJ0480 cable is not usable • Observations – S11 & S22 look like noise – Too few points DC-40GHz range • Phase jumps ~180 degrees between consecutive points • Need 6000 points or more

– Cannot be fitted with RCM (Rational Compact Model)

• Action – Replaced it with ad-hoc representative model with 0.9dB/ft IL (Insertion Loss)

Gore Cable 2ZOAJOAJ0480: Phase jumps ~180 degrees between consecutive points Magnitude

Original Fitted RCM

Original Phase

S11 & S22 are non-causal in Gore s2p measurement of 2ZOAJOAJ0480 cable

CW 0% = non-causal

S-pars of Generic Cable COAX_4ft_1dBat15GHz with IL=0.9 dB/ft at 14GHz

How good is the IC Package someone designed for you?

From Layout -> to Solid Model

2-axis symmetry allows modeling of only the right bottom quarter of the package

TxIN0

Ports

IO1 P01 P02

P03 P04

IO3

IO1

IO4 P05 P06

TxIN4

IO2

P07 P08

IO5

TxIN2 IO3

TxIN0 IO5

BGA Side

TxIN2 Die Side

TxIN4

Circuit connectivity / netlist

J K

IO6 P09 P10

Port[1] = P01_TXIN4n_die Port[2] = P02_TXIN4p_die Port[3] = P03_TXIN4n_K6 Port[4] = P04_TXIN4p_J6

P11 P12 Port[5] = P05_TXIN2n_die Port[6] = P06_TXIN2p_die Port[7] = P07_TXIN2n_K8 Port[8] = P08_TXIN2p_J8

6 IO2

8 IO4

Port[9] = P09_TXIN0n_die Port[10] = P10_TXIN0p_die Port[11] = P11_TXIN0n_K10 Port[12] = P12_TXIN0p_J10

10 IO6

10G: TXIN4 and TXIN0: skew ~1.5ps

10G and 25G super-imposed

Differential IL & RL for all 3 channels: Mixed-Mode (mm) S-parameters

IL

IL

RL

RL IL~0.2dB, and RL~22-24dB at 5GHz RL profile points at Zdm impedance mismatch.

Extra wide void

Initial void

Effect of L2-L4 GND net cutout widening on TDR plots (DM & CM )

Removal of some capacitance to GND brings DD impedance closer to 100Ω but also raises CC impedance (as expected). Page 42 April 2011

Check DC current density on PWR nets

Max is 6.75e7 Amp/m2 43

Section 4: On vias…

Diff Via on 6L board with just 2 planes 25 Drill diameter: 8mil Pad diameter @top/bot (S1/S6): 18mil Drill c2c: 25mil Void diameter: a= ?? mil

7 6 7

a=30mil

6 7

a=40mil

a

Optimal Via: c2c=25mil, void Y=50mil, Stitching Via pads DO NOT encroach on to the void

Perfect geometry

TDR of via with Edge Tr=15ps Optimal via

25 50

a=40mil a=30mil Drill diameter: 8mil Pad diameter @top/bot (S1/S6): 18mil Drill c2c: 25mil Void: Y-size 50 mil, X-size 75mil

Pad-to-pad capacitance may dominate if: 1) few planes & 2) pads hang over void

Try to design 25 Ohm via (Voids D=24, MID2/MID3 Pads D=26, TOP/BOT PadD=25/18mil, distance to stitching via 32mil) Optimization of via to 25Ω

Single-Ended via under SMA on a Test Board

3.5mm SMA Via

SMA (top)

SL (L7)

TDR with Tr/Tf=25ps

SL end

SMA end

300ps 50Ω

SL end

SMA end

300ps 50Ω

The SMA via is too inductive: Z~61Ω. The excessive inductance is closer to the SL end than to the SMA end: δt~20ps.

Optimization reduced RL by about 8.2dB at 5GHz

Dimensions of the Optimized* SMA Via launch for Rx channels ( *Further improvement is possible – if there were more time to do it ) Anti-pad diameter L1: 90mil (unchanged) L2-L5: 69mil (unchanged) L6 & L7: 62mil (changed) L8: 56mil (changed) Pads are 36mil - present on L1, L7, and L8 (unchanged)

TDR blip of the optimized design is smaller peak-to-peak and more centered about 50 Ohm

Differential Via with Stubs

TDT / TDR of MPT2 shows it’s excessively capacitive 0.46

84Ω

84Ω

MPT2 Via performance without NC signal pads: it is still too capacitive: improvement is insufficient!

92Ω

-8dB improvement

84Ω

Optimal Dimensions of MPT2 via MPT2

MPT2

60m il

After much ado, the optimal via geometry is: MID4 is to be 60mil; others 40mil

40m il

Section 5: On turns and skews… Some counterintuitive conclusions

o 90

The turns skew: Need to compensate? MS 8-6-8mil inner radius is 19mil

Questions • Does SE length skew lead to signal skew? • Does x-point shift up/down? • Does jitter arise from skew?

Skew is 22mil

Circuit testbench for

o 2x90

U-turn 22mil skew

100ps

High -18dB D->C through conversion?

100ps

22mil skew

If the U-turn were a straight 12ps ideal delay line...

Noise floor / Baseline

If the U-turn were a straight 82mil line...

RL is up to -40/-50dB

No mode conversion

Circuit testbench for

o 2x90

U-turn 22mil skew

100ps

High -18dB D->C through conversion?

100ps

22mil skew

Short Channel S-pars

+5dB

RL is up to -40/-50dB

No mode conversion Mode conversion just got worse @12.5GHz

TDR: Diff Voltage and Z

Single-Ended TDR/TDR and p/n Skew TDR TDT 6.6ps 16.5% of UI

Length skew DOES NOT result into 1) x-point vertical shift, or 2) jitter

0.17ps

o 90

The turns skew: the takeaway MS 8-6-8mil inner radius is 19mil

Conclusions • Differential signal is quite insensitive to skew – Sub-ps jitter @skew of 16%UI

• High D->C conversion => EMI

Skew is 22mil

Section 6: On voids beneath DC-blocks… How wide? How many plane layers should be voided?

A

B

C

Void on L3 raises RL @5GHz from -47 to -38dB. This is INSIGNIFICANT.

C

A B

TDT / TDR of DC-block & Edge Conn

Section 7: On dispersion as a cause of jitter… The rumor has it that when routing CBCPW one should use the thinnest dielectric possible. Justification is the analogy with a cable: higher diameter cables allow higher modes with different phase velocity => hence timing jitter

Let’s quantify this effect…

SWEC: SouthWest Edge Connector SW 1492-03A-5

@14GHz, IL~0.375 dB, RL~-17dB

SouthWest Edge Connector (7-12-39) Launch including 1cm of Nelco4000-13SI board (Dk=3.7, Df=0.008) with 9 pairs of stitching vias (10-40-5mil diameter-pitch-offset)

CB-CPW (Copper-Backed CoPlanar Waveguide): How to select the right geometry? Periodic 2-cell structure

t

G

W

G H

(H,W,G)=Function(Available_Material(H, Dk, Df, t), Target_Loss, Component_Footprints) VSWR (aka RL) is minimal when H~15mil. [See SW appnotes]. What about dispersion & jitter??

25G Eye through 7cm CB-CPW with Vias on Ro4003C: 8.7mil (red) vs. 16.7mil (blue) Phase Delay dispersion 0.075ps/mm @12.5GHz

Eyes are offset by 5.25ps

Jitter is comparable for both 8.7 and 16.7mil dielectric. What should drive the choice of dielectric thickness?? …. The RL at Edge Connector.

Why do we stitch CBCPW anyway? Not to squash dispersion of the main (propagating) mode – but to suppress undesirable two modes and radiation.

CB-CPW without Stitching Vias on 16.7mil Ro4003C: 7cm Eye after 7cm TLine

Phase Delay [ps/mm]: ~10% dispersion below 50GHz

This dispersion is partially reduced when stitching vias are used (see another slide). Even with this much dispersion, eye diagram shows ~1.25ps jitter.

The addition of stitching vias every 40mil reduces Phase Delay dispersion ~4 times – particularly above 20GHz Eye after 7cm TLine is almost unchanged

Presence of Stitching Via

None Yes: every 40mil

Phase Delay becomes almost linear between 20GHz and 50GHz

Some test results: SFP+32G MCB

TDR (1/2)

SFI to SFP+DUT transition

SFI to SFP+DUT transition

TDR plot above shows a very smooth transition from the RF cable to the PCB Co-Planar Wave Guide on the Eval Board, as well as the transition from PCB to DUT connector. As reference TDR captured from current manufacturing Dual DUT SFP+10Gb/s Eval Board

Section 8: On embellishing the eye by adding loss… The case for circuit optimization

The short channel to DFB laser: Zd=50Ω

Tx1 IC

Tx3 IC Tx2

IC

IC

Tx4

Rx3 Rx2 Rx1

Rx4

Circuit topology of Tx channel 0.1uF DCblock

DFB LD (Zdiff=6.9Ω) TOSA45

10mm of Flex run IC Tx (Zdiff=50Ω or 100Ω)

Not obvious that matching is beneficial at all.

PRBS13: Tx Zdiff=50 Ω, PCB & Flex are 50Ω Diff Rmatch=2 Ω

Rmatch=42 Ω

Matching resistor mainly adds loss at DC and low frequencies thus reducing the ‘1’ (high) and ‘0’ (low) DC level spread / modulation while the Eye height is reduced by very little because the IL at 5.5GHz is barely reduced.

The spread between IL at DC and 5.5GHz determines the amount of level smear (between AC and DC levels of the eye at ‘high’ and ‘low’)

5.5GHz

It is the ripple band of IL from DC to 5.5GHz that determines the amount of level spread / modulation.

TDR of the channel TDR Head Z TOSA 20mm PCB+Flex

Desired / optimal channel impedance profile Z(x) Z(LD)+DC(loss)

Brute force optimization: Variable circuit parameters Optimization variables are: Z1, Z2, and Rmatch The target is to make S21 flat from DC to as high frequency as possible.

Z2 of Flex trace Z1 of of PCB trace

Rmatch Resistor Film inside TOSA

Baseline case (to be compared to): Case 0 (Z1 =25Ω, Z2=25Ω, Rmatch=34 Ω)

Several palatable solutions are found Z(ITL1)

Z(ITL2)

Rmatch

dB loss @5.5GH z

Case 0

25

25

34

-9.72

Case 1 Case 2

26.94 24.34

22.31 26.28

118.3 4.2

-13.6 -7.93

Case 3

19.83

30.22

4.24

-7.66

Case 4

19.83

26.28

138.8

-13.5

Case 5

28.20

34.09

0

-6.18

Case 6

24.00

28.95

14

-8.08

Case 7

28.53

35.63

14

-7.16

Case 8

29.60

37.45

34

-8.49

Case 9

29.34

37.13

34

-8.60

Case 10

25

25

34

-9.82

Case 11

25

25

77

-11.65

Case 12

31.6

43.4

66.9

-10.66

… it could be much worse: Case 5

… or it could be this good: Case 1

Covered Topics • On “the grinder” approach… • On loss… • On connectors, IC packages, and cables: vet your vendors… • On vias… • On turns and skews… • On voids beneath DC-blocks… • On dispersion as a cause of jitter… • On embellishing the eye by adding loss…

Design (Thought) process as a tree Need a void under AC-caps? Can make diff vias smaller to fit better? Do need to backdrill stubs? Do need to length-match intra-pair? What if cannot? Would zigzagging help? Is VendorA connector good enough?

Materials to meet loss budget: 1. Cost; 2. Availability @FabX (QuickTurn, Local) & FabY (HVM, Asia); 3. Lead time 4. Datasheet Dk/Df…. Available? Or do need to characterize? …no time for that…. 5. To ENIG/ENIPIG or SM?

The Upshot #1. Establish a good process to control your fab. Design to mid-tier fab process - for robustness. Do not allow last moment changes by fab. #2. Build SI intuition for reuse.