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Architecture of Xilinx XCR3064XL CPLD ...
Graduate Institute of Electronics Engineering, NTU
CH9 Multiplexers, Decoders, and Programmable Logic Devices Lecturer:吳安宇 教授 Date:2006/11/10 V1.1
ACCESS IC LAB
Graduate Institute of Electronics Engineering, NTU
Outline 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers 9.4 Decoders and Encoders 9.5 Read-Only Memories 9.6 Programmable Logic Devices 9.7 Complex Programmable Logic Devices 9.8 Field Programmable Gate Arrays
pp. 2
Graduate Institute of Electronics Engineering, NTU
Integrated Circuits (IC) Small-Scale Integrated circuit (SSI): Medium-Scale IC (MSI)
Multiplexer Decoder
NOR NAND NOT XOR
Large-Scale IC (LSI) : Arithmetic-Logic Unit (ALU) Very Large-Scale IC (VLSI)
pp. 3
Graduate Institute of Electronics Engineering, NTU
Outline 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers 9.4 Decoders and Encoders 9.5 Read-Only Memories 9.6 Programmable Logic Devices 9.7 Complex Programmable Logic Devices 9.8 Field Programmable Gate Arrays
pp. 4
Graduate Institute of Electronics Engineering, NTU
Multiplexers(1/2)
A B
Z
0 0 1 1
I0 I1 I2 I3
0 1 0 1
I0 I1
Z
I2 I3 A B
pp. 5
Graduate Institute of Electronics Engineering, NTU
Multiplexers(2/2) Z = A’B’I0 + A’BI1 + AB’I2 + ABI3 ( mi : Minterm ) = m0I0 + m1I1 + m2I2 + m3I3 I0 I1 I2
I3 A
z
AND-OR Network
B pp. 6
Graduate Institute of Electronics Engineering, NTU
General 2n-to-1 Multiplexer 2n Data Lines
2 −1 n
2n-to-1 Mux Z
z = ∑mk Ik k =0
n control Inputs
pp. 7
Graduate Institute of Electronics Engineering, NTU
Application: 4-bit Word Selector A
B
A= ( a3a2a1a0 ) B= ( b3b2b1b0 )
sel
Sel
C
0 1
A B
C= ( c3c2c1c0 ) C
sel
a3 b3
a2 b2
a1 b1
a0 b0
2-to-1
2-to-1
2-to-1
2-to-1
c3
c2
c1
c0
pp. 8
Graduate Institute of Electronics Engineering, NTU
Realize Combinational Logic Function
F = A' B'+ AC = A' B'+ AC(B + B' ) = 1⋅ A' B'+ AB' C + ABC+ ( A' B ⋅ 0) 10
00
1 C
I0 I1
0 C
I2 I3 A
11
Z=A’B’+AC
01
AB
Z
00 01 10 11
1 C 0 C
B pp. 9
Graduate Institute of Electronics Engineering, NTU
Ex: Use 8-to-1 Mux to Realize F=A’B’ + AC
AB 00
01 11
CD 00
1
0
1
1
01
1
0
0
0
11
1
1
0
1
10
0
1
1
0
ABC = 000
ABC = 001
10
ABC = 101
D 1 0
1 0
1 D 0 1
I1=D D 0
D’ D
1
1
0
D’ D’
I6=D’
I0 I1 I2 8-to-1 I3 MUX I4
Z
I5 I6 I7 A
B
C
pp. 10
Graduate Institute of Electronics Engineering, NTU
Ex: use 8-to-1 Mux to Realize F(A,B,C,D)
0 1 2 3 4 5 6 7
ABC
Z
000 001 010 011
1 D 0 1
100 101 110 111
D’ D D’ D’
F = A’B’C’ + B’CD + A’BC + A’BC + AC’D’ (From K-map) AB ABC
Z
0 1 2 3
000 001 010 011
C’ 1 C C
4 5 6 7
100 101 110 111
C’ C 1 0
00 CD 00
01 11
10
1
0
1
1
1
0
0
0
1
1
0
1
0
1
1
0
01 11 10
I0=C’ I2=C I4=C’ I6=1
I1=1 I3=C I5=C I7=0 pp. 11
Graduate Institute of Electronics Engineering, NTU
Ex 4-to-1 Mux to Realize F(A,B,C,D) AB
C’ 00
CD
01 11 0
1
10
00
1
01
1
0
0
0
11
1
1
0
1
10
0
1
1
0
I0
D
1
C
C’
I1
Z
I2
D D’
I3
CD
I1
00
1
01
1
11
1
10
0
A B CD
I1
CD
I1
CD
I1
00
0
00
1
00
1
01
0
01
0
01
0
11
1
11
1
11
0
10
1
10
0
10
1
I 0 = (CD ' ) = C '+ D I1 = C I 2 = C ' D'+CD = C '⊕ D I 3 = D' pp. 12
Graduate Institute of Electronics Engineering, NTU
Decoder (MSI)
a b c y0 y1 y2 y3 y4 y5 y6 y7 000 001 010 011 100 101 110 111
1 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0
0 0 1 0 0 0 0 0
0 0 0 1 0 0 0 0
0 0 0 0 1 0 0 0
0 0 0 0 0 1 0 0
0 0 0 0 0 0 1 0
0 0 0 0 0 0 0 1
pp. 13
Graduate Institute of Electronics Engineering, NTU
An n-to-2n decoder generate 2n minterms y y
i
=
i
= (m
m
i
, i = 0 to 2 i
)' =
M
i
n − 1
, i = 0 to 2
(non-Inverted outputs) n − 1
(Inverted outputs)
Using MSI 7442(BCD input decoder)
Ex:
f1 ( a , b, c , d ) = m1 + m2 + m4 = ∑ m (1,2,4) f 2 ( a , b, c, d ) = m4 + m7 + m9 = ∑ m ( 4,7,9) f 1 = ( m 1 '⋅ m 2 '⋅ m 4 ' )'
(NAND)
f 2 = ( m 4 '⋅ m 7 '⋅ m 9 ' )'
(NAND)
M > 10 is not allowed
pp. 14
Graduate Institute of Electronics Engineering, NTU
Realization of a Decoder
(a) Logic Diagram
BCD input
Decimal Output
ABCD
0123456789
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
0111111111 1011111111 1101111111 1110111111 1111011111 1111101111 1111110111 1111111011 1111111101 1111111110 1111111111 1111111111 1111111111 1111111111 1111111111 1111111111
(c) Truth table (b) Block Diagram pp. 15
Graduate Institute of Electronics Engineering, NTU
Design of Two-level Multiple-Output Network
F1 = ∑ m(11,12,13,14,15)
Lost of Network
F2 = ∑ m(3,7,11,12,13,15)
9 gates 21 gate inputs
F3 = ∑ m(3,7,12,13,14,15) AB
AB 00
01 11
10
CD 00
1
CD 00
01
1
01
11
1
10
1
1
11 10
AB 00
01 11
10
1
1
1
00
01 11
1
01 1
11 10
10
1
00
1 1
CD
1
1
1 1
pp. 16
Graduate Institute of Electronics Engineering, NTU
Outline 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers 9.4 Decoders and Encoders 9.5 Read-Only Memories 9.6 Programmable Logic Devices 9.7 Complex Programmable Logic Devices 9.8 Field Programmable Gate Arrays
pp. 17
Graduate Institute of Electronics Engineering, NTU
Three-state Buffer(1/3) F
C
F = C Buffer Gate
F
C Invert pairs
Gate Circuit with added Buffer pp. 18
Graduate Institute of Electronics Engineering, NTU
Three-state Buffer(2/3) 1, C=A B= 0, open CKT (High-impedance)
BA
C
BA
C
BA
C
BA
C
00
Z
00
Z
00
0
00
1
01
Z
01
Z
01
1
01
0
11
1
11
1
11
Z
11
Z
10
1
10
0
10
Z
10
Z
Operations of tri-state buffers
pp. 19
Graduate Institute of Electronics Engineering, NTU
Three-state Buffer(3/3)
S1
x01z
x 0 1 z
xxxx x0x0 xx11 x01z
Output of both Tristate Buffer (B,D are independent)
pp. 20
Graduate Institute of Electronics Engineering, NTU
Application of tri-state buffer Bus structure: Multiple I/O on a Bus for communication
{EnA, EnB, EnC, EnD} should be exclusive ( Only 1 active ) Bi-directional I/O pin Bi-directional means that the same pin can be used as can input pin and as an output pin, but not both at the same time pp. 21
Graduate Institute of Electronics Engineering, NTU
Outline 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers 9.4 Decoders and Encoders 9.5 Read-Only Memories 9.6 Programmable Logic Devices 9.7 Complex Programmable Logic Devices 9.8 Field Programmable Gate Arrays
pp. 22
Graduate Institute of Electronics Engineering, NTU
3-to-8 Decoder a b c y0 y1 y2 y3 y4 y5 y6 y7 000 001 010 011 100 101 110 111
1 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0
0 0 1 0 0 0 0 0
0 0 0 1 0 0 0 0
0 0 0 0 1 0 0 0
0 0 0 0 0 1 0 0
0 0 0 0 0 0 1 0
0 0 0 0 0 0 0 1
Master Binary number (a2a1a0)
Decode 0 Decode 1 Decode 2 Decode 3 Decode 4 Decode 5 Decode 6 Decode 7 pp. 23
Graduate Institute of Electronics Engineering, NTU
Priority Encoders (8-to-3) y0 y1 y2 y3 y4 y5 y6 y7
abcd
0 1 x x x x x x x
0000 0001 0011 0101 0111 1001 1011 1101 1111
0 0 1 x x x x x x
0 0 0 1 x x x x x
0 0 0 0 1 x x x x
0 0 0 0 0 1 x x x
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 x 1 0 x x 1
No signal
happen
Event detect with priority!
pp. 24
Graduate Institute of Electronics Engineering, NTU
Outline 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers 9.4 Decoders and Encoders 9.5 Read-Only Memories 9.6 Programmable Logic Devices 9.7 Complex Programmable Logic Devices 9.8 Field Programmable Gate Arrays
pp. 25
Graduate Institute of Electronics Engineering, NTU
Read-only Memory (ROM) An 8-word x 4-Bit ROM: each word is 4-bit, total 8 words in this ROM
ABC
000 001 010 011 100 101 110 111
Input (ABC)=23 input values (0~7 address) Output(F0 F1 F2 F3 )=(word)
F0 F1 F2 F3
1 1 0 0 1 0 1 0
0 0 1 1 1 0 1 1
1 1 1 0 0 0 1 0
0 0 1 1 0 1 1 1
typical data stored in ROM (2n words of 4 bits each)
pp. 26
Graduate Institute of Electronics Engineering, NTU
Generalized Form ( n-inputs/m-outputs ) n-bit input address
m-bit Output data
00…00 00…01 00…10 00…11
100…110 010…111 101…101 110…010
11…00 11…01 11…10 11…11
001…011 110…110 011…000 111…101
typical data array stored in ROM (2n words, each m-bits)
Size = m x 2n (bits)
pp. 27
Graduate Institute of Electronics Engineering, NTU
Basic ROM Structure (A Decoder + Memory Array)(1/2)
Figure 9-19 Basic ROM Structure
2n entries M output lines
pp. 28
Graduate Institute of Electronics Engineering, NTU
Basic ROM Structure (A Decoder + Memory Array)(2/2) F0 F1 F2 F3
0 1 2 3
1010 1010 0111 0101
4 5 6 7
1100 0001 1111 0101
A ' B ' + AC
'
F 1 = ∑ m ( 2 , 3 , 4 , 6 , 7 ) = B + AC
'
F
0
= ∑ m ( 0 ,1 , 4 , 6 ) =
F
2
= ∑ m ( 0 ,1 , 2 , 6 ) =
A ' B ' + BC
F
3
= ∑ m ( 2 ,3 ,5 ,6 ,7 ) =
AC
'
+ B pp. 29
Graduate Institute of Electronics Engineering, NTU
Contents of ROM specifies a “TRUTH TABLE” Input WXYZ
Hex Digit
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
0 1 2 3 4 5 6 7 8 9 A B C D E F
invert
ASCII Code for Hex Digit A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1
0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1
0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0
Same pp. 30
Graduate Institute of Electronics Engineering, NTU
Outline 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers 9.4 Decoders and Encoders 9.5 Read-Only Memories 9.6 Programmable Logic Devices 9.7 Complex Programmable Logic Devices 9.8 Field Programmable Gate Arrays
pp. 31
Graduate Institute of Electronics Engineering, NTU
Different Types of ROM Mask-programmable ROM(manufactured) Programmable ROM(PROM)-program once Electrically Erasable Programmable ROM(EE-PROM) Programmable
Logic Device (PLD)
N-by-m PLD
pp. 32
Graduate Institute of Electronics Engineering, NTU
Programmable Logic Device (PLD) (1/2) And plane generates minterm (Product terms) OR plane sums the product terms
.
Product Term
Inputs ABC
Outputs F0 F1 F2 F3
A’B’ AC’ B BC’ AC
00 1 -0 - 1 - 1 0 1 - 1
1 1 0 0 0
0 1 1 0 0
1 0 0 1 0
F 0 = A ' B ' + AC ' F1 = AC ' + B F 2 = A ' B ' + BC ' F 3 = B + AC pp. 33
0 0 1 0 1
Graduate Institute of Electronics Engineering, NTU
Programmable Logic Device (PLD) (2/2) f 1 = ∑ m ( 2 , 3 , 5 , 7 , 8 , 9 ,10 ,11 ,13 ,15 ) f 2 = ∑ m ( 2 , 3 , 5 , 6 , 7 ,10 ,11 ,14 ,15 ) f 3 = ∑ m ( 6 , 7 , 8 , 9 ,13 ,14 ,15 )
f 1 = a ' bd + abd + + ab ' c ' + b ' c f 2 = c + a ' bd f 3 = bc + ab ' c ' + abd a’bd abd ab’c’ b’c c bc
abcd
f1 f2 f3
01–1 11–1 100– –01– ––1– –11–
1 1 1 1 0 0
10 01 01 00 10 01
pp. 34
Graduate Institute of Electronics Engineering, NTU
Programmable Array Logic (PAL) (1) Notation
(2) Fixed product terms
pp. 35
Graduate Institute of Electronics Engineering, NTU
PAL : Fixed OR array
pp. 36
Graduate Institute of Electronics Engineering, NTU
Implementation of Full Adder using PAL
X Y Cin
000 001 010 011 100 101 110 111
Sum Cout
0 1 1 0 1 0 0 1
0 0 0 1 0 1 1 1
Sum = X ' Y ' Cin + X ' YCin'+ XY ' Cin'+ XYCin Cout = XCin + YCin + XY pp. 37
Graduate Institute of Electronics Engineering, NTU
Read–only memory AND array
Address inputs
A0 A1
An-1 Device access Control signal (chip select)
y0 y1
x0 x1
Word 0
OR Array
Word 1
n-to-2n Address decoder
xn-1 CS
y2n-1 Word 2n-1 Product terms (minterms)
O1 O2
O3
Data outputs (sum terms)
Mask-programmed ROM Types:
Erasable programmable ROM(EPROM) Electrically erasable programmable ROM EEPROM pp. 38
Graduate Institute of Electronics Engineering, NTU
Programmable Array Logic (PAL)
Progammable array logic (PAL) device
Standard PAL representation pp. 39
Graduate Institute of Electronics Engineering, NTU
Outline 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers 9.4 Decoders and Encoders 9.5 Read-Only Memories 9.6 Programmable Logic Devices 9.7 Complex Programmable Logic Devices 9.8 Field Programmable Gate Arrays
pp. 40
Graduate Institute of Electronics Engineering, NTU
Complex Programmable Logic Device (CPLD) Tools will program for you
Architecture of Xilinx XCR3064XL CPLD pp. 41
Graduate Institute of Electronics Engineering, NTU
CPLD Function Block and Macrocell
(a Simplified Version of XCR3064XL) pp. 42
Graduate Institute of Electronics Engineering, NTU
Outline 9.1 Introduction 9.2 Multiplexers 9.3 Three-State Buffers 9.4 Decoders and Encoders 9.5 Read-Only Memories 9.6 Programmable Logic Devices 9.7 Complex Programmable Logic Devices 9.8 Field Programmable Gate Arrays
pp. 43
Graduate Institute of Electronics Engineering, NTU
Field Programmable Gate Arrays (FPGA)
Layout of a Typical FPGA
pp. 44
Graduate Institute of Electronics Engineering, NTU
Simplified Configurable Logic Block (CLB)
pp. 45
Graduate Institute of Electronics Engineering, NTU
Implementation of a Lookup Table (LUT) abcd
F
0000 0000
0 1
1111
1
pp. 46
Graduate Institute of Electronics Engineering, NTU
Decomposition of switching function Purpose: Reduce input variables f(a,b,c,d)=a’f(b,c,d)+af(b,c,d)=af1+a’f0 Ex: f(a,b,c,d)=c’d’+a’b’c+bcd+ac’ =c’d’(a+a’)+a’b’c+bcd(a+a’)+ac’ =a’(c’d’+b’c+bcd)+a(c’d’+bcd+c’) =a’(c’d’+b’c+cd)+a(c’+bd) =a’f0+af1
pp. 47
Graduate Institute of Electronics Engineering, NTU
K-map approach a=0, f0 = c’d’+b’c+cd a=1, f1 = c’+bd ab cd
a=0
ab 00
01 11
10
cd
00
a=1
01 11
10
00
1
1
1
1
00
1
1
1
1
01
0
0
1
1
01
0
0
1
1
11
1
1
1
0
11
1
1
1
0
10
1
0
0
0
10
1
0
0
0
F
F0
F1
pp. 48
Graduate Institute of Electronics Engineering, NTU
Generalized expression f ( x1 , x2 , L , xi −1 , xi , xi +1 , L , xn ) = xi ' f ( x1 , x2 , L , xi −1 ,0, xi +1 , L , xn ) + xi f ( x1 , x2 , L , xi −1 ,1, xi +1 , L , xn ) = xi ' f 0 + xi f 1 Input variables Reduces from n to (n-1) one function
two functions pp. 49
Graduate Institute of Electronics Engineering, NTU
Ex: 5-variable function f (a, b, c, d , e) = a' f (0, b, c, d , e) + af (1, b, c, d , e) = a'⋅ f0 + a ⋅ f1
Two 4-variable functions + 2-to-1 Mux (controlled by a)
pp. 50
Graduate Institute of Electronics Engineering, NTU
Ex: 6-Variable Function G (a, b, c, d , e, f ) = a ' f (0, b, c, d , e, f ) + af (1, b, c, d , e, f ) = a '⋅G0 + a ⋅ G1
G1 = b' G (1,0, c, d , e, f ) + bG (1,1, c, d , e, f ) = b' G10 + bG11 G0 = b' G (0,0, c, d , e, f ) + bG (0,1, c, d , e, f ) = b' G00 + G01
G = a ' b ' G 00 + a ' bG 01 + ab ' G 10 + abG 11
Four 4-variable functions +3 2-to-1 mux pp. 51