tunneling for Flash memories programming looking for a good tradeoff between ... gramming, ultimately allowing a correspondingly higher degree of parallelism ...
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Pulsed Tunnel Programming of Nonvolatile Memories Fernanda Irrera, Senior Member, IEEE, and Bruno Riccò, Fellow, IEEE
Abstract—This paper investigates the use of Fowler–Nordheim tunneling for Flash memories programming looking for a good tradeoff between applied voltage (to relax requirements for on-chip circuitry), program time and oxide stress-induced leakage current (SILC) degradation. Exploiting the results of a recent study of trap dynamics under pulsed tunnel conditions, it is shown that by means of a small number of relatively high voltage pulses, memories featuring oxide thickness of 7 nm can be programmed in about 20 s with smaller SILC degradation than commonly achieved with programming times in the ms range. Index Terms—Nonvolatile memories, program time, stress-induced leakage current (SILC degradation), tunnel programming.
I. INTRODUCTION
N
ONVOLATILE (NV) memories are important elements of modern microelectronics attracting a strong research effort because of the complex physical mechanisms involved in their operation [1]–[3]. In this context, program throughput (PT), i.e., number of bits that can be written per unit time, is a memory characteristic of particular interest for a number of significant applications. At this regard it is well known that, compared with the alternative method based on channel hot electrons, Fowler–Nordheim (FN) tunneling has a substantial advantage as physical mechanism to inject electrons into the cell floating gate (FG), essentially because of much higher values of the ratio between injection curand total current absorbed by the device during prorent gramming, ultimately allowing a correspondingly higher degree of parallelism (i.e., the number of cells that can be programmed in parallel) that is limited by the total current available from on-chip circuitry. For this reason, in the present paper only tunnel programming is considered, obtained injecting electrons from the channel into the FG of Flash cell transistors by means of a high voltage applied between the source (shorted to the drain and bulk) and control gate (CG) terminals [4], [5]. The result of this operation in the cell threshold voltage , correis a target shift injected into the sponding to a target amount of charge cell FG. Together with the degree of parallelism (not of interest for this of paper), the essential factor for PT is the program time a single cell, and from this point of view tunneling offers an inincreases exponentially with teresting characteristic, in that Manuscript received May 20, 2003; revised September 17, 2003. The review of this paper was arranged by Editor J. Vasi. F. Irrera is with the DIE, Università di Roma “La Sapienza,” Rome, Italy. B. Riccò is with the DEIS, Università di Bologna, Bologna, Italy. Digital Object Identifier 10.1109/TED.2003.820125
the electric field in the tunnel oxide : hence, even small in. creases in the applied voltage produce large decreases in , it has long been believed that For a fixed value of during programming would degrade oxide reincreasing liability, essentially because of stress-induced leakage currents (SILCs), leading to inadequate data retention characteristics. Recently, however, it has been found [6], [7] that this is not the comparable with the time case for (really short) values of needed to create the stable oxide traps responsible for SILC (due to trap-assisted tunneling). In particular, it has been shown that tunnel injection with voltage pulses duration of a few tens of ns allows very high PT with tolerable SILC degradation. On the other hand, programming under such conditions has significant drawbacks, since: a) very high voltages are needed (about 22 V for oxide thickness of 7 nm), with severe implications on technology and circuitry; 2) well formed, high voltage pulses with rising and falling times in the ns range are required, that are difficult to realize with on-chip solutions. In this paper we look for a voltage waveform to be used in , memory programming realising a good tradeoff between applied voltages and oxide degradation. As discussed later, the proposed solution features a small number of relatively high voltage pulses, whose parameters are determined exploiting a recent study on oxide trap dynamics under pulsed tunneling conditions [8], [9]. As for quantitative results, our work indicates that in the case of 7 nm, of about 20 s can be used of oxide thickness of about 18 V applied with minimal oxide degradation and between gate and substrate, i.e., moderately higher than those normally used today for program times in the ms range. This result compares favorably with the most recent data published of 200 s (essentially for the same in the literature featuring ) [10], [11]. value of The paper is organized as follows. In Section II the tradeoff between program time and voltage is discussed; the search for a waveform producing minimum SILC is illustrated Section III; in Section IV the proposed program procedure and the effects on cell reliability are discussed. Finally, conclusions are drawn at the end of the paper. II. TIME AND VOLTAGE TRADEOFF As discussed in [6], [7], [12], the creation of (stable) oxide traps is a physical phenomenon requiring a finite time to be com, that increases with decreasing . Thus oxide plete . SILC degradation can be avoided making (hence ) and For a fixed target value of nm, it has already been shown [6] that tunnel programming in the range of 20 ns is compatible with standard with
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IRRERA AND RICCÒ: PULSED TUNNEL PROGRAMMING OF NONVOLATILE MEMORIES
requirements of data retention. However, very high voltages are required to achieve adequate injection currents and, as already mentioned, this has severe implications on technology and on-chip circuitry. is reduced, decreases exponentially and If must be correspondingly increased, while increases weakly. Thus, in order for the program voltage to remain must be made and SILC adequately constrained, degradation cannot be avoided. In fact, SILC increases for when cell programming is achieved with a decreasing voltage pulse with duration below about 1 s [6]. and , charge On the other hand, for fixed values of injection by means of a number of voltage pulses, rather than with a single and longer one, leads to smaller SILC degradation, because the regime of pulsed tunneling features trap creation but also spontaneous annealing of trap precursors (i.e., oxide damage sites bound to produce stable traps if enough time is allowed for the process to be completed) [8]. From this point of view, in fact, in [8] it has been shown exceeds a limiting that when the time-between pulses , all trap precursors revert to a normal state not convalue tributing to SILC degradation: thus for minimum program time should be made (about) equal to and oxide degradation, (to be determined by means of suitable experiments). Therefore, this paper considers memory programming under pulsed tunneling conditions and program waveform is essentially studied with respect to the following parameters: number , duration of each of them, and of voltage pulses (conveniently replacing because externally controllable). III. MEMORY PROGRAMMING
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3) A significant fraction of newly created states is annealed out during the time between two pulses (these evidently not yet stable traps have been called trap precursors). 4) Such a fraction increases with the time between pulses until exceeds , beyond which a final, time-independent number of stable traps is reached (saturation of SILC). was in the order of some microseconds in all The value of will be the experiments, and for this reason in this paper fixed at 10 s. Of course, in order to reduce SILC not only the amount of created stable traps should be reduced, but the degree of precursor annealing should be maximized. In order to develop a methodology aimed at minimizing oxide damage under pulsed tunneling conditions an analytical description accounting for all main physical mechanisms of interest (creation of stable traps and precursors, precursors annealing, and conversion of residual ones into stable traps) represents a useful starting point. To this purpose, the following equation links (for the same ) the density of traps created by a pulsed fixed value of and and dc stress (these values are indicated as , respectively) (1) represents the fraction of trap presursors annealed where is the fraction of at the end of the pulse, hence residual precursors which do not anneal and finally become stable traps. Using the model of [13] holding for dc stress, (1) can be written as
A. Oxide Damage Modeling In practice, the parameters mentioned just above (not inand determine the dependent of one another, since amount of charge transferred to the FG with each voltage pulse, is given by the number of voltage pulses needed while ) can be determined exploiting to achieve the required the results of a recent study on trap dynamics under pulsed tunneling conditions [8] with the purpose of minimizing oxide degradation and program time. In [8] oxide degradation under pulsed tunneling conditions in MOS capacitors fabricated with the same technology as the Flash cells of this paper has been studied and the main results relevant for the problem at hand are briefly summarized below for completeness. Trains of pulses were applied to the devices, exploring wide and (from a nanoseconds to miranges of values of (above 10 MV/cm). The number of pulses croseconds) and C/cm (the same was always adjusted to inject value of interest in this paper). The obtained results clearly indicate that a reduction of SILC of several orders of magnitude can be achieved using a train of short pulses instead of a single longer pulse of the same amplitude. In particular, the following was shown. 1) (As expected) new traps are created during each voltage pulse. (for 2) The concentration of such traps decreases with and ). fixed
(2) has been written as in order to where stress its dependence on pulse parameters. Furthermore: A, B, are constants, and L is the scattering length of free elecand trons in the oxide. has been derived from meaIn this paper, the value of surements with the following procedure. The SILC current was V) after dc and pulsed tunmeasured at a fixed bias ( . neling programming, in both cases for the same value of and , These two currents are here denoted respectively. Then (3) The experimental results also show the following way:
to depend on
in (4)
is a constant to be determined fitting measured where was fixed data, as for example illustrated in Fig. 1, where s, in this case). In this way, it was found to 10 s ( than 0.75 for ns. In [8] it was shown that
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Because of (5), hereafter in all parameter dependences will . be replaced with (the more convenient external quantity) plane, identifies a line representing On the all possible combinations of voltages and duration achieving , and, as can be seen in Fig. 2, the crucial point the target exhibits a is that along such lines the function (broad) minimum, clearly corresponding to minimum SILC degradation. Such a behavior is essentially due to the fact that, with respect is increased the increase of the term to the minimum, if representing trap creation dominates on the decrease of that describing precursor annealing, while the opposite is true if becomes smaller. Since the program duration is given by (7) Fig. 1. Trap annealing percentage as a function of pulse time duration. 11 MV/cm, the continuous Symbols are measured data obtained with F line represents the exponential interpolation.
=
that the timescale for precursors annealing is rather insensitive to the amplitude of the external perturbation originating them; is infor this reason, in our calculations we assumed that . dependent on B. Minimum SILC Degradation The model of (1)–(3) can be calibrated to accurately reproduce experimental data and represents the basis for the optimization of the waveform used for memory programming. To this purpose, an extensive set of experiments has been performed using MOS capacitors fabricated by STMicroelectronics, Agrate Brianza, Italy (with the same technology, hence the same oxides, as the NV cells to be considered later), that allow accurate characterization of SILC by means of direct current measurements. (2) was used to calculate that, in turn, represented the input of the inelastic trap-assisted-tunnel model [14]. The correctness of the model was already demonstrated in [8] interpolating SILC data with calculated curves. In order to make use of (2), at first order we assume to be constant throughout the whole programming procedure. This assumption clearly represents an approximation, since the oxide field is affected by the injected charge, hence it changes from one pulse to the next one as well as within the same pulse. However, the assumption is convenient here and its validity in the case of interest will be verified at the end of our calculation. Under the condition of constant field: a) in the case of can be simply expressed in terms of the memory cells, external voltage as (5) is the coupling coefficient between CG and FG, where is applied between gate and source (shorted to substrate and is the Flat Band voltage of the cell transistor; drain), while is simply given by b) the charge injected with each pulse (6)
s, we are where, for the reasons already given, . interested only in small values of 1.5 V The main results of Fig. 2, illustrates that for C/cm ) a minimum of (hence corresponds to the following set of parameters: 333 ns, V. s, a value well below Consequently, (7) gives those recently reported in the literature [10], [11]. That the assumption of constant oxide field during programming made above do not substantially affect the validity of our conclusions can be verified in two different ways: a) Fig. 2 clearly shows that in the region around their minimum, (hence, also the curves exhibit a weak dependence on ), and no significant difference would be found if the on dynamic variations of the oxide field during programming were accounted for; b) the results illustrated in Section IV-A indicate that the programming procedure developed here achieves , thus implicitly confirming the substantial the correct quantitative correctness of our calculation. IV. EXPERIMENTAL RESULTS A. Program Accuracy Flash cells fabricated with the same technology as the capacitors of [8] have been used for experiments of memory programafter UV-erase is 2.3 V, with an intrinsic spread of ming. is 1.5 about 0.35 V, while, as already mentioned, the target C/cm ). As for , the V (corresponding to 18 V determined in the previous section have been obtained biV asing the source (shorted to drain and bulk) with V. Therefore, the cells have been programmed and with the waveform defined in the previous section, featuring: V, V, ns, s (giving s). The particular share of the bias between substrate and CG was made purely on the basis of experimental set-up convenience, and does not affect our predictions since the voltage drop (and oxide field) is the same as in theoretical calculations. Erase has been done as in standard operation, applying a 1-ms V and V. long pulse featuring The complete write/erase (W/E) waveform is depicted in Fig. 3.
IRRERA AND RICCÒ: PULSED TUNNEL PROGRAMMING OF NONVOLATILE MEMORIES
Fig. 2.
Q
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Density of created traps during FN tunnel programming vs. program voltage and pulse duration for C/cm .
= 10
Fig. 3. W/E waveform applied to the CG (top) and to drain, source and substrate (bottom). Time duration were, respectively, 333 ns, 10 s, and 1 ms.
A set of memory cells has been programmed and erased with a few cycles using the waveform of Fig. 3 and the obis 1.5 V with distribution of the tained medium value of which reproduces the same 0.35 V spread as programmed in the UV-erased case. Furthermore, a few write/erase cycles value (always have been also performed varying only the s), and it was verified that V. B. Endurance The impact of precursors annealing on memory reliability has been investigated performing 10 program cycles with waveforms different from that described in the previous Section (which has been varied in the range only for the value of 0.4–20 s). versus reported in Fig. 4 with The obtained data of closed symbols clearly show that, apart from the known intrinsic
N
=2, 3, and 4, for a target 1V =1.5 V and
(t ), time between pulses (t
) and erase time
spread of values, only when s cycling has no effect . on the time between one pulse and the next one For shorter is not sufficient for the precursors created during the former one to completely anneal out before the beginning of the latter, thus confirming the results obtained with the capacitors mentioned in Section III. In Fig. 4, values of the program voltage shift of the same samples before cycling are also shown (open symbols), in order to demonstrate that the behavior found after cycling is not due to characteristics of the fresh samples, but only to the duration . of The reproducibility of this result has been verified on a wide set of samples, all subject to 10 cycling with the “optimized” s), confirming that the medium value waveform ( was 1.5 V with a spread of the distribution of the measured of 0.175 V.
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Fig. 4. Program voltage shift measured on several samples using the waveform after 10 cycles (closed circles) and of Fig. 3 featuring different values of t just a few cycles (open circles).
Fig. 5. Change of the program voltage V measured after four months retention (in the programmed state) with respect to the value measured soon after cycling.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 12, DECEMBER 2003
Fig. 6. Experimental SILC data after dc stress (crosses) and stress obtained with the “optimized” waveform (diamonds) for the same injected charge (0.3 C/cm ); simulations (solid lines) are obtained with the voltage-controlled current generator used in the lumped element model of the Flash cell of [15]. 8.15 V, V 35 ms. Here, V
=
=
Fig. 7. Variation of the voltage window of cycled Flash memory cells in the case of “optimized” pulsed FN tunnel programming (solid line) and dc FN tunnel programming (dashed line).
C. Data Retention of cycled At this regard, in the programmed state samples has been measured four months after the stress, having left the memory cells in the programmed state (resulting in an average oxide field of 4.6 MV/cm). Results indicate that such values are approximately the same as measured just after the stress in the most cells. This is illustrated in Fig. 5, showing that 14 of the 17 measured cells did not exhibit any change (or at least the change was smaller than 50 mV, which is the sensitivity of our instrument). The percentage of unaffected cells is good and compatible with standard case, however the statistic is extremely poor and any further comment on this is probably meaningless. As far as SILC is concerned, the effects on cell data retention must be evaluated but, in our case, this cannot be done experimentally because the instrumentation needed to this purpose is not available.
Therefore, we have replaced measurements with appropriate modeling, based on a recent paper by Larcher et al. [15] that allows to calculate cell data retention starting from SILC characteristics. The compact, lumped element model of the memory cell introduced in [15] features a voltage-controlled current generator between FG and substrate based on an analytical expression of SILC given by trap-assisted tunneling, that must be properly calibrated to achieve adequate accuracy. To this purpose, pulsedstress experiments have been performed on the capacitors described in Section 3 applying the same waveform of the programming procedure proposed in this paper (the voltage applied to the ca). The total injected pacitor gate is directly compared with C/cm as in the case of cycled Flash cells. charge was SILC has been then measured on the stressed capacitors and experimental data (shown in Fig. 6 with diamonds) have been interpolated by the analytical expression of trap-assisted tun-
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TABLE I POSSIBILE COMBINATIONS OF THE THREE PARAMETERS (N ; V ; t ) CHARACTERIZING THE WAVEFORM UNDER STUDY, IN THE CASE t = 10 s AND Q = 10 C/cm . THE QUANTITY N th=1 REPRESENTS THE PERCENTAGE OF THE CHARGE INJECTED WITH THE LAST RESPECT TO THE FIRST PULSE
neling [14], in order to calibrate the model for the devices at hand. In the same Figure, data of SILC after dc stress are also displayed (crosses) and interpolated with the same model. Fig. 6 clearly indicates the excellent accuracy of the calibrated model (continuous lines). Starting from the obtained expression of the voltage controlled SILC generator, the model has then been used to calculate the charge loss of Flash memory cells after cycling with the waveform proposed in this paper. The result is shown in Fig. 7 with solid line. As can be seen, the variation of the threshold window after ten years and 10 W/E cycles is 0.65 V, a value less than 30% of the UV erase voltage. This represents an excellent result, particularly compared with the effects of conventional programming schemes (using long times and relatively low voltages) as can be easily seen in Fig. 7, where the dashed line represents data relative to dc FN programming obtained with a single 35 ms-long and 8.15 V-high pulse, injecting a charge of 0.3 C/cm . Although extensive experiments for assessing cell reliability should be done (in particular to improve the statistical significance of the data and check the effect of temperature), our results clearly indicate that the program waveform of this paper does not significantly degrade the reliability compared with the much longer procedure normally used to-day. D. Injection Efficiency As mentioned at the end of Section III-B, because of the properties of the function be minimized [given in (2)] the procedure of this work achieves sufficient accuracy in spite of the fact that it has been derived making use of the assumption of constant injection condition during programming. Nevertheless, it is interesting to study in details how electron injection changes from one tunneling pulse to the other. after each pulse has been measured To this purpose, s, under the following programming conditions: s, 18 V. The results featured: 0.65, 0.5, and 0.4 V after the first, the second, and the third pulse, respectively (for a total threshold voltage shift of 1.55 V).
The decrease of (average) voltage drop across the oxide during the second and third pulse (compared to the first one) is 0.27 V (1.5% of 18 V) and 0.19 V (1% of 17.73 V), respectively. Furthermore, several different waveforms have been also considered, keeping constant the target . Table I shows results relative to twelve waveforms, with and V. The first row of each between of the twelve boxes represents the ratio and the first pulse. As can be seen, the charge injected in it is not convenient to increase the number of pulses above 4, V, since this ratio becomes smaller especially for than 50%, clearly indicating a strong decrease of injection efficiency of the last pulses. V. CONCLUSION In this paper, Flash memory programming by means of FN tunneling (from the cell channel) has been studied with the aim of minimizing SILC oxide degradation and, at the same time: a) limiting the program voltage in order to soften technology requirements; b) reducing the program time. In this sense, the goal was the synthesis of a program procedure realizing a good tradeoff among conflicting needs. The paper has shown that a waveform composed of a (small) number of (relatively) high voltage pulses represents the optimum solution, because the absence of applied field in the period between pulses allows spontaneous annealing of oxide stressed states that would evolve in stable traps contributing to SILC. The parameters of the voltage waveform used in memory programming (pulse height and duration, as well as the time between pulses) have been determined using a model of oxide trap dynamics, verified by means of experiments on capacitors fabricated with the same technology as the Flash cells of interest. By means of such a model it has been shown that, in the region of voltage and time of interest, trap creation exhibits a minimum corresponding to optimum program conditions. The identified program procedure has been validated by means of measurements on Flash cells showing that, compared with commonly used program conditions, it performs better as
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far as memory reliability is concerned, while strongly reducing program time. In particular, it has been shown that cycling has negligible effects. The results of this paper are important from the point of view of applications because they indicate that Flash memories can be programmed in about 20 s, with voltages only slightly higher than those used to-day for operation in the ms range. Thus, they clearly indicate that substantial improvements in Program Throughput can be achieved with the same technologies already in use today. ACKNOWLEDGMENT The authors wish to thank STMicroelectronics for fabricating the devices used in this paper. They are also indebted with Dr. T. Fristachi for technical support and Dr. L. Larcher for help in data retention calculations.
[15] L. Larcher, S. Bertolu, and P. Pavan, “SILC effects on E PROM memory cell reliability,” IEEE Trans. Device Mater. Reliab., pp. 13–18, Mar. 2002.
Fernanda Irrera (SM’84) was born in 1959. She started her career working on integrated optics and fiber optics working with Alcatel. In 1989, she joined the Electronics Department, University “La Sapienza,” Rome, Italy, where she was involved in research on amorphous silicon-based electronic devices. She is now an Associate Professor of electronics there, working on reliability issues in CMOS technology and nonvolatile memory devices. She is coauthor of approximately 80 papers published either in international journals or conference proceedings, and holds two international patents. Dr. Irrera won a national prize in 1995 for science and technology for the invention of a voltage-controlled three-color detectors.
REFERENCES [1] P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, Flash Memories. Norwell, MA: Kluwer, 1999. [2] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells—An overview,” Proc. IEEE, pp. 1248–1271, 1997. [3] S. Lai, “Flash memories: Where we were and where we are going,” in IEDM Tech. Dig., 1998, pp. 971–973. [4] S. Kobayashi, M. Mihara, Y. Miyawaki, M. Ishii, T. Futatsuya, A. Hosogane, A. Ohba, Y. Terada, N. Ajika, Y. Kunori, K. Yuzuriha, M. Hatanaka, H. Miyoshi, T. Yoshihara, Y. Uji, A. Matsuo, Y. Taniguchi, and Y. Kiguchi, “A 3.3 V only 16 Mb DINOR flash memory,” in ISCC Tech. Dig., 1995, pp. 122–125. [5] N. Tsuji, N. Ajika, N. Yuzuriha, Y. Kinori, M. Hatanaka, and H. Miyoshi, “New erase sheme for DINOR flash memory enhancing erase/write cycling endurance characteristics,” in IEDM Tech. Dig., 1996, pp. 181–183. [6] B. Riccò and A. Pieracci, “Tunneling bursts for negligible SILC degradation,” IEEE Trans. Electron Devices, vol. 46, pp. 1497–1500, July 1999. [7] R. Versari, A. Pieracci, and B. Riccò, “Fast programming/erasing of thinoxide EEPROMS,” IEEE Trans. Electron Devices, vol. 48, pp. 817–819, Apr. 2001. [8] F. Irrera and B. Riccò, “SILC dynamics in thermal oxides under pulsed stress,” IEEE Trans. Electron Devices, vol. 49, pp. 1729–1735, Oct. 2002. [9] R. Feruglio, F. Irrera, and B. Riccò, “Microscopic aspects of defect generation in SiO ,” Microelectron. Rel., vol. 42, pp. 1427–1432, Oct. 2002. [10] D.-C. Kim et al., “A 2 Gb NAND flash memory with 0.044 mm2 cell size using 90 nm flash technology,” in IEDM Tech. Dig., pp. 919–922. [11] J.-D. Choi et al., “A 0.15 mm NAND flash technology with 0.11 mm2 cell size for 1 Gbit flash memory,” in IEDM Tech. Dig., 2000, pp. 767–770. [12] R. Versari, A. Pieracci, D. Morigi, and B. Riccò, “Fast tunneling programming of nonvolatile memories,” IEEE Trans. Electron Devices, vol. 47, pp. 1297–99, June 2000. [13] F. Irrera, “Degradation kinetics of thermal oxides,” Appl. Phys. Lett., vol. 79, pp. 182–84, July 2001. [14] B. Riccò, G. Gozzi, and M. Lanzoni, “Modeling and simulation of stress induced leakage current in ultra-thin SiO2 films,” IEEE Trans. Electron Devices, vol. 45, pp. 1554–60, July 1998.
Bruno Riccò (SM’91–F’03) was born in Parma, Italy, on February 8, 1947. He received the degree in electrical engineering at the University of Bologna, Italy, in 1971, and in 1975, received the Ph.D. degree from the University of Cambridge, U.K. In 1980, he became Full Professor of applied electronics at the University of Padua, Italy, and in 1983, he joined the University of Bologna, Italy. Since 1978, he has been holding courses on electron devices, digital integrated electronics, semiconductor technology, and IC reliability and testing. He has been Visiting Professor at the University of Stanford, CA, at the IBM T. J. Watson Research Center, Yorktown Heights, NY, and at the University of Washington, Seattle, WA. He has consulted for major semiconductor companies and for the Commission of the European Union in the definition, evaluation, and review of research projects in microelectronics. He has worked in the field of solid-state devices and ICs. In particular, he has made many contributions to the understanding and modeling of electron transport, tunneling in thin insulating films, silicon dioxide physics, MOSFETs physics, latchup in CMOS structures, device modeling, and simulation. He is currently working in the field of IC design, evaluation, and testing. He is author or coauthor of over 300 publications (more than half of which have been published in major international journals), three books, and six patents in the field of nonvolatile memories. Dr. Riccò received the G. Marconi Award in 1995 from the Italian Association of Electrical and Electronics Engineers (AEI) for his research in electronics. From 1986 to 1996, he was European Editor of the IEEE TRANSACTIONS ON ELECTRON DEVICES. In 1996, he became President of the Group of Electron Devices, Technologies and Circuits of AEI and in 1998, became President of the Italian Group of Electronics Engineers. In 1999, he was appointed European representative for the International Electron Device Meeting (IEDM). In 1999, he founded the first university spin-off in Italy working in the field of advanced digital systems. In 2002, he was elected Chairman of the IEEE North Italy Section.
