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Reg. No. : M.E. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2010. Second Semester. VLSI Design. VL 9221 — CAD FOR VLSI CIRCUITS. ( Common to ...
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Reg. No. :

Question Paper Code : 98079

M.E. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2010 Second Semester VLSI Design

VL 9221 — CAD FOR VLSI CIRCUITS (Common to M.E. Applied Electronics) (Regulation 2009) Time : Three hours

Maximum : 100 Marks

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Answer ALL questions

PART A — (10 × 2 = 20 Marks) Differentiate DFS and BFS search methods.

2.

How the problems are classified based on the complexity?

3.

What are the different metrics used to estimate the wire length?

4.

How cells are placed in quadrature placement method?

5.

Draw the slicing tree for the given floor plan shown in Fig. 1

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1.

7 5 4

1 2 3 Fig. 1

How routing is performed in standard cell layout?

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6.

5

6

7.

Draw ROBDD for f = ab( c + d ) .

8.

How the signal, gate and delays are modeled for gate level simulation?

9.

Draw a DFG for the code given below :

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If en = 1 then temp = count + 1 else temp = count – 1 end if. 10.

Mention any two scheduling algorithms used in high level synthesis. PART B — (5 × 16 = 80 Marks) (a)

(i)

Using Prim's algorithm find minimum spanning tree for the graph shown in Fig. 2. (10)

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11.

Find the shortest path between ‘B’ and ‘F’ in the graph shown in Fig. 3 using Dijkstra's algorithm.

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(ii)

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Fig. 2

Or

(i)

Discuss on the VLSI Design methodologies used for IC layout design. (12)

(ii)

Draw the Gajski Y-chart.

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(b)

Fig. 3

2

(4)

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(a)

Explain how Kernighan-Lin algorithm is used for partitioning and using the algorithm, find the minimum cut for the graph shown in Fig. 4

Fig. 4 Or (b)

What are the objectives of placement? Discuss any two algorithms used for placement of cells in IC layout.

(a)

(i)

Discuss the optimization issues related to floor planning.

(ii)

Explain Maze routing algorithm.

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13.

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12.

(10) (6)

Or

14.

(a)

(i)

What are shape functions? How it helps in floor plan sizing?

(ii)

Explain left edge algorithm with an example.

(6) (10)

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(b)

How transistor is modeled by Bryant and the simulation is performed at switch level? Or

15.

(b)

Explain how ROBDD is used in logic synthesis.

(a)

Describe the Allocation and Assignment in high level synthesis. Or

Explain the Hardware models and High level transformation in High level synthesis. ———————————

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5

(b)

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