Proceedings of the 3rd Annual IEEE Conference on Automation Science and Engineering Scottsdale, AZ, USA, Sept 22-25, 2007
TuRP-B03.2
Queue time and x-factor characteristics for semiconductor manufacturing with small lot sizes Kilian Schmidt (AMD), Oliver Rose (TUD) 1
Abstract— Small lot size is widely regarded as a promising means to achieve shorter cycle times in semiconductor manufacturing. The dominant contributor to cycle time is queue time. In this paper, we quantify how the queue time changes with lot size reductions by means of queuing theory and single-operation simulation. This includes an analysis of the factors shaping this queue time change and how their influence changes for different availability characteristics. Additionally, the x-factor changes resulting from the changes in queue time and raw process time are outlined.
I. INTRODUCTION
S
MALL lot size has been identified by several IC manufacturers as a potential architectural shift to drive down cycle time (e.g. [1]). Limited simulation work on this change has been done by Wakabayashi et al [10], but a solid analytical background on the expected queue time reduction is still missing. This paper aims at closing this gap and will outline which queue time and x-factor changes can be expected for smaller lot sizes. In the literature, there are a few papers that provide some background material. In [7], we analyzed the mandatory characteristics of models of raw processes for small lot sizes. Ref. [8] includes a high-level application of these models for a semiconductor fab. In [9], we analyzed changes of raw process time (RPT) and queue time (QT) changes for priority lots. As priority lots normally bypass the queue and are instantly processed on an available tool, their analysis is comparably easy because the corrupting influence of variability can be ignored. The opposite is the case for normal lots. Queue time is the dominant share of normal lot cycle time and its amount is considerably influenced by variability. Therefore, the change of variability that goes hand in hand with the lot size change is an important part of this paper’s analysis. This paper is organized as follows. Section II illustrates the problem in detail. The theoretical discussion is given in Section III while Section IV discusses experimental approaches and results. Section V focuses on the
consequences that follow for x-factor changes. Section VI summarizes the paper. II. PROBLEM ILLUSTRATION Fig. 1 illustrates the problem analyzed in this paper. The cycle time that lots spent at a particular operation is divided into queue time and raw process time. In Ref. [7] we showed how raw process time changes for smaller lot sizes, therefore we now turn to the next step, the analysis of queue time changes. In the illustration, we further divided the raw process time into processing t0 and a delay d because this simplifies the queue time analysis. The processing time t0 is given as t0 = n ×
(1)
with n denoting the lot size and PR denoting the wafer process rate. The delay d is caused by the overlapping processing of consecutive lots and is often referred to as first wafer delay. Definition of first wafer delay is not uniform throughout the industry mainly as a consequence of different raw process time definitions. Slightly simplified we think of it as the time necessary to transport a wafer from the carrier to the actual process location and back into the carrier after processing. Universally valid it can be defined as d = RPT − t0 ,
(2)
such that all other formulas for different tool types or accuracy levels can be derived from the RPT formulas and definition generated in [7].
Manuscript received July 31st, 2007. Kilian Schmidt is with AMD Saxony LLC & Co. KG, Wilschdorfer Landstraße 101, MS I11-IE, D-01109 Dresden (phone: +49-351-277-3118; fax: +49-351-277-93118; email:
[email protected]). Oliver Rose is with the Institute of Applied Computer Science, Dresden University of Technology.
1-4244-1154-8/07/$25.00 ©2007 IEEE.
1 , PR
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Queue Time 25 wafer lot
Queue QT ?
Raw Process Time Delay d
Processing t0
50%. However, current availability characteristics will mostly lead to a smaller reduction. We also showed that variability not only drives queueing time in general, it also corrupts the effectiveness of the lot size reduction. The less variability in a system, the higher the relative queueing time improvement is for lot size reductions. Therefore variability reductions remain a key contributor to cycle time reduction efforts in the semiconductor industry that can be leveraged with lot size reduction. Furthermore we pointed out that for lot size reductions xfactor changes are possible in both directions depending on variability of the equipment and the size of the delay d. Further research will analyze the queueing time reduction based on the switch from batch to mini-batch or single wafer tools. Additionally, we will analyze how the results presented within this paper hold within a fab simulation model. ACKNOWLEDGMENT The authors thank AMD’s Industrial Engineering Department for their helpful contributions. Special thanks go to Andreas Kirchberg for his valuable suggestions. REFERENCES [1]
O. Bonnin, D. Mercier, D. Levy, M. Henry, I. Pouilloux, E. Mastromatteo. Single-Wafer/Mini-Batch Approach for Fast Cycle Time in Advanced 300-mm Fab. IEEE Transactions on Semiconductor Manufacturing, Vol. 16, No. 2, pp. 111-120, 2000. [2] O. J. Boxma, J. W. Cohen and N. Haffels. Approximations of the mean waiting time in an M/G/s Queueing System. Operations Research 27, pp. 1115-1127, 1979. [3] D. Gross and C. M. Harris. The fundamentals of queueing theory. John Wiley & Sons, Inc. 3rd edition, 1998. [4] F. Hillier and G. Lieberman. Introduction to Operations Research, McGraw Hill Inc., 2004. [5] W.J. Hopp and M.L. Spearman. Factory Physics. McGraw Hill Inc., 2000. [6] J. K. Robinson. The P-K Formula at http://www.fabtime.com/ [7] K. Schmidt, O. Rose and J. Weigang. Modeling Semiconductor Tools for small lot size fab simulations, Wintersim Conference, 2006. [8] K. Schmidt and O. Rose. Development and simulation assessment of semiconductor fab architectures for fast cycle times, Ph.D Colloquium of the Simulation and Visualization Conference, Magdeburg, 2007. [9] K. Schmidt. Improving priority lot cycle times, ASMC 2007 [10] T. Wakabayashi, S. Watanabe, Y. Kobayashi, T. Okabe, A. Koike. High-speed AMHS and its operation method for 300mm QTAT fab, IEEE Transactions on Semiconductor Manufacturing, Vol. 17, No. 3, pp. 25-28, 2004. [11] W. Whitt. Approximating the GI/G/m Queue. Production and Operations Management 2, pp. 114 –161, 1993.
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