E-T Based Statistical Modeling and Compact Statistical Circuit Simulation Methodologies
James C. Chen, Chenming Hu, C.-P. (Dan) Wan*, Peter Bendix*, and Ashok Kapoor* Dept. of EECS, University of California Berkeley, 211-37 Cory Hall #1772, Berkeley, CA 94720-1772, FAX: (510) 642-2759, Phone: (510) 642-8861, Email:
[email protected] *LSI Logic Corporation, Milpitas, CA 95035
Abstract A new statistical parameter extraction methodology which translates actual process variations into SPICE model parameter variations is presented. This methodology uses E-T data to extract SPICE model parameters and guarantees that its extraction results match measured variations. We have applied this methodology to an industrial 0.5µm process. Excellent, overall I-V curve fit for multiple device geometries is achieved. A compact statistical circuit design technology that improves upon the typical/worst/best case methodology is also presented. I. Introduction There is very little doubt that accurate representations of process variations for circuit design is an important modeling concern. Slightly less clear, however, is the method by which this is best achieved. Many past efforts can be grouped into two parts: those which focus on mixing and matching Electrical Test parameters at “process corners” [1], and those which find justification in randomly generated, statistical parameter distributions [2,3]. The fundamental problem for both methodologies is their inability to guarantee that the final extracted SPICE model parameters are indeed an accurate reflection of real device behaviors. For example, it is usually known that the former yields overly pessimistic and/or overly optimistic results. Likewise, there is no reassurance that the latter approach randomly selects SPICE model parameter values which produce I-V curves that actually match those measured from silicon. The new methodology set forth in this paper, E-T Based Statistical Modeling (EBSM), not only alleviates the shortcomings of the former two methodologies, but
also guarantees that its extracted SPICE parameter sets match measured device performance variations. These extracted files are then used for Compact Statistical Circuit Simulation (CSCS), this paper’s second methodology, for efficient simulation of large circuits and accurate prediction of performance distributions. II. Methodology Figure 1 illustrates the basic idea of EBSM. From a nominal die, one SPICE model file is extracted for a group of devices. This step involves the traditional use of a SPICE model parameter extractor. The extracted parameters are then grouped into two parts: those which are assumed to vary between different die locations and those which do not (fixed at extracted nominal values). For the former SPICE parameters, E-T data are either used as their direct replacements or as inputs into calculations that yield their corresponding values. This procedure is repeated for all dies of interest. Nominal .Model File SPICE parameters which vary from die to die SPICE parameters fixed at extracted nominal values
E-T Data
.Model Files
E-T Data Used as Direct Replacements E-T Data Used for Model Parameter Calculations
SPICE parameters which vary according to E-T Data
Model Equations Solver
SPICE parameters fixed at extracted nominal values
Figure 1. Illustration of E-T Based Statistical Modeling Methodology.
This work is supported under SRC contract number 96SJ-417 0-7803-3393-4/96/$5.00 (c) 1996 IEEE
BSIM3v3 SPICE Parameters for the Following Speed Percentiles Calculated NMOS BSIM3v3 Parameter
NMOS E-T Data Used for Calculation
Mean
Sigma
(fast) 2%
10%
25%
50%
75%
90%
(slow) 98%
Vth0
Vth (20µ µm/20µ µm)
0.5839
0.00848
0.5472
0.5712
0.5803
0.5859
0.5894
0.5826
0.5870
Nlx (x10-7)
Vth (20µ µm/1µ µm)
1.958
0.1193
1.817
2.110
1.923
1.966
2.068
1.913
1.965
Dvt1
Vth (20µ µm/0.6µ µm)
0.3526
0.03425
0.4441
0.3638
0.3812
0.3320
0.3311
0.2971
0.3416
Dvt0
Vth (20µ µm/0.5µ µm)
3.528
0.7705
6.515
3.875
4.295
2.895
2.795
2.325
3.545
K3
Vth (5µ µm/0.5µ µm)
25.47
15.05
111.756
44.636
36.056
21.356
6.586
23.996
26.666
Dvt0w
Vth (1µ µm/0.5µ µm)
0.4423
0.4976
2.409
1.371
0.965
0.244
-0.404
0.317
0.490
U0
Idsat (20µ µm/20µ µm)
340.6
4.279
340.2
349.7
350.5
342.7
337.1
337.2
339.3
Vsat
Idsat (20µ µm/0.5µ µ m)
142100
12460
148570
121090
127960
145280
159930
145590
143590
Dwg (x10-9)
Idsat (1µ µ m/0.5µ µm)
-8.006
6.383
1.119
-0.991
-1.472
-0.442
-0.766
-0.597
-0.901
Table 1. NMOS E-T data used to calculate NMOS BSIM3v3 model parameters. Similar calculations were performed for PMOS transistors. Percentile columns represent 7 SPICE files which can be used for statistical circuit simulations.
Using E-T data as direct replacements for SPICE model parameters is relatively straightforward. Many SPICE models, such as BSIM3 Version 3 (BSIM3v3) [4], do have parameters with physical interpretations (i.e. Tox, ∆L, ∆W, Nch, and Rds). However, to ensure the methodology actually produces parameters that reflect I-V characteristics more accurately, other electrical parameters from the E-T database such as Idsat (saturation current) can be used to calculate other SPICE model parameters. This calculation amounts to solving the BSIM3v3 current expression. For example, an E-T measured Idsat value can be inserted on the left hand side of the current expression. The BSIM3v3 SPICE current expression with the specific model parameter of unknown value is on the right hand side. Once a solution is found, the calculated SPICE model parameter value will guarantee the simulated Idsat value at that bias condition will be equal to the measured value. This idea can be extended to calculate other SPICE model parameters. There is flexibility in deciding which electrically measured E-T parameters are used in the calculation of other SPICE model parameters. However, special attention should be paid to the fact that different SPICE model parameters are more sensitive to particular E-T data at certain bias points than others.
Figure 2. Comparison of the 95th percentile and 5th percentile measured current characteristics for W/ L=20µ µm/0.5µ µm. III. Application and Results E-T Based Statistical Modeling was used to model device performance variations (Figure 2) for an experimental, industrial 0.5µm process. Five E-T data (Tox, ∆L, ∆W, γ1, Rds) were used as direct replacements for BSIM3v3 model parameters. In additional, 9 electrical E-T data were chosen to ensure accurate modeling of threshold voltage and saturation current. These are listed in Table 1 and were used to calculate 9 NMOS BSIM3v3 parameters. PMOS parameters were similarly calculated. This process was repeated for 220 dies from 5 wafers and 2 lots. The average time spent was
0-7803-3393-4/96/$5.00 (c) 1996 IEEE
30 seconds per die. Figures 3 and 4 show a comparison between simulated and E-T measured threshold voltages as functions of Ldrawn and Wdrawn, respectively.
Figure 5. Comparison between simulated (solid line) and measured (markers) 95th percentile drain current characteristics. The RMS error is 4.76%. Figure 3. Comparison between simulated (solid line) versus measured (markers) threshold voltage characteristics for three different dies as a function Ldrawn.
The distribution of one calculated BSIM3v3 parameter is shown in Figure 6. To assess overall I-V curve fit, the RMS Error percentage is calculated between measured and simulated Id-Vd curves for all dies. A distributive nature is observed (Figure 7). The results are summarized in Table 2 and display excellent fit for all device geometries and both MOS channel types. IV. Discussion The total number of extracted SPICE files is only limited by the number of available E-T data sets. These extracted SPICE files can then be used immediately (or after Principal Component transformation) for Compact Statistical Circuit Simulation (CSCS), the second proposed methodology of this paper.
Figure 4. Comparison between simulated (solid line) versus measured (markers) threshold voltage characteristics for three different dies as a function of Wdrawn. Figure 5 shows simulated versus measured drain current characteristics for the 95th percentile (or highest 5%) current characteristics for the W/L=20µm/0.5µm NMOS transistor. The RMS error is 4.76%. Excellent agreement was also observed (RMS error of 4.31%) for the 5th percentile (or lowest 5%) drain current characteristics. These observations illustrate the ability of E-T Based Statistical Modeling methodology to model a wide variety of process induced device performance variations.
Figure 6. Results from E-T Based Modeling calculation of one SPICE BSIM3v3 model parameter, µ0. Wafer to wafer and lot to lot variation can be readily seen.
0-7803-3393-4/96/$5.00 (c) 1996 IEEE
In order to avoid repetitive simulation of large circuits, representative smaller digital circuits are simulated for all 220 extracted SPICE files. The basis for this efficient methodology is that all digital gates (e.g. inverter, NAND, NOR, etc.) speeds are all highly correlated with one another [5]. Since these smaller circuit blocks comprise the larger circuit; “worst”, “best”, or other percentile case files corresponding to these smaller circuits can be said to correspond to similar performance of the larger circuits. As an example, an inverter was simulated 220 times and the SPICE model files corresponding to seven specific delay percentiles were then retained (Table 1). These were then used for seven simulations of a 4-bit adder. The results are compared (Figure 8) against actual 4-bit adder simulations from all 220 extracted SPICE files. The agreement is good and shows that accurate speed distributions can be efficiently determined.
98th Percentile Delay Worst 2% SPICE File 2nd Percentile Delay Best 2% SPICE File
Delay (Identical Scale) Figure 8. Actual simulated density (220 simulations) of a 4-bit adder is compared with that predicted from just seven simulations. The latter used SPICE files generated from seven specific delay percentiles of a smaller logic circuit. Excellent quantitative agreement is observed. V. Conclusion New methodologies for statistical parameter extraction and statistical circuit simulation are presented. The methodologies use Electrical Test data to directly generate SPICE model parameter sets. This process is fast and guarantees accurate representation of drain current. Once SPICE model files are generated, an efficient simulation strategy circumvents repetitive simulation of large circuits to produce accurate distribution of circuit speeds.
Figure 7. Distribution of Id-Vd RMS error percentages for NMOS W/L=20µ µm/0.5µ µm transistors. Device
Mean (%) Sigma (%)
NMOS: W/L=20µ µm/20µ µm
1.6813
0.1311
NMOS: W/L=20µ µm/0.5µ µm
4.8086
0.9804
NMOS: W/L=1µ µm/0.5µ µm
4.4581
2.1461
PMOS: W/L=20µ µm/20µ µm
4.9612
1.7780
PMOS: W/L=20µ µm/0.5µ µm
4.4868
2.3991
PMOS: W/L=1µ µm/0.5µ µm
6.4220
2.6335
Table 2. Summary of Id-Vd RMS Error percentages for various devices. Low values for the mean and sigma are observed for all device geometries
VI. References [1] R. Rios, N.D. Arora, C.-L. Huang, N. Khalil, J. Faricelli, and L. Gruber, “A Physical Compact MOSFET Model, Including Quantum Mechanical Effects for Statistical Circuit Design Applications”, Proc. IEDM 1995, pp. 937-940. [2] J. Power, B. Donnellan, A. Mathewson, and W. A. Lane, ”Relating Statistical MOSFET Model Parameter Variabilities to IC Manufacturing Process Fluctuations Enabling Realistic Worst Case Design”, IEEE Trans on Semiconductor Manufacturing, Aug. 1994, pp. 306-318. [3] M.J. van Dort and D.B. Klassen, “Circuit Sensitivity Analysis in Terms of Process Parameters,” Proc. IEDM 1995, pp. 941-944. [4] BSIM3 Version 3 Users Manual. [5] J. C. Chen, C. Hu, Z. Liu, P.K. Ko, “Realistic Worst-Case SPICE File Extraction Using BSIM3”, Proc. CICC 1995, pp.375-378.
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