Jia-Liang Chiou Han-Chia Cheng. Department of Electrical Engineering. National Tsing-Hua University, Taiwan. Abstract. VDD. We address in this paper the ...
Modeling and Testing of Intra-Cell Bridging Defects Using Butterfly Structure Lu-Yen Ko
Shi-Yu Huang Jia-Liang Chiou Han-Chia Cheng Department of Electrical Engineering National Tsing-Hua University, Taiwan
Abstract We address in this paper the defect modeling and testing of intra-cell bridging defects from the layout perspective. For defect modeling, we incorporate a butterfly structure to resolve the potential non-logical effect a bridging defect may cause. By doing so, a realistic Boolean fault model at the gate level can thus be generated for each defect under consideration. Furthermore, the test vectors can be generated by a formulation on top of existing ATPG tools. Experimental results indicate that simple stuck-at test set can only achieve 85% coverage for intra-cell bridging defects for ISCAS85. The proposed systematic flow can further boost it to
1.
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logic-level
layout-based higher
defect coverage Fig. 1: A potential paradigm shift to layout-based testing.
99%F.
It is quite often that a bridging defect inside a cell could fighting condition, i.e., multiple signals could drive a cell's output, with some of them to Vdd and the others to GND. The resulting voltage of the output signal could be non-logical, instead of a logic level. The fighting conditions will become harder to resolve with the shrink of the supply voltage and the noise margins of the logic signals. In this work, we present a layout-based test methodology for defects occurring inside a cell. There are three major steps in this methodology: defect analysis, defect modeling, and test generation. In defect analysis, we take the layout of the circuit under test (CUD) in GDS format and decide the top two most likely bridging defects based on critical area analysis [5][12]. For each defect, we use a defect modeling procedure to convert its behavior as faithfully as possible into a Boolean fault model based on exhaustive quick SPICE simulation. Finally, we invoke an ATPG tool to generate deterministic patterns for each undetected defect based on a formulation to be proposed. Such a layout-based approach has been pioneered by many other researchers [6][7][8][17][20]. As compared to their works, the contributions made in this work are mainly in two aspects: (1) We propose a scheme called butterfly structure to resolve the ambiguous voltage level inside a faulty cell, and (2) We derive a systematicformulation for generating vectors for any defect modeled as a gate-level sub-circuit. 2. Defect Analysis In this work, we follow the popular critical area concept [5] [12] to decide the top 2 most likely defects.
Introduction Test set quality has long been assessed by the stuck-at fault coverage. However, this metric is getting more and more challenged. Evidence shows that 100% stuck-at fault coverage may not be adequate to catch a high percentage of real physical defects. In response to this problem, a number of new test generation methods have been proposed. N-detection is a direct enhancement of existing ATPG tools [10][13][15]. For each stuck-at fault, multiple test vectors, instead of just one, are generated. The strategy is to generate a large number of high-quality test vectors with good fault propagation capability, and hopefully a lot defects can thus be detected. More recently, fault diagnosis based on N-detection test set has also been studied [19]. For interconnection faults, N-detection seems to be quite satisfactory. However, there is no clear guidance as for detecting defects inside logic cells. In some sense, it is more like a semi-random approach, and thus the overall defect coverage can only be achieved at the cost of a large number of test vectors. In addition, it is often not easy to decide how big the parameter N in this N-detection methodology should be for a circuit under test. On the other hand, the defect-based testing (DBT) has also been touted as another promising solution, marking a potential paradigm shift to the transistor-level or even the layout-level testing as illustrated in Fig. 1 [2][3][10][11][2 1]. In a DBT methodology, the most important task is the defect modeling - an activity to answer where the most likely defects are and what their resulting behaviors will be. For the first question, the critical area concept [5] has been popularly used. It iS based on the analysis of the layout for identifying the most likely spots for bridging faults. Using this concept, a number of enhancement techniques have been proposed to model the defects at the layout level, or even at the schematic level [6][7] [8][12][14][16][17][18] [20][21].
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2.1DftAnlssFo The overall flow is depicted in Fig. 3. A given circuit layout is first parsed into a number of cell layouts. A cell layout is further decomposed into polygons of a number of layers. Polygons with connections (by overlapping or via) are grouped into logical nets. Then the minimum distance of
1
every two nets is estimated to determine the probability of bridging defects. Once the two most likely locations are identified, a short conducting segment is inserted into the layout to mimic the defect as illustrated in Fig. 2. At the end of this flow, totally 2n faulty cell layouts are generated, where n is the total number of cells in the circuit. In this work, we pick only two defects. However, more defects can be selected if necessary. layout of Into cells & polyns =itcllt ihddf teln L by
logic '1' or logic '0' differently by its fanout cells easily, a so-called Byzantine effect [9]. Defet Modeling 3 The defect modeling process is to abstract the behavior of a defect into the logic domain. For a given defect, the entire modeling flow is shown in Fig. 4. A
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Fig. 2: The defect analysis flow.
The inputs include the circuit netlist, the layout of each cell, and a specific defect. As mentioned previously, we perform 2. 2 Defect Classification the defect injection, which adds one conducting segment into the target cell's layout to mimic the defect. Then, we start a During the above defect analysis flow, we can also four-step procedure, including (1) Butterfly structure produce the statistics about the defect types. identification, (2) faulty layout construction, (3) faulty Each net is first categorized as one of five types: input, schematic extraction, and (4) exhasutive SPICE simulation. output, internal, Vdd, or GND. The bridging of the five basic * (Step 1): The butterfly structure identification finds a subtypes gives rise to 13 defect types, including 10 of them circuit from the netlist so that the non-logical effect can be between different net types (e.g., a bridging between input resolved. This identification rule will be demonstrated by and internal), and 3 of them between the same type (i.e., an example later. input-input, output-output, internal_internal). D * (Step 2): After we have identified the bufferfly structure, DD we construct its corresponding faulty layout by direct replacement, i.e., we replace each cell in the butterfly structure by its corresponding layout. A- BH D * (Step 3): Faulty schematic extraction is then performed on o 1n 1 i1 the faulty layout by a commercial tool. The result is a SPICE file with detailed parasitic RC's. If necessary, the S (CouldAbe be ambiguous)... igu ) A interconnection models among cells can be included at Input ul Cthis stage.
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simulator on the faulty schematic is performed to construct the truth table of the Boolean fault model of the defect under consideration. The Boolean fault model is then converted to a logic circuit. Next, we use an example to illustrate the butterfly strucutre identification process. Example 2: Given a logic circuit as shown in Fig. 5(b), with five inputs {XI, X2, X3, X4, X5} and one output {z1}. There are six logic cells in this circuit with their output signals denoted as {a, b, c, d, e, J}, respectively. Suppose that the cell generating signalf is a faulty cell, with an input-to-input type of bridging defect. Fighting condition could cause ambiguity at signals c and d. These two ambiguous (or potentially nonlogical) signals are marked in bold lines. To resolve the ambiguity, we trace back from signals c and d towards the primary inputs by one level, reaching signals {a, b, X4}.
Internal_internal
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Fig. 3: Examples of defect types in NAND4.
Example 1: Two examples of defect types for 4-input NAND cell are shown in Fig. 3, namely, input internal and internal_internal bridging defects. For these two types, nonlogical effect will arise. Take the input_input one for example. When the input vector is {(A, B, C, D) (1,1,0,1)}, there will two driving paths, one to Vdd through the pull-up pMOS, while the other to ground through the pull-down nMOS, leading to a fighting condition. Under such a condition, the voltage level of the output signal Out could be non-logical. This non-logical level could be interpreted as
2
These three signals are included as the pseudo-inputs of our butterfly structure. Then, we trace forward towards to the primary outputs from signals c and d by one level, reaching signals {e, J3. These two signals form the pseudo-outputs of our butterfly structure. The resulting sub-circuit is called a butterfly structure because of its outlook as illustrated in Fig. 5(a). Pseudo
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_ Case 1: The detection is made via single fault effect propagation through signal e, as shown in Fig. 6. In this ecase, the function of a is denoted as:
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circuit). In this example, the outputs of the butterfly subcircuits are denoted as {e,j}, and those of the fault model are {e', f'}. These four signals are fed to a Fault Activation Circuit (FAC), driving signal a. In this miter, we aim to translate the detection conditions into a stuck-at-O fault. The FAC circuit, depending on the number of outputs in the Boolean fault model and on how we want to propagate a fault effect to the primary outputs, could split into multiple forms. We consider the cases when there are two outputs as
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, where -= is an equilvalence operator. It mandates that the values of signal e and e' should be different, and those of signal f and f' should be the same in order to force a '1' at signal a. Also, signal a is used to replace signal e as shown in Fig. 6. It can be proved that an input vector for detecting a stuck-at-0 fault can differentiate the behaviors of the butterfly sub-circuit and the Boolean fault model at signals e and e' and this difference can be further propagated to some primary outputs. * Case 2: The detection is made via single fault effect propagation through signal f In this case, the function of a is denoted as: a= (f e f) (e _ e a P ) Also, signal a is used to replace signalf * Case 3: The detection is made via double fault effect propagation through signals e and f in the same polarity. In this case, the function of a is denoted as: ao= (e e e') * (f e f') Also, signal a is used to replace both signals e and f, as shown in Fig. 7(a).
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defect_________________ (b) Example circuit. Fig. 5: The butterfly structure for defect modeling.
Test Generation The previous section implies that we can mostly find a Boolean fault model for a defect, by enlarging the sub-circuit under consideration marginally to a butterfly sub-circuit. Once a Boolean fault model is built, the subsequent test generation can be solved in a number of different ways as proposed in the literature [4] [11] [21 ]. In our system, we incorporate a piggyback program on top of a commercial tool for this purpose. One major feature of this formulation is that it can be adapted to handle a Boolean fault model with multiple outputs, if necessary. This formulation was inspired by the original work in [1] for circuit verification. For a given Boolean fault model as a logic sub-circuit, we construct a model called miter [1]. The conditions for detecting a target defect is transformed to the detection conditions for a stuck-at-0 fault of a signal in this miter, named signal a. 4.
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FAC: fault activation circuit FAC function: a= (e e') (fflPf)
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In general, this formulation can be extended to the case when there are n (n > 2) outputs in the Boolean fault model. But due to the lack of space, the extension is ommitted. 5. Experimental Results We have implemented the proposed methodology as a system for PSC 0.25um technology in C and Perl 5.8. This system invokes NanoSim for quick SPICE simulation, StartRC for post-layout SPICE netlist generation, and TetraMax for test vector generation. We have conducted experiments on all ISCAS'85 circuits. Table 1 shows the defect coverage improved by our method and the required CPU time. The meanings of some columns are explained in the following: * vector: means the number of test vectors generated by TetraMax, either using traditional stuck-at fault model or
further push it up to 99%. Acknowledgements The authors would like to thank PowerChip Semiconductor Corp. and Syntronix Corp. for their supports in providing the standard cell library in the experiments of this work. References [1] D. Brand, "Verify Large Synthesized Designs," Proc. of Int'l Conference on Computer-AidedDesign, pp. 534-537, Nov. 1993. A. and M. [2] J.Observation, Dworak, D.andDorsey, ELF-MD:Wang, Criteria"Excitation, for High Optimization Mercer,
[3]
our methodology.
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generation.
On the average, the defect coverage has been improved from 84.63% (by suck-at fault test set) to almost 99.03% by our methodology. On the average, the total number of test vectors increases from 50 to 148.
[7]
C17 6 4 C432 175 45 C499 370 61 C1355 302 45 C1908 465 29 C2670 694 66 82 C3540 1020 C53151462064 C5315 1462 64 C6288 2353 38 C7552 2114 61 Avg. ____ 49.5
defect cover.
cover.4 100%o
82.9% 99.5% 89.3% 83.2% 86.3% 64.9°/o 83.
83.4%o
94.6%
77.9%o 84.6%o
vector
4 128 126
defect cover.
10000
99.98% 100% II 1 OOO 67 100% 241 97.17% 231 98.82% 191 98.19%o 81 100% 297 98.13°/ Avg. 147.7 99.2%o
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Table 1: Results for ISCAS-85 circuits. traditional ours vector
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* defect cover.: stands for defect coverage of a given test set. * model time: means the CPU time in second for defect modeling, including the quick SPICE simulation. * ATPG time: means the CPU time in second for defect coverage computation and the subsequent test vector
circuit gates
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477
Conclusion With the supply voltage and the noise margin getting smaller and smaller and the defects becoming more and more ambiguous, the traditional stuck-at fault testing may not be adequate to guarantee the quality of an IC. To cope with this 6.
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new challenge, the defect-based testing could provide an
alternative solution in addition to the N-detection methodology. In this paper, we presented a complete defectbased test methodology with two major contributions: Firstly, we incorporate an automatic procedure to convert a defect into an equivalent sub-circuit at the logic domain based on a butterfly structure. Secondly, we formulate the defect detecionequiemens as numer o stuk-at aultdetetion problems that can be directly solved by existing ATPG
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and S.
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programs. Experimental results indicate that traditional stuck-at fault test set can only detect around 850% of those
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