APPLIED PHYSICS LETTERS 97, 143108 共2010兲
Radial junction silicon wire array solar cells fabricated by gold-catalyzed vapor-liquid-solid growth Chito E. Kendrick,1 Heayong P. Yoon,2 Yu A. Yuwen,2 Greg D. Barber,3 Haoting Shen,1 Thomas E. Mallouk,3 Elizabeth C. Dickey, Theresa S. Mayer,2 and Joan M. Redwing1,2,a兲 1
Department of Materials Science and Engineering, The Pennsylvania State University, University Park, Pennsylvania 16802, USA 2 Department of Electrical Engineering, The Pennsylvania State University, University Park, Pennsylvania 16802, USA 3 Department of Chemistry, The Pennsylvania State University, University Park, Pennsylvania 16802, USA
共Received 26 July 2010; accepted 13 September 2010; published online 5 October 2010兲 The fabrication of radial junction silicon 共Si兲 solar cells using Si wire arrays grown by Au-catalyzed vapor-liquid-solid growth on patterned Si substrates was demonstrated. An important step in the fabrication process is the repeated thermal oxidation and oxide etching of the Si wire arrays. The oxidation cleaning process removes residual catalyst material from the wire tips and exposes additional Au embedded in the material. Using this cleaning process and junction formation through POCl3 thermal diffusion, rectifying p-n junctions were obtained that exhibited an efficiency of 2.3% and open circuit voltages up to 0.5 V under Air Mass 1.5G illumination. © 2010 American Institute of Physics. 关doi:10.1063/1.3496044兴 Radial junction Si wire arrays are being pursued as an alternative device geometry to reduce the cost of crystalline Si photovoltaics 共PV兲. These structures consist of a high density array of Si wires1,2 with diameters ranging from approximately 50 nm to 10 m with a radial p-n junction formed on the outer periphery of the wires. As described by Kayes et al.,2 the high aspect ratio radial p-n junction wire geometry enables a decoupling of the direction of light absorption from that of carrier collection. Maximum efficiencies are predicted for devices in which the radius of the wire is approximately equal to the minority carrier diffusion length,3 which therefore provides a pathway to improve the efficiency of solar cells fabricated using lower purity Si. The wire array geometry also offers unique light trapping advantages that enables both reduced reflectivity and enhanced absorption.4 Our recent studies of n + / p+ Si pillar array solar cells fabricated by deep reactive ion etching 共DRIE兲 demonstrate enhanced conversion efficiencies compared to planar devices due to the combined effects of a shorter carrier collection length and multiple reflections within the structure.5 From a practical perspective, the efficiency advantage of the radial junction wire array geometry is only compelling if it enables a reduction in solar cell material and/or fabrication costs. Several techniques are currently being pursued for Si wire array fabrication including the bottom-up vapor-liquidsolid 共VLS兲 growth technique6–10 and top-down wet etching approaches.11 In the VLS process, a metal particle 共typically Au兲 is used to promote the axial growth of Si microwires/ nanowires from a Si-containing source gas such as silane 共SiH4兲 共Ref. 12兲 or silicon tetrachloride 共SiCl4兲.13 The use of Au as the catalyst is a particular concern because Au is a deep level trap in Si and at high enough concentrations 共⬎1013 cm−3兲 will lead to a reduction in the efficiency of planar Si solar cells.14 While Au has been found to incorporate within the bulk of the Si nanowires at moderate levels during VLS growth,15 several studies have demonstrated that a兲
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significant Au diffusion occurs along the outer surface of the nanowires during growth and subsequent cooling.16,17 Consequently, the density of Au-related electronic states is expected to be highest near the surface of VLS-grown Si wires. Radial junction solar cells fabricated using Au-catalyzed Si nanowire arrays and single nanowires have thus far all reported low open circuit voltages 共Voc兲 of 130–300 mV,7,8,11,18 suggesting that residual Au impurities may be negatively impacting the performance of the devices. In this study, radial junction Si wire array solar cells were fabricated on p+ Si substrates using Au-catalyzed VLS growth and the effects of surface cleaning on the dark and light current-voltage characteristics of the devices were investigated. The results offer important insights into the impact of residual impurities on the performance of PV devices fabricated with VLS-grown material. The radial junction solar cells fabricated in this study used p + 共⬎0.005 ⍀ cm, 2 ⫻ 1019 cm−3兲 具111典 Si wafers as the starting substrate. The wafers were then thermally oxidized to form a 300 nm thick SiO2 layer that was patterned with a hexagonal array of holes with diameters of 5 m and a pitch of 7 m. The hole pattern was transferred to the SiO2 by reactive ion etching. The patterned wafers were then coated with 300 nm of Au, followed by a metal lift off. The Si wires were grown by atmospheric pressure chemical vapor deposition at a growth temperature of 1050 ° C and a SiCl4 partial pressure of 9 Torr in an H2 carrier gas. Under these conditions, 50 m long vertically-oriented Si wire arrays were grown 共Fig. 1兲 with an average wire diameter of 2.6 m, pitch of 7 m and good pattern integrity across an area of 2.5⫻ 2.5 mm2 共⬃126 000 wires兲. For the fabrication of the solar cell, it was essential to effectively remove Au from the tips and sidewalls of the Si wires. To reduce the surface diffusion of Au down the side walls of the wires during postgrowth cooling, the reactor tube was force cooled using fans. Rapid cooling produces a well-confined Au droplet on the top of the wires as shown in Fig. 2共a兲. The Si wire array samples were initially etched
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FIG. 1. Low magnification SEM image of an array of Si wires grown from a pattern with 5 m diameter pores with 7 m pitch, producing 2.6 m diameter wires. The size of the image is 400⫻ 400 m2. Shown in the inset is a higher magnification image of the Si wires; the scale bar represents 20 m.
with buffered oxide etch 共BOE兲 and Au was then removed using a commercial etchant 关Transene Au etchant 共TFA兲兴 that was heated to 40 ° C to increase the etch rate. The top surfaces of the micrometer-diameter wires were found to exhibit a rough texture, as shown in Fig. 2共b兲, although Au was not detected within the limits of energy dispersive spectroscopy 共EDS兲 共approximately one atomic percentage兲. The rough surface is believed to be due to residual Si that precipitated from the Au droplet during the forced cooling.19 The residual Si was thin enough to enable characterization by transmission electron microscopy 共TEM兲 without the need for additional sample preparation. The material was found to contain nanoscale particles 关Fig. 2共e兲兴 that were determined by EDS to be Au inclusions within the Si matrix 关Fig. 2共f兲兴. In an effort to remove the embedded Au and reduce the tip roughness, the wire arrays were thermally oxidized and then re-etched in BOE. The wire arrays were initially cleaned using a standard RCA process and then oxidized at a temperature of 1000 ° C for 2 h, producing an oxide thickness of
FIG. 2. SEM images of the Si wire tip: 共a兲 after growth and cool-down showing the Au catalyst; 共b兲 after removal of the Au catalyst showing the residue on the top of the Si wire; 共c兲 after one oxidation and etch step which exposes Au particles; 共d兲 after two successive oxidation and etch steps showing the complete removal of Au; 共e兲 TEM image; and 共f兲 EDS data from the residue on the top of wires confirming the presence of Au precipitates. The scale bars represent 1 m unless specified.
Appl. Phys. Lett. 97, 143108 共2010兲
⬃75 nm. The thermal oxide was then removed using BOE. After this first oxidation and etch step, the roughness was reduced, and subsequent EDS analysis revealed the presence of Au particles on the tips of the wires 关Fig. 2共c兲兴. The Au particles were removed with a second gold etch and an additional thermal oxidation and BOE etch was then carried out which yielded smooth tip surfaces 关Fig. 2共d兲兴 and no additional evidence of Au. The embedded Au particles in the Si wire tip region 关Fig. 2共e兲兴 are believed to form during phase segregation of the Au–Si eutectic liquid during the rapid cooling after VLS growth. It is also anticipated that Au concentrations in excess of the solid solubility limit of 1 ⫻ 1016 cm−3 for Au in Si at 1000 ° C will be present in the near-surface region of the Si due to bulk Au diffusion at the temperatures used for VLS growth.20,21 During subsequent thermal oxidation at 1000 ° C, Au will segregate to the SiO2 – Si interface as reported previously22 due to the reduced surface energy of Au– SiO2 compared to Au–Si. The segregated Au will agglomerate via Ostwald ripening to form larger Au particles at the SiO2 – Si interface. After the SiO2 is removed by the BOE, the Au particles are exposed on the Si wire surface as shown in Fig. 2共c兲. The residual Au can then be removed via wet etching although additional oxidation/etch steps or longer oxidation times may be required to remove excess Au down to the solid solubility limit of Au in Si at 1000 ° C 共1016 cm−3兲.20 The Si wire arrays reported in this study were grown without the addition of an in situ dopant source. To determine the resistivity and carrier type of the wires, back-gated four point resistance measurements were carried out on individual Si wires using an electrical test bed structure previously described23 that included four topside electrodes. The two inner electrodes serve as voltage probes for four-point resistance measurements and source and drain electrodes for gate-dependent current-voltage measurements. A sample containing smaller diameter 共200–600 nm兲 Si nanowires grown under identical conditions was used for this measurement in order to ensure conformal coverage of the top contact metals on the wire surface. The four point resistance measurements indicated a Si wire resistivity of 170⫾ 50 ⍀ cm and the back-gated measurements indicated p-type conductivity. Assuming a wire diameter of 500 nm and an interface state density of 1012 cm−2 that fully depletes the wires, the maximum carrier concentration is estimated to be 6 ⫻ 1016 cm−3. To form the p-n junction, POCl3 was thermally diffused into the p– Si wire arrays at 1000 ° C for 13 min, which is expected to result in a junction depth of 350 nm. To ensure that only the Si wires and the area in between the wires were exposed to the POCl3, the back of the wafer and the area surrounding the Si wire array 共2.5⫻ 2.5 mm2兲 was protected with 200 nm of SiO2 that remained from the second oxidation step. The SiO2 was later removed in BOE to allow the n-type and p-type regions to be contacted. For the back contact, 300 nm of Al was thermally evaporated on the back of the sample after the removal of the SiO2 layer, and the Al was annealed at 600 ° C for 10 min in N2. Top contacts to the diffused n-type region were formed by cold pressing indium onto the oxide-free Si surface. The effect of postgrowth cleaning on the I-V characteristics of the diffused junction Si wire arrays is shown in Fig.3共a兲. Devices fabricated on a similar sample as described
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FIG. 3. 共a兲 Semilog plot of the dark I-V data obtained from radial junction Si wire array solar cells. Devices fabricated after the Au etch step only 共dashed line兲 result in nonrectifying behavior while an improvement in the diode characteristics is obtained following the oxidation and stripping process 共solid line兲. The diode ideality factor is 3.4 and Jo = 1.9⫻ 10−6 A / cm2. 共b兲 Light J-V characteristics obtained using a class A solar simulator for a radial junction solar cell fabricated using a Si wire array fabricated with wires 2.6 m in diameter, 50 m long, and a filling ratio of 10% with a total active array area of 2.5⫻ 2.5 mm2. The solar cell produced a Voc of 0.5 V, Jsc of 7.6 mA/ cm2, FF of 57% and an efficiency of 2.3%.
above using the Au etch step only exhibited very high reverse saturation currents 共Jo = 4.1⫻ 10−4 A / cm2兲 and were generally considered to be nonrectifying. This is believed to be due to the residual Au contamination on the wire tips and sidewalls, which leads to increased leakage across the junction. By using the thermal oxidation and stripping process to further clean the wire surfaces, the reverse saturation current was reduced by two orders of magnitudes to Jo = 1.9 ⫻ 10−6 A / cm2 yielding diodes with ideality factors of ⬃3.4. The high ideality factor is believed to arise from shunt leakage due to edge effects in the device.24 The fabricated solar cell was tested using a class A solar simulator under a one sun Air Mass 1.5G illumination. Figure 3共b兲 shows the light I-V data obtained for a diffused junction Si wire array solar cell fabricated with 2.6 m diameter by 50 m long Si wires with a pitch of 7 m, which gives a wire filling ratio of 10%. The solar cell had a Voc of 500 mV, which is significantly higher than the values of 130– 300 mV reported previously for Au-catalyzed Si nanowire solar cells and is similar to the Voc obtained for DRIE Si pillar devices 共480–530 mV兲.5,7,8,11,18 However, the best planar Si solar cells have Voc values between 600 and 700 mV.25 The lower Voc values of these pillar array cells can be attributed to the higher saturation current density and the lower shunt resistance 共12 k⍀ cm2 determined from a linear fit of the light I-V near Isc兲 compared to planar Si cells. The shortcircuit current density 共Jsc兲 of the cell was 7.6 mA/ cm2 and the fill factor 共FF兲 was 57%, which resulted in an efficiency 共兲 of 2.3%. In addition to the low shunt resistance, which can likely be improved through surface passivation, the cells had a relatively high series resistance 共78 ⍀ cm2 determined from a linear fit of the light I-V near Voc兲, which together account for the low FF of these cells.26 The high series resistance arises from the high resistivity of the Si wire cores and the top contact geometry and further improvements can be achieved through the use of intentional doping and the introduction of a low resistance conformal transparent conductive oxide top contact layer. The Jsc of these initial Aucatalyzed Si wire array devices is lower than that reported for
the DRIE Si pillar array solar cells5 likely due to a combination of the high series resistance, low wire filling ratio and lack of additional light-trapping elements. Nevertheless, the results demonstrate an important step in the development of radial junction solar cell devices fabricated using VLSgrown Si wire arrays. In summary, thermal oxidation and stripping was found to significantly improve the diode and light I-V characteristics of radial p-n junction Si wire array solar cells fabricated by VLS growth using Au as the catalyst. The oxidation/ stripping process effectively removed residual Au impurities embedded within the wires resulting in an increased Voc of 500 mV and efficiency of 2.3% for a 2.5⫻ 2.5 mm2 Si wire array device. This work was supported by the Department of Energy under Contract No. DE-FG36-08GO18010. The devices were fabricated at the PSU site of the NSF NNIN under Grant No. 0335765. 1
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