radioelectronics & informatics

TEST TECHNOLOGY TECHNICAL COUNCIL (TTTC) OF THE IEEE COMPUTER SOCIETY EDUCATION AND SCIENCE MINISTRY OF UKRAINE

KHARKOV NATIONAL UNIVERSITY OF RADIOELECTRONICS

ISSN 1563-0064

RADIOELECTRONICS & INFORMATICS

Scientific and Technical Journal № 2 (45), April – June 2009

Founded in 1997 Published 4 times a year

© Kharkov National University of Radioelectronics, 2009 Sertificate оf the State Registration КВ № 12097-968 ПР 14.12.2006

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International Editorial Board:

Local Editorial Board:

Y. Zorian – USA M. Karavay – Russia R. Ubar – Estonia S. Shoukourian – Armenia D. Speranskiy – Russia M. Renovell – France A. Zakrevskiy – Byelorussia R. Seinauskas – Lithuania Z. Navabi – Iran E. J. Aas – Norway J. Abraham – USA A. Ivanov – Canada V. Kharchenko – Ukraine O. Novak - Czech Republic Z. Peng - Sweden B. Bennetts - UK P. Prinetto - Italy V. Tarassenko - Ukraine V. Yarmolik - Byelorussia W. Kusmicz - Poland E. Gramatova - Slovakia H-J. Wunderlich – Germany S. Demidenko – New Zealand F. Vargas – Brazil J-L. Huertas Diaz – Spain M. Hristov – Bulgaria W. Grabinsky – Switzerland A. Barkalov – Poland, Ukraine

Bondarenko M.F. – Ukraine Bykh A.I. – Ukraine Volotshuk Yu.N – Ukraine Gorbenko I.D. – Ukraine Gordienko Yu.E. – Ukraine Dikarev V.A. – Ukraine Krivoulya G.F. – Ukraine Nerukh A.G. – Ukraine Petrov E.G. – Ukraine Presnyakov I.N. – Ukraine Rutkas A.G. – Ukraine Rudenko O.G. – Ukraine Svir I.B. – Ukraine Svich V.A. – Ukraine Semenets V.V. – Ukraine Slipchenko N.I. – Ukraine Terzijan V.Ya. – Ukraine Chumachenko S.V. – Ukraine Hahanov V.I. – Ukraine Yakovenko V.M. – Ukraine Yakovlev S.V. – Ukraine

Address of journal edition: Ukraine, 61166, Kharkiv, Lenin avenu, 14, KNURE, Design Automation Department, room 321, ph. (0572) 70-21-326, d-r Hahanov V.I. E-mail: [email protected]; [email protected], http://www.ewdtest.com/ri/

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CONTENTS INTEGER LINEAR PROGRAMMING MODELS FOR THE PROBLEM OF COVERING A POLYGONAL REGION BY RECTANGLES G. SCHEITHAUER, YU. STOYAN AND T. ROMANOVA……………………………………………………4 Z DOMAIN DELAY SUBCIRCUITS AND COMPACT VERILOG-A MACROMODELS FOR MIXED-MODE SAMPLED DATA CIRCUIT SIMULATION M. E. BRINSON, H. NABIJOU...................................................................................................................14 OPTIMIZATION FACTORS IN MODELING AND TESTING HARDWARE AND SEMICONDUCTOR DEFECTS BY DYNAMIC DISCRETE EVENT SIMULATION JACK H. ARABIAN………………………………………………………………………………………21 ITERATIVE METHOD OF MINIMIZATION OF ARBITRARY BOOLEAN FUNCTIONS OF MANY VARIABLES ARKADIJ ZAKREVSKIJ………………………………………………………………………………….24 REDUCTION OF HARDWARE AMOUNT FOR CONTROL UNIT WITH ADDRESS TRANSFORMER ALEXANDR A. BARKALOV, LARISA A. TITARENKO, ALEXANDR S. LAVRIK.........................................29 NUMERICAL SIMULATION OF CHARGE DIFFUSION ON THE SURFACE OF A DENDRIMER MOLECULE ARTYOM V. ANDREYEV, OLEKSIY V. KLYMENKO…………………………………………………….34 OPTIMIZATION OF CONTROL UNIT WITH CODE SHARING ALEKSANDER A. BARKALOV, LARYSA A. TITARENKO, ALEKSANDER N. MIROSHKIN………………39 STATISTICAL PROPERTIES OF SPREAD SPECTRUM SIGNALS SYNCHRONIZATION SYSTEM INNA O. TKALICH, HELEN V. KHARCHENKO AND YEGOR I. VDOVYCHENKO………………………..44 ALGEBRA-LOGICAL REPAIR METHOD FOR FPGA LOGIC BLOCKS VLADIMIR HAHANOV, EUGENIA LITVINOVA, WAJEB GHARIBI, OLESYA GUZ………………………49 CORPORATIVE ECOLOGICAL SYSTEM AND PROCESSES MATHEMATICAL MODELLING KOZULIA T.V., SHARONOVA N.V...........................................................................................................57 COMPUTER-AIDED DESIGN FOR ROBOTIC ASSEMBLY TECHNOLOGY IGOR SH. NEVLYUDOV, OLEXANDER M. TSYMBAL, SVETLANA S. MILYUTINA……………………...63 THE PROCESS ALGEBRA USAGE FOR SIMULATION PURPOSES OLISHCHUK S., VOLK M.………………………………………………………………………………68 PREPARATION OF PAPERS FOR IEEE TRANSACTIONS AND JOURNALS……………………………71

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Integer Linear Programming Models for the Problem of Covering a Polygonal Region by Rectangles G. Scheithauer, Yu. Stoyan and T. Romanova Abstract– The aim of the paper is to develop integer linear programming (ILP) models for the problem of covering a polygonal region by rectangles. We formulate a Beasley-type model in which the number of variables depends on the size parameters. Another ILP model is proposed which has O(n2 max{m, n}) variables where m is the number of edges of the target set and n is the number of given rectangles. In particular we consider the case where the polygonal region is convex. Extensions are also discussed where we allow the polygonal region to be a union of a finite number of convex subsets. Index terms – Covering, Integer Linear Programming, Mathematical Modelling, Optimization

Introduction and Problem Formulation In this paper the problem of covering a polygonal target set Ω by a finite number of given rectangles is considered. The main aim is to formulate integer linear programming or optimization models. Rotation of rectangles is not allowed. In particular, the target set is assumed to be an arbitrary convex polygon. Since covering with axes-parallel rectangles is considered the target set can also be assumed to be an orthogonally convex rectilinear polygon. The decision version of problem CPR (Covering a Polygonal set with Rectangles) asks whether there exists a covering or not. It is known to be NP-complete since the decision version of the Bin Packing Problem ([6]) can be reduced to the CPR problem (cf. [4]). Notice, in difference to e.g. [4] where a finite number of points has to be covered, we consider the covering of an infinite point set. Therefore, the verification that a certain configuration of the rectangles forms a cover of the target set cannot be done by inspecting a finite number of points, another technique is needed.

require a lot of computational effort to prove that circumstance. In [8] one-dimensional bar relaxations for the CPR problem are proposed to be used as necessary conditions for existence of coverings. Covering problems are of interest in many fields of application. There are many relations between covering and packing or cutting problems. For an annotated survey on Cutting and Packing we refer to [5]. Covering problems arise naturally in a variety of applications. For a comprehensive overview we refer to [4]. As an example, query optimization in spatial databases is a source of covering problems. In this setting a query may correspond to a geometric region and be phrased in a generic form using geometric parameters. Given a set of existing geometric, parametrized, query regions and a set of points or regions, we might want to ask if there are values of the parameters that allow the query regions to cover the set of points or even regions. Another field of application (also mentioned in [4]) is shape recognition for robotics, graphics or image processing applications. In these cases it is sometimes useful to represent a shape as a collection of parts. However, given a collection of parts and a shape, it can be difficult to determine if the shape can be described by that collection of parts. If the goal is to obtain an outer approximation of the shape using the parts, then this can be posed as a covering problem. Besides the decision problem whether a covering exists or not, related problems can be of interest. For instance, one can ask for a minimum number of (identical) rectangles needed to form a cover for the target region. Or, if there exist several covers one can look for a best cover where best means that some objective function is regarded.

In computational geometry, decomposition of a polygon is of high interest involving partitioning and covA solution approach based on a so-called Γ-function ering problems. For details and further literature we is proposed in [9]. The Γ-function of a certain config- refer to [10, 1, 7]. uration of all given rectangles attains a non-negative value if and only if this configuration forms a feasible In the approach proposed in [9] to solve the problem covering of the target set. Based on an enumera- of covering a compact polygonal region with a finite tion scheme, instances for which no cover exists can family of rectangles, the choice of a suitable starting configuration is in particular an essential aspect.

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Therefore, and since the CPR problem is hard to solve, enumeration algorithms like branch-and-bound have to be used in general in an exact solution approach. Another possibility to attack the CPR problem consists in formulating integer linear programming models and to solve them. The aim of this contribution is to develop models and to discuss advantages and disadvantages with respect to the construction of exact solution approaches. Without loss of generality, we assume that all inputdata are integers. The paper is organized as follows. In the rest of this section we give the input-parameter and state the problem considered in the paper. In the next section a Beasley-type model of the covering problem is discussed. Then, in section 3, a basic model is developed. In section 4, we present a corresponding ILP model. Some extensions and alternative formulations are discussed in section 5. Finally, some conclusions follow.

We always assume that problem CPR has a solution. This can be done by adding some sufficiently large rectangle R0 (i.Pe. the minimum Ω enclosing rectangle) with c0 > i∈In ci . Consequently, if the optimal value of the CPR problem is not smaller than c0 then the original problem has no covering.

A Beasley-type Model: ILP Model 1 Beasley [3, 2] proposed an integer linear programming (ILP) model with 0/1-variables for the twodimensional rectangle packing problem. There, the 0/1-variables xipq are used to describe the placement of the reference point (lower left corner) of rectangle Ri at position (p, q). For an ILP model of the CPR problem we can also use these xipq -variables. Let

XW := mini∈IΩ Xi , XE := maxi∈IΩ Xi , Within this paper we consider the following optimizaYN := maxi∈IΩ Yi , YS := mini∈IΩ Yi tion problem. We assume that target set Ω is a convex polygon. Consequently, we can use the represen- denote the extremal coordinates of Ω. To visualize tation different directions we use N for the north-direction, E, S and W for east, south and west direction, reΩ = {(x, y) : gj (x, y) ≤ 0, j ∈ IΩ } spectively. Clearly, directions N , E, S and W can be = conv{(Xj , Yj ) : j ∈ IΩ }, understood as top, right, bottom or left direction, reIΩ = {1, . . . , m}. spectively. Without loss of generality, we may assume XW = 0 and YS = 0. Consequently, target set Ω is All the linear functions gj , j ∈ IΩ are assumed to completely contained within a rectangle R0 of dimenbe necessary for the representation of Ω. Hence, the sions L0 = XE − XW and W0 = YN − YS . Since all number of vertexes (corners) (Xj , Yj ) of Ω coincides input-data are assumed to be integral we can restrict with the (minimum) number of functions gj . In order the coordinates of all allocation point to be integral to cover the given target set Ω the following rectantoo. Let Li = {0, . . . , L0 −ℓi }, Wi = {0, . . . , W0 −wi }, gles are available: i ∈ In . If rectangle Ri is placed with its lower left Ri = {(x, y) : −ai ≤ x ≤ ai , −bi ≤ y ≤ bi }, corner at point (p, q) with p ∈ Li and q ∈ Wi then it covers the point set i ∈ In = {1, . . . , n} Ri (p, q) = {(x, y) : p ≤ x < x + ℓi , where 2ai is the length and 2bi the width of rectangle (1) Ri . We assign to each rectangle its (positive) value ci , ≤ y < q + wi } i ∈ In , e. g. ci = ai bi , and we denote the placement parameters (translation vectors) by ui = (xi , yi ), i ∈ where ℓi = 2ai and wi = 2bi , i ∈ In . Notice, here the upper and right boundary are assumed not to be In . Hence, in Ri (p, q) Let Ω denote the minimal orthogonally Ri (xi , yi ) = {(x, y) : xi − ai ≤ x ≤ xi + ai , convex rectilinear polygon with only integral corner yi − bi ≤ y ≤ yi + bi } points enveloping Ω. Since we are looking for a covrepresents the translated rectangle Ri . Then the ering of Ω with only rectangles we have, the convex target set is covered if Ω is covered. Notice, using problem CPR under consideration is: an appropriate scale the approximation of Ω by Ω is tight enough to obtain an exact solution. We assume Find a subset I ∗ of In of the rectangles and that Ω is a closed point set. According to definition corresponding placement parameters ui , i ∈ (1) not all integer lattice points in Ω have to be covI ∗ such that ∪i∈I ∗ Ri (uP i ) forms a cover of Ω ered namely those lying on the NE or SE boundary, and its total valuation i∈I ∗ ci is minimal.

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 {N, S}, if t ∈ {E, W }, accept the leftmost point lying on the SE boundary. t ∈ D. D := t e denote the integer lattice points in Ω which {E, W }, if t ∈ {N, S}. Let Ω have to be covered by the rectangles. Since the polygonal region Ω is assumed to be conThen the optimization problem can be formulated as vex the following denotations and abbreviations are meaningful. We identify Ω defining functions visible follows: from different directions as follows: Beasley-type model: ILP model 1 δgj δgj < 0, > 0}, IΩN W := {j ∈ IΩ : δx δy X X ci xipq → min (2) mN W := |IΩN W |, i∈In (p,q)∈Ω e

IΩN E := {j ∈ IΩ :

subject to X

s X

t X

xipq ≥ 1,

i∈In p=s(i) q=t(i)

X X

xipq ≤ 1,

e (3) ∀ (s, t) ∈ Ω,

∀ i ∈ In ,

(4)

mN E := |IΩN E |, IΩSW := {j ∈ IΩ :

p ∈ Li , q ∈ Wi , i ∈ In (5)

δgj δgj < 0, < 0}, δx δy

mSW := |IΩSW |,

p∈Li q∈Wi

xipq ∈ {0, 1},

δgj δgj > 0, > 0}, δx δy

IΩSE := {j ∈ IΩ :

δgj δgj > 0, < 0}, δx δy

mSE := |IΩSE |, where s(i) = max{0, s − ℓi + 1}, t(i) = max{0, t − wi + 1}. Moreover, let This Beasley-type model has some drawbacks. First mrs = msr ∀r ∈ Ds , s ∈ D. of all, the number of 0/1-variables depends on the dimensions of the target set. Moreover, the choice of In order to characterize the relation between two rectan appropriate scale can further increase this number. angles we define the constants Furthermore, the continuous (or linear programming,  1, ai > aj , LP) relaxation (restrictions xipq ∈ {0, 1} are replaced aij := 0, ai ≤ aj , by xipq ∈ [0, 1]) is weak. It yields feasibility if the  i, j ∈ In , i 6= j. (6) 1, bi > bj , total area of the rectangles is not smaller than the bij := 0, bi ≤ bj , area of Ω. This makes it difficult to solve the (integer) Beasley-type model. These constants are used to combine different cases, Notice, the number of 0/1-variables can be some- and therefore, to shorten the description. what reduced regarding the shape of Ω instead of the enveloping rectangle L × W . Another opportunity For a given 0/1-vector α = (α1 , . . . , αn ) and a given 2n results from the principle of normalized patterns or vector u = (u1 , . . . , un ) ∈ IR of placement parame2 ters ui ∈ IR , i ∈ In let raster points. [ Ri (ui ), P (u, α) :=

Basic Model

i:αi =1

H(u, α) := IR2 \ int(P (u, α)). In the following, an attempt is made to model the Polygonal set P (u, α) represents the point set covered CPR problem using a polynomial number of variables by the chosen rectangles whereas H(u, α) denotes the and restrictions. closure of the complement of P (u, α). For technical purposes let ( Notations 4, if t ∈ {N, W }, dt := t ∈ D. (7) 2, if t ∈ {S, E}, The following sets of directions will be used: D := {N, E, S, W },

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Placement Parameters

If more then one rectangle is used to cover Ω not all of these restrictions have to be fulfilled depending on the As already introduced above, we denote the place- relative positions of the rectangles. Here we assume ment parameters (translation vectors) to be found that no coverings are of interest where some covering rectangle Ri (ui ) is completely contained within by ui = (xi , yi ), i ∈ In . Hence, another covering rectangle Rj (uj ). Such a configuraRi (xi , yi ) = {(x, y) : tion cannot be optimal because of assumption ci > 0, xi − ai ≤ x ≤ xi + ai , yi − bi ≤ y ≤ yi + bi } i ∈ In . represents the region covered by the translated rectangle Ri .

Selection Variables In order to indicate those rectangles Ri , i ∈ In which are used to cover the polygonal region Ω we define 0/1-variables αi according to ( 1, Ri (ui ) is used for the cover, αi = 0, Ri (ui ) is not used for the cover. Let Ri be given in the form Ri (xi , yi ) = {(x, y) : fir (x, y) ≥ 0, r ∈ D}, i ∈ In ,

Relative Position Variables If rectangles Ri and Rj are both used to cover Ω, i. e. if αi = αj = 1, 0/1-variables r φrij and ψij ,

i, j ∈ In , i 6= j, r ∈ {1, . . . , 5}

are introduced to characterize the relative position of the two rectangles to each other. In doing so we consider five different situations in horizontal and ialso n vertical direction (cf. Fig. ??). Consequently, using both rectangles Ri and Rj that means we have r=1

r=3 i

where fiN (x, y) := yi + bi − y, fiE (x, y) := xi + ai − x, fiS (x, y) := y + bi − yi , fiW (x, y) := x + ai − xi . In case that Ω fits within a single rectangle Ri (ui ) and in related situations the following conditions on the translation vector ui = (xi , yi ) are probably nontrivial since they form the boundary of H(u, α): feiN (xi , yi ) := yi + bi − YN ≥ 0,

feiE (xi , yi ) := xi + ai − XE ≥ 0,

feiS (xi , yi ) := YS + bi − yi ≥ 0,

feiW (xi , yi ) := XW + ai − xi ≥ 0.

r=5

r=2

r=4

Figure 1: labelfig-1 Different relative horizontal positions

5 X r=1

φrij = 1

and

5 X

r ψij = 1.

(9)

r=1

With other words, equations (9) should be fulfilled if and only if both rectangles Ri and Rj are used to cover Ω in order to get a unique description of the different configurations/interactions of the two rectangles which are as follows.

We define φ1 = 1 if and only if Rj (uj ) is completely These inequalities should hold only if rectangle Ri left to R (u ij) which leads to the inequality i i is used. Therefore we modify them by adding some term depending on αi : xj + aj ≤ xi − ai + M (1 − φ1ij ) (non-trivial if φ1ij = 1) feir (xi , yi ) + M (1 − αi ) ≥ 0, (8) r ∈ D, i ∈ In , where M is a sufficient large number, e. g. M = XE + a i + aj . The case when Rj (uj ) is completely right to where M is a sufficient large number, e. g. M = 5 R i (ui ) is characterized by φij = 1. If int(Ri (ui )) ∩ max{L0 , W0 }. For every i ∈ In these four restrictions (in a somewhat modified manner) have to be Rj (uj ) 6= ∅ then we have three subcases, namely added to an ILP model. r = 2: xj − aj ≤ xi − ai ≤ xj + aj ,

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r = 3: either xj − aj ≤ xi − ai < xi + ai ≤ xj + aj or xi − ai ≤ xj − aj < xj + aj ≤ xi + ai , r = 4: xj − aj ≤ xi + ai ≤ xj + aj . Obviously, only one of two cases with r = 3 can occur according to the definition of aij and bij in formula (6). Altogether, we have the following restrictions (describing the relative horizontal position of Ri and Rj ) which are non-trivial if some φ-variable has value one: h1ij (x, φ) := xi − ai − xj − aj + M (1 − φ1ij ) ≥ 0, 2 hij (x, φ) := xj + aj − xi + ai + M (1 − φ2ij ) ≥ 0, 3 hij (x, φ) := xi − ai − xj + aj + M (1 − φ2ij ) ≥ 0, h4ij (x, φ) := (aij − aji )(xj − aj − xi + ai ) +M (1 − φ3ij ) ≥ 0, h5ij (x, φ) := (aij − aji )(xi + ai − xj − aj ) +M (1 − φ3ij ) ≥ 0, h6ij (x, φ) := xj + aj − xi − ai + M (1 − φ4ij ) ≥ 0, 7 hij (x, φ) := xi + ai − xj + aj + M (1 − φ4ij ) ≥ 0, h8ij (x, φ) := xj − aj − xi − ai + M (1 − φ5ij − ≥ 0.

Notice, every combination of φ- and ψ-values which fulfills conditions (9) defines a subset of IR4 of possible placement parameters ui = (xi , yi ) and uj = (xj , yj ).

Overlap Characterizing Variables If two rectangles Ri and Rj are used to cover Ω then two essential different situations have to be considered: is the intersection of the two rectangles empty or not. For that reason 0/1-variables βij can be introduced which gets value one if and only if the intersection of Ri (ui ) and Rj (uj ) is non-empty. It is obvious, the β-variables are dependent on the φand ψ-variables. It holds

(10)

βij =

4 X

φrij ·

r=2

4 X

r ψij ,

i, j ∈ In , i 6= j.

r=2

Note that although in cases r = 1 or r = 5 some ”touching” is allowed, these situations cannot lead to a real overlap.

Inner Corners

Every pair Ri and Rj of used rectangles with nonIn a similar way the ψ-variables are defined to char- empty intersection (i. e. βij = 1) determines some acterize the relative vertical position of the two rect- points, called inner corners which probably define a angles: cone usable in the representation of H(u, α) 1 e hij (y, ψ) := In order to obtain a description of H(u, α) we con1 yi − bi − yj − bj + M (1 − ψij ) ≥ 0, sider all eight possibilities of inner corners which can e arise. By means of 0/1-variables we identify in depenh2ij (y, ψ) := 2 dence of the φ- and ψ-variables these inner corners yj + bj − yi + bi + M (1 − ψij ) ≥ 0, which are formed with respect to this configuration. e h3ij (y, ψ) := Using further 0/1-variables we characterize those in2 yi − bi − yj + bj + M (1 − ψij ) ≥ 0, ner corners which form cones for the description of e h4ij (y, ψ) := (bij − bji )(yj − bj − yi + bi ) H(u, α). 3 +M (1 − ψij ) ≥ 0, (11) In total, there are eight different types of inner core h5 (y, ψ) := (bij − bji )(yi + bi − yj − bj ) ners. We define ij

3 +M (1 − ψij ) ≥ 0,

e h6ij (y, ψ) := 4 ) ≥ 0, yj + bj − yi − bi + M (1 − ψij 7 e h (y, ψ) := ij

4 ) ≥ 0, yi + bi − yj + bj + M (1 − ψij

e h8ij (y, ψ) := 5 ) ≥ 0. yj − bj − yi − bi + M (1 − ψij

Because of definition we have

6−r r φrij = φ6−r ji , ψij = ψji , r ∈ {1, . . . , 5}, i, j ∈ In , i 6= j.

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st Eij ,

s ∈ D, t ∈ Ds , i, j ∈ In , i 6= j,

as follows: NW Eij := (xj −aj , yi +bi ),

NE Eij := (xj +aj , yi +bi ),

SW Eij := (xj −aj , yi −bi ),

SE Eij := (xj +aj , yi −bi ),

EN Eij := (xi +ai , yj +bj ),

ES Eij := (xi +ai , yj −bj ),

WN Eij := (xi −ai , yj +bj ),

WS Eij := (xi −ai , yj −bj ).

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In order to identify those inner corners which are induced by Ri , Rj , and the φ- and ψ-variables we define 0/1-variables εst ij as follows.

1.

3.

2.

@ @ Ω @ @

@ @ Ω @ @

@ @ Ω @ @

W which corresponds to point The variable εN ij NW NW = (xj − aj , yi + bi ) has to be one if and only if Figure 3: Interaction between Eij and target region Eij Ω NW αi = αj = 1, Eij ∈ Ri (ui ) ∩ Rj (uj ).

1. Either Ω ⊂ {(x, y) : y ≤ yi + bi }, or

In this case, the set

2. Ω ⊂ {(x, y) : x ≥ xj − aj }, or

{(x, y) : x ≤ xj − aj , y ≥ yi + bi }

NW ) ≥ 0 for at least one l ∈ IΩN W . 3. gl (Eij

forms a cone in North-West direction. There are sevNW forms an inner cor- This can be modelled using the ε-variables as follows:: eral situations where point Eij ner, namely: max {yi + bi − YN , XW − xj + aj , 4 NW = 1, 1. φ4ij = 1, ψij max{gl (Eij ) : l ∈ IΩN W } (12) NW +M (1 − εij ) ≥ 0. 2. φ4 = 1, ψ 3 = 1, b = 1, ji

ij

ij

For every pair of rectangles and every kind of potential inner corner such an inequality has to be considered, i. e. approximately 4n2 restrictions. But this NW is inequality should be redundant if the point Eij covered by a third rectangle.

4 3. φ3ij = 1, aij = 1, ψij = 1, 3 4. φ3ij = 1, aij = 1, ψij = 1, bji = 1.

These four situations are depicted in Ffigure 2. 1.

j

2.

j

3.

j

Similar conditions hold for the other types of inner corners.

4.

i

j

i

i

i

NW Figure 2: Situations where inner corner Eij arise

If P only two rectangles are needed to cover Ω, i. e. i∈In αi = 2 and βij = 1, then the resulting two or four inner corners determine cones usable in the can description of H(u, α).

If more than two rectangles are needed to cover Ω Linear equations or inequalities are needed which en- then some of the resulting inner corners can be covW sure that εN becomes one in exactly these four ered by another third rectangle, and hence, are not ij useful for the description of H(u, α). cases. It holds for i 6= j: W 4 3 εN = (φ4ij + aij φ3ij )(ψij + bji ψij ), ij E 2 3 4 3 εN ij = (φij + aij φij )(ψij + bji ψij ), 2 3 εSW = (φ4ij + aij φ3ij )(ψij + bji ψij ), ij 2 3 2 3 εSE ij = (φij + aij φij )(ψij + bji ψij ).

Furthermore, for i 6= j we have sr εrs ij = εji ,

Active Inner Corners In case of more than two rectangles used to cover Ω NW , is it may happen that some inner corner, e. g. Eij NW covered by a third rectangle Rk so that Eij does not form a part of the complement of the union of covering rectangles as drawn in Fig. 4. In order to charac-

r ∈ D, s ∈ Dr . j

W NW If we suppose that εN = 1 and that Eij ∈ H(u, α) ij then at least one of the following inequalities, illustrated in Fig. 3,

must be fulfilled for the convex region Ω to ensure non-overlapping:

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k i NW Figure 4: Inner corner Eij is not active

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W terize such situation we introduce a 0/1-variable ρN restriction (14) can be formulated as ij NW P st rs rs rs which has to be one if and only if Eij is not covfeir (xi , yi ) + m λrs NW ij0 t=1 λijt gt (Eij ) ered by another rectangle. More precisely, ρij = 1 es +λrs should hold true if and only if there does not exist ij,mrs +1 fj (xj , yj ) ≥ 0, any k ∈ In \ {i, j} with r ∈ D, s ∈ Dr , i, j ∈ In , i 6= j,

(16)

where gtrs are the functions corresponding to IΩrs .

1. φ4kj + akj φ3kj = 1, and 4 3 2. ψik + bki ψik = 1.

Summation

Hence, we define

If for all relations between the α-, φ-, ψ-, ρ-, mad λvariables linear inequalities or equalities can be W = 1 ⇐⇒ ρN ij P found then an ILP model for the problem of covering 3 4 3 4 k6=i,j (φkj + akj φkj )(ψik + bki ψik ) = 0. a convex polygon by rectangles can be obtained. As an intermediate result we have the following formuW = 1 the bounding constraints in lation of the CPR problem: In case of ρN ij North-direction for Ri and in West-direction for Rj (according to (1)) must be removed. This can be Compute placement parameters xi , yi , i ∈ In and p 0/1-variables αi , i ∈ In , φpij , ψij p ∈ {1, . . . , 5}, ρrs achieved as follows: ij , rs and λijt , r ∈ D, s ∈ Dr , t ∈ {0, . . . , mrs + 1}, i, j ∈ feiN (xi , yi ) + M (1 − αi ) In , i 6= j such that P NW X +M j:j6=i ρij ≥ 0, ci αi → min, (17) (13) fejW (xj , yj ) + M (1 − αj ) i∈In P W ≥ 0. +M j:j6=i ρN ij subject to Instead of the two removed restrictions, another condition has to become relevant which guaranties that Ω is either in one of the two half-planes determined NW 6∈ int(Ω): by fiN or fjW or that Eij max{feiN (xi , yi ), fejW (xj , yj ), NW max{gl (Eij ) : l ∈ IΩN W }} W +M (1 − ρN ij ) ≥ 0.

t=0

10

∀r, s, i, j.

r ψij = αi αj ,

∀i, j,

(14)

(18)

r=1

htij (x, φ) ≥ 0,

t ∈ {1, . . . , 8}, ∀i 6= j,

(19)

e htij (y, ψ) ≥ 0,

t ∈ {1, . . . , 8}, ∀i 6= j,

(20)

sr εrs ij = εji ,

ρrs ij

≤

εrs ij ,

rs ρrs ij = εij

rs In case of an active inner corner Eij , i. e. with ρrs ij = rs 1, 0/1-variables λijt , t = 0, . . . , mrs + 1, are needed to identify a single constraint which ensures the nonoverlapping similar to (12). Because of

rs λrs ijt = ρij ,

r=1

5 X

dr aij φ3ij )(ψij

3 εrs + + bji ψij ), ij = r ∈ D, s ∈ Dr , i 6= j.

Constraint Selection Variables

mX rs +1

φrij = αi αj ,

(φdijs

Similar restrictions have to be introduced for the other types of active inner corners: max{feir (xi , yi ), fejs (xj , yj ), rs ) : l ∈ IΩrs }} max{gl (Eij +M (1 − ρrs ij ) ≥ 0, r ∈ D, s ∈ Dr , i, j ∈ In , i 6= j.

5 X

(21)

r ∈ D, s ∈ Dr .

(22)

∀r ∈ D, s ∈ Dr , i 6= j, P ds ⇔ k6=i,j (φkj

(23)

dr 3 +akj φ3kj )(ψik + bki ψik ) = 0, ∀r ∈ D, s ∈ Dr , i 6= j,

feir (xi , yi ) + M (1 − αi ) P P +M j6=i s∈Dr ρrs ij ≥ 0, r ∈ D, i 6= j, Pmrs |+1 rs λijt t=0 rs = ρij , ∀r, s, i, j. Pmst rs rs rs er λrs ij0 fi (xi , yi ) + t=1 λijt gt (Eij ) s rs e f (xj , yj ) ≥ 0, +λ ij,mrs +1 j

(24)

(25)

(26)

(27)

r ∈ D, s ∈ Dr , i, j ∈ In , i 6= j. (15) In the following we are going to develop a corresponding ILP model.

R&I, 2009, No2

ILP Model 2

βij ≤

In order to get an ILP formulation with polynomial number of variables and constraints, all conditions in basic model (17) – (27) have to be formulated as linear restrictions.

Restricting the Placement Parameters

4 X

φrij , βij ≤

r=2

βij ≥

4 X

r ψij ,

r=2

φrij +

r=2

Relations Variables

4 X

4 X

r ψij − 1.

r=2

Between

ε-,

φ-

and

ψ-

In order to ensure that Ri does not overlap Ω if Ri Naturally, we have is not used, i. e. if αi = 0, we define the following inequalities: 0 ≤ εst ∀s ∈ D, t ∈ Ds , i, j ∈ In , i 6= j, (33) ij , −ai ≤ xi ≤ (XE + 2ai )αi − ai , −bi ≤ yi ≤ (YN + 2bi )αi − bi , i ∈ In .

Relations Variables

Between

α-,

φ-

and

(28)

ψ-

(29)

Symmetry conditions (source of reducing the number of variables): 6−r r φrij = φ6−r ji , ψij = ψji , r ∈ {1, . . . , 5}, i, j ∈ In , i 6= j.

(30)

P5

r=1

r ≤ αj , ψij

≥ αi + αj − 1,

sr εrs ij = εji

∀i, j, r, s.

i, j ∈ In , i 6= j.

(36)

Relations Between ε- and ρ-Variables By definition we have rs 0 ≤ ρrs ij ≤ εij ,

Realization of the logical AND: P5 P5 r r r=1 φij ≤ αj , r=1 φij ≤ αi , P5 r i, j ∈ In , i 6= j. r=1 φij ≥ αi + αj − 1, αi ,

(35)

Because of definition:

r 0 ≤ φrij , 0 ≤ ψij , ∀i, j ∈ In , i 6= j, r = 1, . . . , 5.

r r=1 ψij ≤ P5 r r=1 ψij

dr ds 3 3 εrs εrs ij ≤ ψij + bji ψij , ij ≤ φij + aij φij , (34) r ∈ D, s ∈ Dr , i 6= j, ds dr 3 3 εrs ij ≥ φij + aij φij + ψij + bji ψij − 1, r ∈ D, s ∈ Dr , i 6= j,

Lower bounds for φ- and ψ-variables:

P5

Realization of the logical AND:

∀r ∈ D, s ∈ Dr , i 6= j,

(37)

In order to get an ILP formulation for (24), i. e. for (31)

(32)

rs ρrs ij = εij ⇔ P ds dr 3 3 k6=i,j (φkj + akj φkj )(ψik + bki ψik ) = 0, ∀r ∈ D, s ∈ Dr , i 6= j,

we introduce 0/1-variables ρrs ijk by

Moreover, inequalities (19) and (20) have to be fulfilled.

ρrs ijk = 1

⇔

dr 3 (φdkjs + akj φ3kj )(ψik ) = 1, + bki ψik

∀r ∈ D, s ∈ Dr , i 6= j, k ∈ In \ {i, j}.

Relations Variables

Between

β-,

φ-

and

ψ- This can be modelled as follows:

According to basic model (17) – (27) where no βvariables are used the following inequalities are not needed. On the other hand, if it is intended to exploit β-variables then these inequalities yield the relations between β-, φ- and ψ-variables. Realization of the logical AND: 0 ≤ βij , ∀i, j ∈ In , i 6= j,

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ds 3 0 ≤ ρrs ijk ≤ φkj + akj φkj , dr 3 ρrs ijk ≤ ψik + bki ψik , ds dr 3 3 ρrs ijk ≥ φkj + akj φkj + ψik + bki ψik − 1,

(38)

∀r ∈ D, s ∈ Dr , i 6= j, k ∈ In \ {i, j}. Now we have the condition X ρrs ⇔ ρrs ij = 1 ijk = 0 k6=i,j

11

ρrs ij , i 6= j ∈ In , r ∈ D, s ∈ Dr , O(n2 m) constraint selection variables λrs itj , i 6= j ∈ In , r ∈ D, s ∈ Dr , t ∈ IΩ , and (39) O(n3 ) variables ρrs , i 6= j 6= k ∈ In , r ∈ D, s ∈ Dr . ijk Hence, the total number of variables is proportional to n2 · max{n, m}. In the last condition it is assumed that at least two rectangles are available to build a cover, i. e. n ≥ 2. The number of constraints has the same order of magnitude. Moreover, we have

which is modelled as P rs rs εrs ij − ρij ≤ k6=i,j ρijk , P rs rs (n − 2)(εrs ij − ρij ) ≥ k6=i,j ρijk , ∀r ∈ D, s ∈ Dr , i 6= j.

sr ρrs ij = ρji ,

∀r, s, i, j.

(40)

Extensions

and, last but not least, feir (xi , yi ) + M (1 − αi ) P P +M j6=i s∈Dr ρrs ij ≥ 0,

Here we propose directions of further research. r ∈ D, i 6= j,

(41)

ILP Model 3: Non-convex Region Ω

mrs |+1

X

rs λrs ijt = ρij ,

∀r, s, i, j.

t=0

Pmst rs rs rs er λrs ij0 fi (xi , yi ) + t=1 λijt gt (Eij ) s rs e f (xj , yj ) ≥ 0, +λ ij,mrs +1 j

r ∈ D, s ∈ Dr , i, j ∈ In , i 6= j.

(42) If Ω is the union of a finite number of convex polygons, i. e. [ Ω= Ωq where Ωq is convex for all q, (44) (43) q

Feasibility

then, in analogy to [9], for every subset Ωq a complete set of λ-variables has to be introduced. The placement parameters xi and yi and the α-, φ- and ψ-variables are maintained.

In this model, objective function (17) and restrictions (28) – (43), it is possible that no covering exists. For computational purposes it may be better to have An Alternative ILP Model the existence of feasible solutions in the optimization Another way of modelling is as follows. Given the problem. φ- and ψ-values we can obtain the ε-values. For a There are several possibilities to guarantee feasible certain subset Ωq we derive the ρ-values regarding solutions, e. g. by adding artificial rectangles with only these rectangles which are used to cover Ωq . For sufficient high costs, or by weakening some of the every Ωq a set of α-, ρ- and λ-variables is needed. restrictions similar to [9].

The Linear Model Besides the linear objective function (17) and the linear restrictions (19), (20), (22), (23), (25) – (27) of the basic model now we have to add all linear constraints (28) – (43) to get a linear formulation of the CPR problem with continuous and binary variables. In this formulation we have 2n continuous variables xi , yi , i ∈ In , n rectangle selection variables αi , i ∈ In , r , 10n(n − 1) relative position variables φrij and ψij i 6= j ∈ In , r ∈ {1, . . . , 5}, 8n(n − 1) inner corner identification variables ǫrs ij , i 6= j ∈ In , r ∈ D, s ∈ Dr , 8n(n − 1) active inner corner identification variables

12

Restricting the Placement Parameters For every q ∈ Q 0/1-variables αiq are defined. Then, a rectangle Ri , i ∈ In , is used to cover Ω if for at least one q ∈ Q αiq = 1 holds true. S In order to ensure that Ri does not overlap Ω = P q∈Q Ωq if Ri is not used for any subset of Ω, i. e. if q∈Q αiq = 0, we define the following inequalities: P −ai ≤ xi ≤ (XE + 2ai ) q∈Q αiq − ai , P (45) −bi ≤ yi ≤ (YN + 2bi ) q∈Q αiq − bi , i ∈ In .

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Conclusions Two ILP models have been developed for problem CPR. In the first one, the number of variables and constraints is dependent on the size of the target region; in the second model it is polynomially bounded but even large. Investigations to reduce this number as well as numerical experiments are needed. Moreover, alternative formulations can possibly help. References [1] V. S. Anil Kumar and H. Ramesh. Covering rectlinear polygons with axis-parallel rectangles. SIAM J. Comput. vol. 32, no. 6, 2003, pp. 1509–1541. [2] J. E. Beasley. Bounds for two-dimensional cutting. J. Oper. Res. Soc., vol. 36, no. 1, pp. 71–74, 1985. [3] J. E. Beasley. An exact two-dimensional non-guillotine cutting tree search procedure. Oper. Res., vol. 33, no. 1, pp. 49–64, 1985. [4] K. Daniels and R. Inkulu. An incremental algorithm for translational polygon covering.

Technical Report 2001-001,

University of Massachusetts at Lowell Computer Science, 2001. [5] H. Dyckhoff, G. Scheithauer, and J. Terno. Cutting and packing. In M. Dell?Amico, F. Maffioli, and S. Martello, editors, Annotated Bibliographies in Combinatorial Optimization, chapter 22, pp. 393–412. John Wiley & Sons, Chichester, 1997. [6] M. R. Garey and D. S. Johnson. Computers and Intractability – A Guide to the Theory of NP- Completeness. Freeman, San Francisco, 1979. [7] A. Lingas, A. Wasylewicz, and P. Zylinski. Note on covering monotone orthogonal polygons with star-shaped polygons. Information Processing Letters vol. 104, no. 6, pp. 220–227, 2007. [8] G. Scheithauer. One-dimensional relaxations for the problem of covering a polygonal region by rectangles. Preprint MATH-NM-04-2009, Technische Universit”at Dresden, 2009. [9] G. Scheithauer, Yu.

Stoyan, T. Romanova, and A.

Krivulya. Covering a polygonal region by rectangles. Computational Optimization and Applications, Springer, online: http://www.citeulike.org/user/ima/article/4575123 [10] San-Yuan Wu and Sartaj Sahni. Covering rectlinear polygons by rectangles.

Computer-Aided Design of Integrated

Circuits and Systems, IEEE Transactions on. 9(4):377-388.

01/05/1990;

G. Scheithauer 1983 Doctor rer. nat. at Technische Universit”at Dresden, Germany, since 1983 member of the scientific staff at the Institute for Numerical Mathematics, Department of Mathematics, TU Dresden. Selected papers: 1. Zuschnitt- und Packungsoptimierung, Vieweg + Teubner, 2008 (in German, 338 pages) 2. Gomory Cuts from a Position-Indexed Formulation of 1D

R&I, 2009, No2

Stock Cutting. In Bortfeldt et al (eds), Intelligent Decision Support, Gabler Edition Wiss. 2008, pp. 1-14 (with G. Belov, ,C. Alves, J.M.V. de Carvalho) 3. LP-based bounds for the Container and Multi-Container Loading Problem. Int. Trans. Opl. Res., 6 (1999) 199–213. Address: Institute for Numerical Mathematics, Department of Mathematics, Technische Universit”at Dresden, 01062 Dresden, Germany, Field of specialisation: Operational Research, Mathematical modeling, Optimization, Cutting, Packing, Covering Member of ESICUP Yu. Stoyan 1966 Ph. D./Candidat in PhysicalMathematical Sciences, Institute of Cybernetics of National Academy of Sciences of Ukraine, Kiev, 1970 Doctor of Technical Science, Aviation Engineering Institute in Moscow, 1972 Professor for Computational Mathematics, the Kharkov National University of Radioelectronics, 1985 Corresponding-member of National Academy of Sciences of Ukraine, since 1972 Head of Department of Mathematical Modeling at the Institute for Mechanical Engineering Problems of the National Academy of Sciences of Ukraine. Selected papers: 1. Packing of convex polytopes into a parallelepiped, Optimization, vol. 54, 2005, pp. 215235.(with N. Gil, G. Scheithauer, A. Pankratov, I. Magdalina) 2. Packing of Various Radii Solid Spheres into a Parallelepiped. Central Europen Journal of Operational Research, 2003, Vol. 11, Issue 4, pp.389-407. (with G. Yaskov, G. Scheithauer) 3. Packing cylinders and rectangular parallelepipeds with distances between them, Europ. J. Oper. Research 197, 2008, 446-455.(with A. Chugay). Address: Institute for Problems in Machinery, National Ukrainian Academy of Sciences, 2/10 Pozharsky St., Kharkov, 61046, Ukraine Field of specialisation: Computational Geometry, Operational Research, Mathematical modeling, Optimization, Cutting, Packing, Covering Member of ESICUP T. Romanova 1990 Ph. D./Candidat in PhysicalMathematical Sciences, Institute of Cybernetics of National Academy of Sciences of Ukraine, Kiev, 2003 Doctor of Technical Science, Institute of Cybernetics of National Academy of Sciences of Ukraine, Kiev, 2005 Professor for Computational Mathematics, the Kharkov National University of Radioelectronics, since 2003 Senior staff scientist of Department of Mathematical Modeling at the Institute for Mechanical Engineering Problems of the National Academy of Sciences of Ukraine. Selected papers: 1. Phi-functions for complex 2Dobjects//4OR Quarterly Journal of the Belgian, French and Italian Operations Research Societies. vol. 2, no 1, 2004 pp. 69 - 84. (with G. Scheithauer, N. Gil, Yu. Stoyan) 2. Construction of a Phi-function for two convex polytopes, Applicationes Mathematicae, 2002, Vol.29, No 2, pp. 199 - 218. (with Yu. Stoyan, J. Terno, M. Gil, G. Scheithauer) 3. Phi-function for 2D primary objects//Studia Informatica Universalis, 2002, Vol. 2, No 1, pp. 1-32. (with Yu. Stoyan, J. Terno, G. Scheithauer, N. Gil) Address: Institute for Problems in Machinery, National Ukrainian Academy of Sciences, 2/10 Pozharsky St., Kharkov, 61046, Ukraine Field of specialisation: Computational Geometry, Operational Research, Mathematical modeling, Optimization, Cutting, Packing, Covering Member of ESICUP

13

1

Z Domain Delay Subcircuits and Compact Verilog-A Macromodels for Mixed-mode Sampled Data Circuit Simulation M. E. Brinson and H. Nabijou, Member, IEEE

Abstract—Mixed-mode simulation is an important circuit design and system testing tool for established and emerging semiconductor sampled data technologies. This paper describes a number of functional, computationally efficient, Z domain delay models, outlining the role of current and charge equations in the construction of subcircuit and compact Verilog-A delay macromodels. To illustrate the properties of the proposed macromodels a number of Qucs (Quite universal circuit simulator) transient and frequency domain simulation examples are presented. Each of these stresses the use of test and data extraction techniques which are not easily undertaken with the SPICE 2g6 or 3f5 simulators. Index Terms—Mixed-mode sampled data circuit simulation; Functional delay subcircuits; Compact Verilog-A delay macromodels; Qucs (Quite universal circuit simulator)

I. I NTRODUCTION

I

N modern circuit design the term mixed-mode simulation has become synonymous with the analysis and design of integrated analog and digital electronic systems. Early simulators, and indeed some more recent releases of commercial and GNU Public License (GPL) open source packages, were primarily analog circuit analysis tools [1] with polynomial sources (SPICE 2g6 [2]) and non-linear controlled sources (SPICE 3f5 [3]) modeling non-linear components at a functional level. Today, most circuit simulators include a digital simulator that operates synchronously with an analog analysis engine [4], allowing the analysis and testing of complex mixed-mode circuit designs. In terms of sampled data technologies mixed-mode simulation is much more than simply the combination of analog and digital analysis software. Designers are faced with the need to simulate multi-domain systems which include an ever increasing range of electrical and nonelectrical technologies. Moreover, amongst the current general purpose simulators it is not common for packages to include dedicated simulation engines for sampled data system analysis and testing [5]. Hence, accurate and computationally efficient signal delay, signal summing and signal multiplication models are required for use with general purpose circuit simulators. Ideally, such sampled data component models should also be optimized for minimum memory usage. This paper introduces M. E. Brinson is with the Faculty of Computing, London Metropolitan University, London, UK. (phone: 0044-607-2789; e-mail: mbrin72043@ yahoo.co.uk). He is a member of the Qucs development team. H. Nabijou, is with the Faculty of Computing, London Metropolitan University, London, UK.(e-mail: [email protected]). Manuscript received October XX, 2009

14

a number of fundamental functional subcircuit and VerilogA [6] delay models. The proposed models have been implemented and tested as equation defined device subcircuits [7] and compact Verilog-A macromodels [8] using the Qucs (Quite universal circuit simulator) GPL software [9]. The text stresses those model features which are not found in SPICE 2g6 or 3f5 and outlines how sampled data system models can be developed which are suitable for use with any general purpose circuit simulator that allows subcircuits with parameters or compiled Verilog-A hardware description language models. II. F UNDAMENTAL PROPERTIES OF SAMPLED DELAY COMPONENTS

A key component in the simulation of sampled data systems is a delay element with a delay of one sampled data period. In the small signal AC frequency domain an ideal delay is represented by (1). Z −1 = e−jωT = cos(ωT ) − j · sin(ωT )

(1)

The magnitude and phase angle of Z −1 are given by (2). mag(Z −1 ) = 1, angle(Z −1 ) = −ωT

(2)

Similarly, group delay (GD) and the first differential of the group delay (dGD/d ω) are given by (3). −d(angle(Z −1 )) dGD = T, =0 (3) dω dω Where ω is angular frequency in radians per second and T is the sampling period in seconds. These properties should be true for all frequencies over which the delay element is expected to operate. SPICE and other circuit simulators often employ ideal transmission lines as delay elements. Unfortunately, this approach is far from perfect because ideal transmission lines tend to consume large amounts of computer memory and often simulate rather slowly during transient analysis [10]. The speed factor is particularly true for circuit simulators developed from the SPICE 2g6 code when simulating circuits which include ideal transmission lines with short delays; this occurs because the 2g6 version of SPICE restricts the maximum transient analysis time step to half the smallest transmission line delay [11]. In a realistic transient run time both the available memory and simulation speed constraints limit the size of sampled data mixed-mode circuits which can be simulated to around five to ten ideal transmission line delays per circuit [12]. GD =

R&I, 2009, No2

2

R2 n11 R=1

SRC1 G=1 S

C1 C=Cd

R1 R=Rd

R4 R5 C2 R=1 R=Rd C=Cd

SRC3 G=1 n21

n12

n22

A

PIN SRC4 G=1

R6 R=1

nN1

C3 C=Cd

R7 R=Rd

SRC2 G=Mult

RCNStage O I

POUT

Eqn1 Rd=1k Cd=Delay/(nStages*Rd) nStages=N

POUT

DEL1 Delay=T Mult=1

Fig. 1. Delay network subcircuit symbol and circuit consisting of N series cascaded RC stages separated by controlled source buffering stages.

III. C ASCADED RC DELAY NETWORKS AS DELAY ELEMENTS

The circuit schematic illustrated in Fig. 1 is a Qucs subcircuit simulation model of a delay network consisting of N series cascaded RC stages separated by buffering voltage controlled current sources with resistive loads. Each RC stage provides a delay of T/nStages seconds, where T is the total delay of the network, and nStages is the number of cascaded stages. Qucs equation block Eqn1 determines, prior to the start of simulation, the values of components Rd and Cd from subcircuit parameter Delay and the value of nStages. Subcircuit parameter Mult allows the delay output signal amplitude to be scaled, the default value being 1. The RC delay network characteristics are given by (4), (5), (6), and (7) respectively. mag(Z −1 ) =

M ult [1 + A2 ]

nStages 2

angle(z −1 ) = −nStages · arctan (A)

(4) (5)

nStages 1 · ωp [1 + A2 ]

(6)

−2 · ω · nStages dGD = 2 dω ωp3 · [1 + A2 ]

(7)

GD =

Where ωp = 1/(Rd · Cd ) = nStages/T , and A = ω/ωp . Fig. 2 introduces a simple AC test circuit for obtaining the fundamental properties of an RC delay network under test. The Qucs equation blocks listed in Fig. 2 either set up the test conditions (Eqn2 plus the AC1 simulation parameters) or are post simulation data extraction scripts (Eqn6 and Eqn7) for processing output data and theoretical data calculated from (4), (5), (6), and (7). Qucs pre and post simulation data processing features allow equations to be entered in any order, and in one or more Eqn blocks, based on the popular MATLAB

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DEL3 B3 Delay=T LEVEL=1

Equation

Equation PIN

RC3Stage O I

V1 U=1 V

R3 R=1

nN2

ac simulation AC1 Type=log Start=20 Stop=20000 Points=101 Equation

dc simulation

Equation

DC1

Eqn6 gain3=B3.v/A.v Phase3=phase(B3.v)-phase(A.v) MinusPhase3=-Phase3 GD3=-diff(deg2rad(Phase3), W) diffGD3=diff(GD3, W)

Eqn2 Eqn7 T=1/SampleFreq Wp3=nStages3/T SampleFreq=100000 nStages3=3 nStages3O2=nStages3/2 ModH3=PlotVs(K23^nStages3O2, acfrequency) MinusPhaseTheory3=-PhaseTheory3 Int1=unwrap(-arctan(W/Wp3),pi/2,pi) Int2=nStages*rad2deg(Int1) PhaseTheory3=PlotVs(Int2,acfrequency) GDth3=PlotVs(nStages3*K23*WPI3, acfrequency) Int3=-2*W*nStages*K23*K23/(Wp3*Wp3*Wp3) diffGDth3=PlotVs(Int3,acfrequency) WPI3=1/Wp3 K13=(W*W)/(Wp3*Wp3) K23=1/(1+K13)

Fig. 2. Three stage RC delay subcircuit AC small signal test circuit and data extraction equation scripts: sampling frequency set at 100K Hz, analysis frequency range 20 Hz to 20 kHz.

R

[13] / Octave [14] language syntax and the mathematical operators and functions defined in the Verilog-A hardware description language. A set of simulated data plots for the characteristics of one to three RC section delay networks are illustrated in Fig. 3. Table I lists an example Verilog-A analog module code routine for a three section RC delay network. Code line numbers are written in ’{ }’ brackets at the left hand side of each line. In Table I Qucs subcircuit parameters are given in lines {6} and {7}. Verilog-A code lines {10} to {13} determine the values of variables specified in line {8}. Model current contributions are listed in lines {15} to {23}. These entries correspond directly to the circuit structure and component types shown in Fig.1, making translation from Qucs subcircuit schematic to Verilog-A code a straightforward process.

IV. C ASCADED F IRST O RDER RC PAD E´ ALL PASS D ELAY N ETWORKS Although the RC delay networks outlined in section III provide the required low node and component count their delay performance at high frequencies is poor. In the test example shown in Fig. 2 the characteristics of the delay element under test are simulated over the audio band of frequencies. At frequencies above approximately 1 kHz the group delay becomes downgraded, resulting in observable error. Increasing the number of RC sections, or the sampling rate, would of course improve the delay performance but these approaches either increase the number of nodes and components or the simulation time which in turn reduces simulation performance, particularly during transient simulation. A better solution is to choose a network with improved delay characteristics per section. Consider the

15

3

-0.1 Phas (deg)

Mag (dB)

0

-5

-10 -100 b -300 20

100 1e3 1e4 Frequency (Hz)

1e-5

100

1e3 1e4 Frequency (Hz)

100

1e3 1e4 Frequency (Hz)

ω (s^2)

0

5e-6

0 20

dGD/d

Group Delay (s)

-10 20

a

-1

c 100 1e3 1e4 Frequency (Hz)

-5e-11

d

20

Fig. 3. Simulated RC delay subcircuit AC characteristics: graph a; mag(Z −1 ) against frequency, graph b; angle(Z −1 ) against frequency, graph c; GD against frequency, and graph d; dGD/dω against frequency: where the solid lines are for a one stage RC delay network, the dashed lines are for a two stage RC delay network , and the dotted lines are for a three stage RC delay network.

the N section cascaded all pass first order Pad´e delay network shown in Fig. 4. The fundamental electrical characteristics of this delay network are given by (8), (9), (10), and (11) respectively, where ωp = 1/(Cd · Rd ) = 2 · nStages/T , and A = ω/ωp . Fig. 5 shows the simulated characteristics for one to three stage Pad´e all pass delay networks. These graphs clearly indicate the superior performance of the cascaded first order Pad´e network across the audio frequency band. For the three stage network this is achieved however, with 11 nodes and 20 components compared to 8 nodes and 14 components for the equivalent RC delay model. Table II lists an example Verilog-A analog module code routine for a three section Pad´e all pass delay network. The structure of the Verilog-A code routine presented in Table II follows that given in Table I.

mag(Z

−1

)=

  M ult · (1 + 2 · A2 + 4 · A2 [1 +

nStages 2



2·ω angle(z ) = −nStages · arctan ωp · (1 − A2 )   1 + A2 2 · nStages GD = · ωp [1 + 2 · A2 + A4 ] −1

16

(8)

nStages A2 ]

 (9) (10)

dGD −4 · ω · nStages = 3 dω ωp · [1 + 2 · A2 + A4 ]

(11)

V. T RANSIENT SIMULATION OF A Z DOMAIN INTEGRATOR Integrators are a basic building block in the synthesis of active filters and many other important classes of mixed-mode circuit. In this section the performance of the proposed delay macromodels are presented using the Z domain integrator as a test device. In the S domain the transfer function of an integrator is given by (12). H(S) =

1 S

(12)

A discrete approximation of equation (12) can be derived by applying Tustin’s method [15] using (13) to give (14). S=

  2 1 − Z −1 · T 1 + Z −1

  Y (Z) T 1 − Z −1 H(Z) = = · X(Z) 2 1 + Z −1

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(13)

(14)

4

TABLE II V ERILOG -A CODE FOR A THREE STAGE PAD E´ ALL PASS DELAY NETWORK

TABLE I V ERILOG -A C ODE FOR A T HREE S TAGE RC D ELAY N ETWORK {1} {2} {3} {4} {5} {6} {7} {8} {9} {10} {11} {12} {13} {14} {15} {16} {17} {18} {19} {20} {21} {22} {23} {24} {25}

‘include disciplines.vams ‘include constants.vams module PadeDelay3Stage (PIN, POUT); inout PIN, POUT; ‘define attr(txt) (*txt*) parameter real Delay=1e-6 from [1e-20 : inf] ‘attr(info=Delay unit=s); parameter real Mult=1 from [1e-20 : inf] ‘attr(info = Signal gain); real Gd, Cd; // Variables analog begin @(initial_model) // Variable initialisation code begin Gd=1e-3; Cd=Delay*Gd/3; end // Current contributions I(n11) < + -V(PIN); I(n11) < + V(n11); I(n11,n12) < + V(n11,n12)*Gd; I(n12) < + ddt(Cd*V(n12)); I(n21) < + -V(n12); I(n21) < + V(n12); I(n21,n22) < + V(n21,n22)*Gd; I(n22) < + ddt(Cd*V(n22)); I(n31) < + -V(n31); I(n31) < + V(n31); I(n31,n32) < + V(n31,n32)*Gd; I(n32) < + ddt(Cd*V(n32)); I(POUT) < + -Mult*V(n32); I(POUT) < + V(POUT); end endmodule

SRC4 G=1 S

R13 R=1

C1 C=Cd

R1 R=Rx

SRC2 G=2

n11

PIN n12

SRC3 G=2

n22

n12

C3 C=Cd

C2 C=Cd

n21

R6 R=Rx

R4 R=Rd

R7 R9 R=1 R=Rx

R5 R=Rx

n13

n13

R2 R=Rx

R3 R=1

{9} {10} {11} {12} {13} {14} {15} {16} {17} {18} {19} {20} {21} {22} {23) {24} (25) {26} (27) {28} {29} {30}

‘include disciplines.vams ‘include constants.vams module RCDelay3Stage (PIN, POUT); inout PIN, POUT; electrical PIN, POUT; electrical n11, n12, n13, n21; electrical n22, n23, n31, n32, n33; ‘define attr(txt) (*txt*) parameter real Delay=1e-6 from [1e-20 : inf] ‘attr(info=Delay unit=s); parameter real Mult=1 from [1e-20 : inf] ‘attr(info = Signal gain); real Gd, Cd; // Variables analog begin @(initial_model) // Variable initialisation code begin Gx= 1e-9; Gd=1e-3; // Rx=1e9 and Rd=1k; Cd=Delay*Gd/6; end // Current contributions I(n11) < + -V(PIN); I(n11) < + V(n11); I(n11,n12) < + V(n11,n12)*Gx; I(n12) < + V(n12)*Gx; I(n11,n13) < + ddt(Cd*V(n11,n13)); I(n13) < + V(n13)*Gd; I(n21) < + -2*V(n12,n13); I(n21) < + V(n21); I(n21,n22) < + V(n21,n22)*Gx; I(n22) < + V(n22)*Gx; I(n21,n23) < + ddt(Cd*V(n21,n23)); I(n23) < + V(n23)*Gd; I(n31) < + -2*V(n22,n23); I(n31) < + V(n31); I(n31,n32) < + V(n31,n32)*Gx; I(n32) < + V(n32)*Gx; I(n31,n32) < + ddt(Cd*V(n31,n32)); I(n33) < + V(n33)*Gd; I(POUT) < + -Mult*V(n32,n33); I(POUT) < + V(POUT); end endmodule

n23 R8 R=Rd

28 single tone sinusoidal signals each of one volt amplitude and differing fundamental, second and third harmonic frequencies. Signal B3S is the integrator output. The performance of the Z domain integrator can be charted by simulating the circuit over a period of one second. Summers Sum1 and Sum2 shown in Fig. 6 have properties represented by (16).

R11 R=1 POUT

nN3

{1} {2} {3} {4} {5} {6} {7} {8}

nN1 nN2 R10 R=Rx Equation Eqn1 MULT=2*Mult DelayON=Delay/nStages Rx=1e12 Rd=1k Cd=DelayON/(2*Rd) nStages=N

nN3 R12 nN2 R=Rd

PIN

V (out) = GIN 1 · V (in1) + GIN 1 · V (in2)

SRC1 G=MULT

PNStage

POUT

I O DEL1 Delay=T Mult=1

Fig. 4. Delay network subcircuit symbol and circuit consisting of N series cascaded first order Pad´e stages separated by controlled source buffering stages.

Expanding (14) results in (15).   T T · X(Z) + Y (Z) · Z −1 Y (Z) = · X(Z) + 2 2

(16)

Where GIN1 and GIN2 are numerical constants or variables held in Qucs equation blocks. Fig. 7 presents plotted simulation data for the Z domain integrator. In order to show the detail in the input and output waveforms only the results for the first 0.5 seconds of the one second simulation period are displayed in Fig.7. Input and output data are analyzed using the fast Fourier transform technique controlled by the post simulation processing and data extraction script listed in Qucs equation block Eqn2, Fig. 6. Fig. 8 illustrates the large signal frequency domain gain (V (B3S)/V (A)) and phase (phase(V (B3S)) − phase(V (A)) function data extracted from the input and output signal amplitude spectra plotted in Fig. 7.

(15)

A. Relative timing and accuracy of the RC and Pad´e delay networks

Where X(Z) and Y(Z) are the Z domain input and output signals respectively. Illustrated in Fig. 6 is a large signal test circuit suitable for investigating the transient characteristics of the Z domain integrator: input signal A consists of the sum of

Table III shows a set of relative simulation run times for the transient analysis of a series of single stage Z domain subcircuit integrators with identical circuits but differing delay models. All timings are relative to those recorded for a circuit

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5

1

-0.1 angle (Deg)

mag (dB)

0 -1 -2 -3 -4 20

a 100

1e3 Frequency (Hz)

-1 -10 -100 b -300 20 100 1e3 1e4 Frequency (Hz)

1e4

0

5e-6

dGD/d

GD (s)

ω (s^2)

1e-5

c

20

100

1e3 1e4 Frequency (Hz)

-2e-11

-4e-11 20

d 100 1e3 1e4 Frequency (Hz)

Fig. 5. Simulated all pass Pad´e delay subcircuit AC characteristics: graph a; mag(Z −1 ) against frequency, graph b; angle(Z −1 ) against frequency, graph c; GD against frequency, and graph d; dGD/dω against frequency: where the solid lines are for a one stage Pad´e delay network, the dashed lines are for a two stage Pad´e delay network , and the dotted lines are for a three stage Pad´e network.

SUM1 GIN1=TO2 GIN2=1 Freq Sig Gen

A 1

FSG1 Equation

2

SUM2 GIN1=1 GIN2=TO2

DEL1 Delay=T Mult=1

B3S 1 2

P3Stage

I

O

transient simulation TR1 Type=lin Start=0 Stop=Ftime Points=65536 IntegrationMethod=Gear Order=6 InitialStep=1 ps MinStep=DTmin MaxStep=DT

Eqn2 Len=Points dc simulation LenO2=Len/2 DC1 fs=1/(Ftime/Len) Equation fsO2=fs/2 Eqn1 frange=linspace(0, LenO2-1, LenO2)/Len NoSamples=100000 f=fs*frange Points=65536 VOUTB3S=fft(B3S.Vt)/LenO2 DT=Ftime/Points VIN=fft(A.Vt)/LenO2 DTmin=DT/128 PVINMag=PlotVs(mag(VIN),f) Ftime=1 PVINPhase=PlotVs(phase(VIN),f) TO2=T/2 PVOUTB3SMag=PlotVs(mag(VOUTB3S),f) T=Ftime/NoSamples PVOUTB3SPhase=PlotVs(phase(VOUTB3S),f)

Fig. 6. Z domain integrator transient simulation test circuit: sampling rate is set at 100 kHz; Gear integration (order 6) with the maximum step size set as the inverse of the sampling rate.

18

with a single stage RC delay model simulated using the trapezoidal numerical integration rule. The simulation conditions were; sinusoidal input signal = 100 Hz at 1 V peak, finish time = 100s, number of samples = 100000 (sampling period = 10 µs), initial transient analysis step = 1ps, abstol = 1pA, vntol = 1uV, and reltol = 0.001. As expected these results confirm that the transient simulation time increases with the number of stages in a delay model. Selection of explicit or implicit numerical integration routine [16] also affects timing. The implicit Gear algorithm performing the best in the integrator test case. Hence, by carefully choosing the number of stages in an RC or Pad´e delay network a compromise between accuracy and simulation speed is possible. Fig. 9 illustrates the large signal AC transfer characteristics for a Z domain subcircuit integrator constructed around a single stage RC delay network employing an identical sampling rate to that used in the previous tests. Clearly at most frequencies, except for those at the top end of the frequency band, the results are similar to those given in Fig. 8, implying that the single RC delay model can be used without significant loss in accuracy at low frequencies while minimizing simulation run time. Timing tests for Z domain Verilog-A integrators constructed from

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6

A (V)

20

0

B3S (V)

-20

a 0

0.1

0.15

0.2

0.25 Time(s)

0.3

0.35

0.4

0.45

0.5

0.05

0.1

0.15

0.2

0.25 Time (s)

0.3

0.35

0.4

0.45

0.5

0.05

0

b

A spectrum (V)

0

B3S spectrum (V)

0.05

1

c

0

100

0.01 1e-3 1e-4 1e-5 1e-6 1e-7 1e-8

1e3

3e3

1e3

3e3

Frequency (Hz)

d

100 Frequency (Hz)

Fig. 7. Z domain integrator transient simulation characteristics: graph a; input signal A against time, graph b; output signal B3S against time, graph c; amplitude spectra for signal A against frequency, and graph d; amplitude spectra for signal B3S against frequency. 0

0.01

TABLE III R ELATIVE TRANSIENT SIMULATION TIMINGS FOR SINGLE STAGE Z

-20

DOMAIN SUBCIRCUIT INTEGRATORS

-40 -60 Gain

-80

Phase (Deg)

1e-3

-100 -120 -140

1e-4

Delay model type

Number of stages

Number of nodes

Number of components

Explicit Trapezoidal Integration

RC RC RC Pad´e Pad´e Pad´e

1 2 3 1 2 3

4 6 8 5 8 11

6 10 14 8 14 20

1 1.31 2.22 1.45 2.08 2.55

Implicit Gear Integration (Order 6) 0.39 0.67 0.80 0.59 0,67 1.18

-160 3e-5 20

100 Frequency (Hz)

1e3

-180 3e3

Fig. 8. Pad´e three stage Z domain integrator frequency domain characteristics: gain against frequency; solid line theory, crosses simulation, phase against frequency; dotted line theory, circles simulation.

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the code listed in Table I and Table II, using the ADMS (Analogue Device Model Synthesizer) [17] compiler, suggest that the relative performance of the Verilog-A models are similar to their equivalent subcircuits. As a general rule it has been found that highly non-linear Verilog-A device models tend to be computationally more efficient than their equivalent equation defined device subcircuits, resulting in measurable improvements in transient run times.

19

7

0.01

0 -20 -40

Gain

-80 -100 -120

Phase (Deg)

-60

1e-3

-140

1e-4

-160 3e-5 20

100 Frequency (Hz)

1e3

-180 3e3

Fig. 9. RC one stage Z domain integrator: frequency domain characteristics; gain against frequency; solid line theory, crosses simulation, phase against frequency; dotted line theory, circles simulation.

VI. C ONCLUSIONS Although ideal transmission delay lines are often used to model Z −1 functions their characteristics in terms of memory usage and simulation speed are far from ideal for mixedmode simulation of sampled data systems. The delay models introduced in this paper demonstrate that it is possible to construct alternative Z −1 functions from standard electrical components. By extending conventional subcircuit technology to include parameters and non-linear equation defined components it becomes possible to construct delay models based on current and charge equations which translate easily into the Verilog-A hardware description language. An important advantage of this approach is that it allows single or multistage delay functions to be selected which meet the accuracy needed to simulate a specific circuit design whilst maintaining minimal simulation run time.

[7] S. Jahn, and M.E. Brinson “Interactive compact modeling using Qucs equation defined devices”. Int. J. Numer. Model., vol. 21, 2008, pp. 33549. [8] M.E. Brinson, and S. Jahn, “Compact macromodelling of operational amplifiers with equation defined devices”. Int. J. Electronics, vol. 96, 2009, pp. 109-22. [9] M. Margraf, S. Jahn, J. Flucke, R. Jacob, T. Habchi T, M.E. Brinson, et. al. (2003), Qucs (Quite universal circuit simulator). Available http://qucs.sourceforge.net/index.html. [10] R.J. Faehnrich, (1994), SPICE does digital filters, EDN Access. Available http://www.edn.com/archives/1994/092994/20di1.htm. [11] See reference [2] section 6.4, p. 8. [12] Simulating digital filters and systems. Intusoft Newsletter Issue 41, 1995. Available http://www.intusoft.com/nlhtm/nl41.htm. [13] MATLAB. Natick, MA: The MathWorks Inc., 1986. [14] GNU Octave. 1992. Available http://www.gnu.org/software/octave/. [15] A.P Page, and S.L. Smith, “Real-time digital simulation for control systems”, in Proc. of the IEEE, vol. 54, pp. 1802-12, 1996. [16] D.A. Calahn, Computer aided network design. New York. McGraw-Hill, 1972. [17] L. Lemaitre, and B. Gu, “ADMS-a fully customizable Verilog-AMS compiler approach,” presented at MOS-AK meeting Montreux, 2006. Available http://www.mos-ak.org/montreux/posters/17_Lemaitre_MOSAK06.pdf. [18] S. Jahn, M.E. Brinson, H. Parruitte, B. Adouin, P. Nenzi P, and L. Lemaitre, “GNU simulators supporting Verilog-A compact model standardization,” presented at MOS-AK meeting Premstaetten, 2007. Available http://www.mos-ak.org/premstaetten/papers/MOSAK _QUCS_ngspice_ADMS.pdf.

M.E. Brinson received a first class honours BSc degree in the Physics and Technology of Electronics from the United Kingdom Council for Academic Awards in 1965, and a PhD in Solid State Physics from the University of London in 1968. Since 1968 Dr Brinson has held academic posts in Electronics and Computer Science. From 1997 to 2000 he was a visiting Professor of Analogue Microelectronics at Hochschule, Bremen, Germany. Currently he is a visiting Professor in the Faculty of Computing at London Metropolitan University, UK. He is a Chartered Engineer (CEng) and a Fellow of the Institution of Engineering and Technology (FIET), a Chartered Physicist (CPhys) and a Member of the Institute of Physics (MinstP). Dr Brinson joined the Qucs project development team in 2006, specializing in device and circuit modeling, testing and document preparation.

ACKNOWLEDGMENT The material reported in this paper forms part of the work done in response to the MOS Modeling and Parameter Extraction Working Group (MOS-AK) Verilog-A compact modeling standardization initiative [18]. R EFERENCES [1] D.O. Pederson. “A Historical Review of Circuit Simulation”. IEEE Trans. Circuits and Systems, vol. CAS-31, 103-111, 1984. [2] A.R. Newton, D.O. Pederson, and A. Sangiovanni-Vincentelli, SPICE Version 2g User’s Guide. Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA, 1981. [3] B. Johnson, T. Quarles, A.R., D.O. Pederson, and A. SangiovanniVincentelli, SPICE3 Version 3f User’s Manual. Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA, 1992. ´ a B˜urmen. Circuit simulation with SPICE OPUS. [4] Tedj Tuma and Arp´ Boston: Birkhuser, 2009 [5] D. Giannopoulos, S. Wong, and A. Lish. “Functional-level simulation of switched-capacitor circuits with nonideal switches and operational amplifiers”. in Proc. of the IEEE Custom Integrated Conference, San Diago, 1989. p. 21.2/1-21.2/4. [6] Verilog-AMS Language Reference Manual. Acellera, Version 2.2, 2004. Available http://www.accellera.org.

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H. Nabijou received his BSc in Electronic Communications, his MSc in Digital Systems and Instrumentation and his PhD in Statistical Signal Processing from UK universities. His research interests include modeling of non-linear stochastic systems. He is currently an academic member of staff in the Faculty of Computing, and a member of the Center for Communication Technology research, London Metropolitan University, UK. He is a member of the IEEE and a fellow of the Royal Statistical Society. Dr Nabijou has recently joined to the Qucs Development Project, as an associate, working on the modeling of signal processing components and algorithms.

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Optimization Factors in Modeling and Testing Hardware and Semiconductor Defects by Dynamic Discrete Event Simulation Jack H. Arabian 1

Index Terms — Optimization, Semiconductors, Production, Testing, Process, Mapping, Modeling, Simulation, System of Systems, Six Sigma, Estimation.

I. INTRODUCTION

T

ESTING of Hardware and Product in the Semiconductor Production Process presented a challenge to the collection of data to resolve cost and production issues. As described in reference [1], it has been shown that the Process can be modeled and run with respect to maximizing the output of the model for typical parameters of cost, time, and resources. It remained, however to optimize the human resources with respect to maximizing the output of the model. This paper describes an optimizing technique/tool, which can be used for a manufacturing test process identifying defects to predict/estimate and optimize costs, scheduling and needed resources.

II. REQUIREMENTS Given the model described in [1], the following steps were taken: 1. Determine the parameters to be optimized 2. Install the parameters in the model 3. Run the optimization tool [ProcessModel™, Provo, UT 84601] III. PROCEDURE 1. After the mapping of the Semiconductor Manufacturing and Test process, (Figure 1 below), we used a commercial process mapping application, and its built-in optimizer called SimRunner™. In the dynamic model, we wanted to maximize the output of the two different wafer slices (called Dice_1 and Dice_2) after reaching the Dicing step. The Test and Burn-in step was used for costing analysis, but it can be seen that a similar series of steps using the Pass/Reject and Re-Do steps can be used wherever a testing step, e.g., Wafer Test, needs to be performed. 2. For purposes of this paper, the optimizing of the human resources to maximize output suffices to simplify the concept. 3. In [1], we used three scenarios of parameters for Fig. 1. The mapping application conveniently ran the scenarios and automatically calculated the cost and other results. Fig. 1 was reduced in scale to fit on the page, but it can be expanded electronically.

4. Note that for this paper, a human resource pool icon (named “Worker Pool), was added, and each of the process steps were connected to the icon. The metric “S” was designated the variable to be optimized (and minimized) for maximum output as explained above. The SimRunner table shown in Figure 2 demonstrates the inputs required for the optimizer. 5. The simulator was then run several times by the SimRunner optimizer in its search for the parameters which met the requirement. A mathematical equation within SimRunner describing an Objective Function provides the parameter which, when calculated and plotted, provides the insight to the optimum process. The plot of the Objective Function against the eight runs needed to converge on the optimum is shown in Fig. 3. 6. After the run of quantity eight (8) experiments, the optimizer converges on the best solution. Experiment 1 shows the best solution of Minimum quantity four (4) workers from the Worker Pool, and the Maximum NumberOfDice_1=1400.000 and Maximum NumberOfDice_2=1000.000, as shown in Fig. 4. IV. CONCLUSION Process Mapping and Dynamic Time Simulation is very useful for a manufacturing test process identifying defects to predict/estimate costs, scheduling and needed resources. Reference [1] showed the previous outcome of metrics, and this paper shows how to optimize the human resources with the process output. This is another compelling argument for QA engineers to justify up-front costs of JTAG (Joint Test Action Group for boundary scan) or BIST (Built-in Self Test) circuitry in design phases. In addition, there are other advantages to modeling a process, viz. 1. Additional parameters are listed after each simulation run in a longer and detailed comprehensive report (6 pages), which is automatically generated. 2. Additional bar graphs, pie charts, cost summaries, and plots are automatically generated using this technique. 3. Model parameters are exported to a spreadsheet, and global changes can be made as needed in the spreadsheet. Changes are then successfully imported directly into the model to create a new scenario to generate new estimates. 4. This technique becomes immediately extendable to appended systems to create a system of systems (SoS) model, by escalating upwards to a higher architectural level.

1

Manuscript received July 9, 2009. This work was supported by the Jacobs Engineering, Technology Division of Bedford, MA

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21

Fig. 1. Model of the Semiconductor Manufacturing and Testing Process

V. LIVE DEMO For this presentation, a 10-minute live demonstration of SimRunner™ optimizer shows dynamic, graphic animation of the test runs automatically generated until the optimizer’s Objective Function converges on the best solution

Fig. 2. SimRunner Table for Optimizer Inputs

VI. FUTURE WORK This model is generic to many manufacturing and test processes in which defects can occur, as, e.g., hardware defects found in testing on a manufacturing production line. Many other aspects need to be shown, such as importing of global parameters from a spreadsheet instead of tedious insertion of parameters in each step of a long process. Process mapping and dynamic time simulation will also lead to future work in creating a true System of Systems (SoS) model through the ability to connect multiple processes and raise levels of abstraction, which are otherwise not easy to achieve. In conjunction with Quality Assurance and Six Sigma practices, other processes can be similarly treated such as in business (order process, Help desk), finance (transactions), healthcare (claims processing), aerospace (radar tracking, checklist, countdown, communications, command and control) and shipbuilding (welding, supply chain). ACKNOWLEDGMENT The author gratefully acknowledges the support and encouragement of the Jacobs Engineering, Technology Division of Bedford, MA REFERENCES

Fig. 3. Plot of Objective Function vs. Simulator Runs (Experiments)

22

[1] Selected Cost Factors in Modeling and Testing Hardware and Semiconductor Defects by Dynamic Discrete Event Simulation; IEEE Proceedings East-West Design and Test Symposium 2008, Lvov, Ukraine, September 2008. By Jack H. Arabian, Engineering Specialist, Jacobs Engineering & Technology Division, Bedford, MA 01731

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Fig. 4. SimRunner Optimizer Converging on Best Solution As founder of Comparative Management Associates, LLC Jack Arabian provides process mapping, modeling and simulation on a contract, consulting basis. He has trained many corporate groups on the topics of process improvement, process mapping and simulation, software and hardware defect detection and correction, engineering design and applications, manufacturing, & finance. His forthcoming book, Process Modeling & Simulation for All Organizations, will be his fourth, including Computer Integrated Electronics Manufacturing and Testing, and Concurrent and Comparative Discrete Event Simulation, the standard references for manufacturing engineers and designers of automated factories. In a distinguished career with such innovative companies as Westinghouse, Polaroid, Foxboro Company, and Digital Equipment Corporation, Jack led the design and development of highly successful hardware and software products in the aerospace systems industry. He has built, led, and mentored high performance design and engineering teams, and taken technology from the laboratory to the customer, with consistently high levels of success in terms of both product quality and profitability.

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At the MIT Instrumentation Laboratory, Jack played a key leadership role in solving the problem of gyroscope drift in space navigation. The results proved critical to the success of the lunar landing program, including the safe return of Apollo 13 after a crippling explosion, and later to the development of commercial aircraft inertial navigation systems. At both Foxboro Company and Polaroid, Jack developed innovative automated test equipment that allowed the restructuring of complex factory production lines, doubling both production and quality while decreasing time to market by as much as 30%. While at Digital, Jack was instrumental in testing computers through modeling and simulation programs, a technique that developed a reputation and a book on the subject. This technique is now used to enhance and accelerate process development and reengineering. A graduate of Harvard University (B.A., Engineering Sciences and Applied Physics) and Massachusetts Institute of Technology (M.S., Instrumentation), Jack has extensive global experience. He is proficient in five languages, including Armenian, Japanese, Spanish, and French. In addition to his four books, Jack is the author of numerous papers on a wide variety of technical and managerial topics, a frequent after-dinner speaker, and a presenter at leading international conferences, such as the IEEE International Test Conference, and symposia.

23

Iterative Method of Minimization of Arbitrary Boolean Functions of Many Variables Arkadij Zakrevskij

Abstract — An iterative algorithm of minimization of Boolean functions of many variables based on usage of parallel operations above adjacent elements in Boolean space of arguments is offered. It includes the operation of fast finding of elements of characteristic set with small number of neighbors and creation of implicants defined by them. The iterative procedure of application of this operation to sequentially reduced characteristic set and operation of simplification of the obtained conjuncts lead to a correct solution. Index Terms—Boolean function minimization, algorithm, prime implicants, computer ex[eriment

iterative

I. INTRODUCTION The classical problem of minimization of Boolean functions in the class of disjunctive normal forms (DNF) can be formulated as follows. Let us define an arbitrary Boolean function f (x) ≡ f (x1, x2, …, xn) in the standard way by a Boolean vector f with 2n components numbered from left to right, starting with zero. Here the component number k sets the value of the function f on the set of values of arguments representing the generally accepted binary code bk of number k. For example, the following vector f represents the Boolean function f of six variables x1, x2, x3, x4, x5, x6, receiving value 1 on 27 collections of values of arguments constituting the characteristic set M1 = {000000, 000011, 000101, …, 111110} of function f. The ordinal numbers of the appropriate components of vector f are 0, 3, 5, … 62. ----- -- - - -

------------ -- - - -

x -------- --------------- x3 2 x -------- --- -- x 4 - - - - - - - - 5 x6

10010101 00100110 00101101 10110010 | 00010010 01010100 10001001 00111010 x1 Note, that such a vector can be interpreted as a perfect normal form of a Boolean function, which terms are represented by single components of the vector and their codes. For example, the code b10 = 001010 of element f10 defines the complete elementary conjunction

Manuscript received 23 March, 2009. Arkadij Zakrevskij is with the United Institute of Informatics Problems of the National Academy of Sciences of Belarus, 220023, Minsk; e-mail: zakr@tut. by.

24

⎯x1⎯x2 x3⎯x4 x5⎯x6 . The problem consists in finding a DNF, minimized as possible, for the function f presented by a given vector f . Let us remark, that the traditional methods of solving this task need run-time fast growing with growth of the number of variables n, and practically become unacceptable at n > 20, when the number of terms in the perfect DNF is measured in millions [1]. In this connection an original method is offered in the given paper, for obtaining DNF of Boolean functions the number of which arguments can reach 24. The method is based on application of efficient parallel operations above Boolean 2n-vectors offered in papers [2, 3]. One of such operations is the operation of conjunctive symmetrizing the vector f by the variable xi, denoted below as S f ∧ i . At its execution the vector f is divided into 2n-1 couples of components adjacent by the variable xi and both units of each couple gain the value equal to conjunction of the values of these units. Let us remind that adjacent such components of the vector f are named, which correspond to sets of values of arguments distinguishing exactly in one argument. When the number of variables n exceeds 5, it is convenient to represent vector f as a Boolean matrix of the size 25 × 2n-5, presenting its 32-component rows by words in computer memory (that is adequate for the majority of modern computers). Then any two units of vector f adjacent by the variable xi will belong to the same word if i < 6 and to different words otherwise, that is possible to use for acceleration of calculations. II. BUILD-UP OF THE BOOLEAN MATRIX OF NEIGHBORHOOD N At the first stage of the offered method the Boolean matrix of neighborhood N of the size n × 2n is created by means of n-fold application of the operation S f ∧ i. Each row ni of this matrix represents the result of execution of the operation S f ∧ i at a concrete parameter value i (from 1 up to n). The matrix N represents the structure of the characteristic set M1 of function f(x), where this function receives value 1. The element nik of the matrix N receives value 1 if and only if the element fk of vector f equals 1 and has a neighbor by the variable xi which also has value 1. Thus, the row ni of this matrix represents the subset of elements from the set M1, having in the same set neighbors by the variable xi, and the column nk displays, by which variables has neighbors the element from M1 presented by the component fk of vector f.

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Let us illustrate obtaining the matrix N with an example of the same vector f, specifying a random Boolean function of six variables: 10010101 00100110 00101101 10110010 00010010 01010100 10001001 00111010

f

00010000 00000100 00001001 00110010 00010000 00000100 00001001 00110010

n1

00000101 00100010 00000101 00100010 00000000 00010000 00000000 00010000

n2

00000100 00000100 00100000 00100000 00010000 00010000 00001000 00001000

n3

IV. SELECTION OF ELEMENTS WITH SMALL NUMBER OF NEIGHBORS

00010001 00100010 00000000 00100010 00000000 01000100 10001000 00100010

n4

00000101 00000000 00000101 10100000 00000000 01010000 00000000 00001010

n5

00000000 00000000 00001100 00110000 00000000 00000000 00000000 00110000 n6 III. MATRIX REPRESENTATION OF DNF In the similar form, the Boolean vector of solution g and the Boolean matrix of solution D of the same dimension as f and N may be used to represent the required DNF, considered as some collection of intervals of the Boolean space M = {0, 1}n. Some elements of these intervals, by one for each interval, are marked with ones in vector g, and the internal variables of these intervals are shown in columns of matrix D. Considering vectors f and g as sets of the elements of space M marked in them, and matrix N and D as subsets of Cartesian product of sets x and M, we shall formulate obvious A f f i r m a t i o n 1. g ⊆ f and D ⊆ N. In other words, vector g and matrix D can be obtained accordingly from vector f and matrix N by replacement in them some ones with zeros, as it is done in the method circumscribed in this paper. For example, according to that method, vector f 10010101 00100110 00101101 10110010 00010010 01010100 10001001 00111010 is transformed to vector g 10010100 00000110 00101000 10010000 00000010 01000000 10000001 00001000 and matrix N – to matrix D presenting DNF of function f (it will be shown later). In the more known form this DNF is set by a ternary matrix, which columns represent elementary conjunctions (⎯x1⎯x2⎯x3⎯x4⎯x5⎯x6, ⎯x2⎯x3⎯x4 x5 x6 , etc.) 1 0-0-0000-111-1 2 00-0-111100111 3 00011-01101001 4 0011-010010-11 5 01-0110-11-016 011100-0-01010

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The number p of conjunctions in the obtained DNF is equal to the weight of the vector of solution g, and the length of DNF (the total of conjunction ranks) is equal to pn − q, where q is the number of elements in matrix D. Let us remark, that the introduced above Boolean matrices and vectors at program implementation of the offered method are handled in internal cycles and, therefore, should be represented in RAM, that limits their allowable size. Taking into account parameters of mogern PCs, it is possible to affirm that the given method is implemented fast enough if the number of variables of the minimized Boolean function does not exceed 24.

The build-up of a DNF implementing function f is expedient to begin with the search for elements of the solution kernel − obligatory simple implicants of high rank. Let us term obligatory such a simple implicant of function f, which enters anyone shortest DNF of this function. The search is facilitated by preliminary allocation in vector f of elements of characteristic set M 1 with small number of neighbors, as such elements can determine implicants of high rank displayed by elementary conjunctions with many literals. The numbers of neighbors for all elements of vector f with value 1 are presented by the finite-valued vector w: 10010101 00100110 00101101 10110010 00010010 01010100 10001001 00111010 f 0..2.3.3 ..2..22. ..1.23.3 1.62..3. ...2..0. .2.3.2.. 1...3..1 ..332.3. w However, it is more convenient in the long term for program implementation of the subsequent calculations, to sort elements by the number of neighbors and to present the result by a series of Boolean vectors mi in which ones mark elements with i neighbors. For the considered example, at i < 4, we shall receive: 10000000 00000010 00000000 00000000 00010000 00010000 00000101 00000000

00000000 00000000 00000000 00000000 00100110 01000100 00000000 00010000

00000000 00000000 00100000 10000001 00001000 00000000 00000101 00001000

00000000 00000000 10000000 00000000 00010000 00001000 00000010 00110010

m0 m1 m2 m3

It is easy to receive these vectors – rows of the Boolean matrix M, by efficient component-wise operations above rows of matrix N, that essentially accelerates the search for appropriate implicants. V. FINDING OF PRIME IMPLICANTS Let us designate through t k the ternary vector obtained from the Boolean vector b k (the code of element fi ) by appropriation of value "−" to components marked with ones in column nk of matrix N. Vector t k can be interpreted as some interval Intk of the Boolean space M = {0, 1}n, and also as

25

corrsponding elementary conjunction, which can appear a prime implicant of the function f. Af f i r m a t i o n 2. The vector t k represents an obligatory prime implicant of the function f if and only if Intk⊆M 1. A f f i r m a t i o n 3. For each obligatory prime implicant of the function f there exists in matrix N a column nk, appropriate to which ternary vector t k represents this implicant. Obligatory prime implicants of rank n are easily found − they are represented by elements of set M1 not having neighbors. They are enumerated in vector m0 and represented in corresponding columns of matrix N, not containing 1s. Similarly, all obligatory prime implicants of rank n − 1 are enumerated in vector m1 and also represented in appropriate columns of matrix N − containing one 1. The detection of obligatory prime implicants of smaller rank is a little bit more difficult. However, it is easy enough for ranks n − 2 and n − 3, being carried out by means of component-wise operations above some columns of the neighborhood matrix N. A f f i r m a t i o n 4. Assume, that element fk of vector f has two neighbors. Then vector t k represents an obligatory prime implicant of the function f if and only if the component fj of vector f is equal to 1, where b j = b k ⊕ n k. For example, b27 ⊕ n27 = 011011 ⊕ 100001 = 111010, j = 58 and f58 = 1; therefore, ternary vector t 27 = −1101− represents an obligatory prime implicant. A f f i r m a t i o n 5. Let us assume, that element fk of vector f has three neighbors. Then vector t k represents an obligatory prime implicant of the function f if and only n k ≤ n j (the vector n k is covered with vector n j), where b j = b k ⊕ n k. The proof of this assertion is based on the fact, that the vectors b k and b j are opposite elements of the interval Intk of rank 3 and together with their neighbors they cover all eight elements of this interval (see fig. 1). There is a problem of practical expediency of checking the components of vector f for satisfying the conditions formulated in the assertions 4 and 5. Let us assume that a Boolean function f of n variables is preset with probability ½ of having value 1 in its components, independently of one another. Consider now some component with value 1 which has k neighbors. How probable it is, that this component determines an appropriate prime implicant of rank n − k? A f f i r m a t i o n 6. The probability of such an event is equal to 1/2t, where t = 2k − (k + 1). This probability fast tends to zero. For example, at k = 2, 3, 4 and 5 it equals 1/2, 1/16, 1/2048 and 1/67 208 864, accordingly, being independent on n. Therefore, in the offered heuristic algorithm only such single components of vector f are exposed to analysis, the number of the neighbors for which does not exceed three. k

j Fig. 1

26

VI. OBTAINING A PARTIAL SOLUTION In the offered algorithm implicants of high ranks are sequentially found. The result is fixed by introduction of ones into the vector of solution g (at first g = 0), definition of corresponding to them columns of the solution matrix D, and correction of vector f *, representing the set of yet uncovered elements of the characteristic set M1. 1. g := m0, f * := f \ m0 . So the implicants of rank n are found (in the given example there exist two such implicants presented by vectors 000000 and 100110 and defined by elements of vector f with numbers 0 and 38). 2. Here are considered sequentially the elements of vector f, marked both in vectors m1 and f *. For a current element f k the corresponding to it vector b k is taken, which component marked by one in column n k of the neighborhood matrix N, is changed for symbol «−». The result represents a prime implicant of rank n − 1. The vectors g and f * are accordingly corrected: in the first vector one 1 is added, and from the second two 1s are deleted. So in the given example elements with numbers k = 18, 24, 48 and 55 are sequentially considered, to which sets 010010, 011000, 110000 and 110111 correspond and which determine prime implicants of rank n − 1: 01-010, 0110-0, 110-00, 10111. The vector of solution g receives the value 10000000 00000000 00100000 10000000 00000010 00000000 10000001 00000000 g and accordingly (as a result of deleting covered elements − they are marked by underline) the value of the vector f * varies: 00010101 00100110 00001100 00010010 00010000 01010100 00000000 00111010

f*

3. At this stage the elements fk with two neighbors marked simultaneously in vectors m2 and f * are considered sequentially and implicants of rank n − 2 are created. First elements fk satisfying the condition of the assertion 4 are found. Corresponding components of vector g receive value 1, the columns d k of matrix D remain equal to columns n k of matrix N, and elements covered with intervals Intk are deleted from vector f *. If the condition of the assertion 4 is not satisfied, one of two neighbors of element fk is selected. (desirably yet not covered). In the column d k only one corresponding 1 remains and the operation foreseen for an element with one neighbor is fulfilled. In the given example (it appears rather simple) that leads to the final solution − covering all elements of the characteristic set M1, obtaining of the couple of vectors 10010100 00000110 00101000 10010000 00000010 01000000 10000001 00001000

g

00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000

f*

build-up of the matrix of solution D, obtained from N by deleting of one unity in every column marked in vector

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00010000 00100110 00001000 00010000 00010000 01000100 00000000 00001000

m2

and deleting of all unities in the columns which have not been marked in vector g: 00010000 00000000 00000100 00000000 00000000 00000000 00000000 00000000 00000100 00000000 00000000 00000000

00000100 00000000 00000010 00000000 00000000 00000000 00000010 00000000 00000000 01000000 00000000 00000000

00000000 00000001 00000000 00000000 00100000 00000000 00000000 10000000 00000000 00000000 00001000 00000000

00010000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 10000000 00001000 00010000 00000000

d1 d2 d3 d4 d5 d6

4. If the vector f * remains nonzero, the elements with three neighbors marked simultaneously in vectors m3 and f * are considered. The elements satisfying the condition of the assertions 5 are found, and the corresponding implicants of rank n − 3 are entered into solution. At omission of the given condition the implicants of higher rank (n − 1 and n – 2) are found, defined by these elements. As a result of the circumscribed procedure of processing of elements of vector f, having no more than three neighbors, we obtain a set of implicants constituting a partial solution S, and vector f *, representing residual − the collection of uncovered by this solution elements of set M1.

At the first iteration of algorithm the elements of the set M1 with number of neighbors i = 0, 1, 2 and 3 are handled, that is 296 + 2087 + 7180 + 16352 = 25915 elements. The obligatory prime implicants defined by them are found, altogether 296 + 2082 + 1974 + 80 = 4432. The total number of the prime implicants retrieved at the first iteration (together with nonobligatory ones) is equal to 24 379. They are marked in the vector of solution g and the elements covered with them are deleted from the variable residual vector f * (in the beginning equal to f). The number of ones in vector f * becomes equal to 81 910. At the second iteration a new matrix N, representing the relation of neighborhood on elements of the set M1 marked in the residual vector f *, is considered. In this vector the elements having no more than three neighbors in the same vector are discovered, and determined by them implicants are found. Vectors g and f * gain new values. If after that f * ≠ 0, the following iteration is fulfilled. So for the considered example four iterations are fulfilled, before vector f * becomes equal to 0 and all elements of the set M1 appear covered with 61 477 implicants with the following distribution on ranks (for example, there exist 2 458 implicants of rank 19)): 19 − 2 458, 18 − 33 668, 17 − 25 237, 16 − 114. As was already said, not all these implicants appear prime. Therefore two procedures of bringing the obtained solution to correct appearance are in conclusion fulfilled. First of them simplifies implicants, appealing to the initial neighborhood matrix N and deleting from implicants some literals if possible. It brings to a new distribution of implicants on ranks: 19 − 296, 18 − 20 933, 17 − 38 617, 16 − 1 631.

VII. ITERATIVE ALGORITHM The idea of this heuristic algorithm consists in the following. At first it discovers a partial solution for the vector f, then fulfils the same operation for the residual f *, supplementing the set of obtained implicants and accordingly simplifying vector f * (deleting some ones from it). If after simplification vector f * will contain some ones, the following iterations are fulfilled up to that moment, when f * becomes equal to zero. The implicants obtained at that can be not obligatory and even not prime. Therefore in conclusion they are reduced to prime ones (by lowering the rank), and also the obtained doubles are eliminated. Let us demonstrate the algorithm on a concrete example, Let n = 19 and each element of vector f receives value 1 with probability p = 1/4. At this supposition a random vector f with 147 232 elements was generated and the neighborhood matrix N with 219 = 534 288 columns was constructed with following distribution of columns on number of ones in them (N(i) columns contain i ones each): i = 0 1 2 3 4 5 6 N(i) = 296 2087 7180 16352 25357 29868 26913 i = 7 8 9 10 11 12 13 14 15 16 N(i) = 19406 11379 5401 2087 690 172 35 8 1 0

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The second procedure eliminates doubles among the obtained implicants, therefore the number of latter’s is reduced down to 60 972, and their disribution on ranks receives the following appearance: 19 − 296, 18 − 20 933, 17 − 38 353, 16 − 1 390. VIII. COMPUTER EXPERIMENTS The explained above iterated algorithm was software implemented in C ++ and tested on the computer (Pentium IV, 2.8 GHz). In order to make more convenient dealing with Boolean vectors, in which the neighbors for considered elements of vector f are enumerated, the neighborhood matrix N was transposed beforehand. A series of experiments were carried out on a set of pseudo-random Boolean functions with two parameters: the number of variables n and the density of ones r, defining the expected number of ones q in vector f representing Boolean function f (r = 32q / 2n). For example, at r = 16 an absolutely random Boolean function is considered, receiving value 1 on each element of Boolean space with probability 1/2. First of all, the boundaries of practical applicability of the offered algorithm in the space of parameters n and r were defined. The point is, that at a large enough value of parameter r the algorithm can stop the operation after some

27

number of iterations, because the values N(0), N(1), N(2) and N(3) can appear equal to zero, while vector f * will remain distinct from 0. For example, if n=17 and r=15, the algorithm stops after eight iterations, finding only 636 implicants. But at n =17 and r=14 it discovers after 90 iterations 20 077 implicants covering the whole set M1 (after consequent simplification of these implicants and eliminating doubles their number is reduced to 19 811). Therefore, the couple (n, r) = (17, 14) is a unit of the upper bound of the algorithm usage. In table I the basic characteristic of this boundary obtained experimentally is represented. The table strings corresponds to the numbers of variables n (from 4 up to 23) and appropriate to them maximum values of the parameter r, at which the program works correctly. TABLE I

TABLE III n

r

N

C

S

It

T

24 24 24 24

1 2 3 4

1047350 1571532 2095590 2619724

685881 919682 1124293 1297946

15982597 21231157 25759214 29532155

2 2 3 3

1693 4068 10695 24348

Table IV shows some additional results of computer experiments at the number of arguments n = 17. Apparently, at increase of the density of ones r the distribution of the obtained implicants on ranks fast varies in favor of implicants of smaller ranks. TABLE IV

n

r

N

C

S

It

T

4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

16 16 16 16 16 16 16 16 16 16 16 15 14 14 13 12 11 11 10 9

5 16 31 62 138 274 556 1083 2203 4337 8734 16404 31021 61150 114347 212620 392995 786345 1442274 2620069

3 8 14 31 58 107 194 379 735 1414 2780 5313 10181 19811 38007 72343 137215 270642 512529 966357

10 27 62 169 360 744 1513 3355 7127 15057 32266 67324 139827 291507 500357 1220742 2462996 5121875 10255122 20386490

1 1 1 1 2 3 3 4 5 7 12 13 13 90 21 12 10 18 10 8

0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.01 0.03 0.09 0.35 1.01 3.12 24.37 42.26 148 610 2499 8858 31064

The following values are shown in strings of this and other tables: N – the number of ones in vector f (the number of implicants in the perfect DNF of function f), C – the number of implicants in obtained DNF, S – the length of obtained DNF (the total of implicant ranks), Q k – the number of implicants of the rank k in obtained DNF (at k = n, n–1, n–2, n–3, n–4), It – the number of iterations, T – the run-time in seconds. The table II shows the behavior of the algorithm at the number of variables n = 17. It is evident, that the number of iterations It and the run-time T grow at increase of the density of ones r. TABLE II

n

r

N

C

S

It

T

17 17 17 17 17 17 17

2 4 6 8 10 12 14

12285 20427 28594 36507 44756 52999 61150

7856 11117 13761 15621 17348 18691 19811

127689 177205 215604 240722 263178 279341 291507

2 2 3 3 4 7 90

0.27 0.53 1.90 4.04 6.49 8.43 24.52

28

The behavior of the algorithm at the greatest possible for it number of variables (n=24) is shown in table III. At increase of the density of ones r by one the run-time T grows more than twice, reaching 6.8 hours at r = 4.

r

Q 17

Q 16

Q 15

Q 14

Q 13

It

T

2 4 6 8 10 12 14

2283 1147 417 135 41 6 1

5283 8162 8406 6370 3864 1880 684

290 1802 4887 8883 12456 13899 12842

0 6 51 233 986 2896 6224

0 0 0 0 1 10 60

2 2 3 3 4 7 9 0

0.27 0.53 1.90 4.04 6.49 8.43 24.52

IX. CONCLUSION In the offered algorithm of minimization of Boolean functions of many variables (up to 24) the following ideas are implemented: 1) The role of elementary operands is played by Boolean vectors with 2n components representing arbitrary Boolean functions of n variables. 2) The Boolean matrix of neighborhood N by the size n × 2n is created, mapping the structure of the characteristic set M1. 3) With its help prime implicants of four higher ranks are quickly found, coating a part of the set M1. 4) The structure of the residual is represented by a new matrix N, the new implicants of high rank are found, etc. The iterations will stop, when the set M1 becomes empty. 5) Finally, the obtained implicants are transformed to prime ones and any doubles are eliminated. The algorithm is implemented by the efficient program, developed by Nikolaj Toropov from the UIIP of NAS of Belarus. It can appear useful at solution of systems of the Boolean equations, verification of logic circuits and solution of other labor-consuming tasks of the theory of Boolean functions. REFERENCES [1] [2]

[3]

Zakrevskij A. D. Logical design of cascade circuits. − Мoscow, 1981 (in Russian). Zakrevskij A. D. Parallel operations over neighbors in Boolean space. – Proceedings of the Sixth International Conference CAD DD-07, Minsk, 2007. Vol. 2, pp. 6−13. Arkadij Zakrevskij. Programming Calculations in Many-Dimensional Boolean Space // Radioelectronics & Informatics, No 1(40), JanuaryMarch 2008, pp. 19-25.

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Reduction of Hardware Amount for Control Unit with Address Transformer Alexandr A. Barkalov, Larisa A. Titarenko, Alexandr S. Lavrik

Abstract — The method of hardware reduction is proposed oriented on control units and CPLD chips. The method is based on a wide fan-in of PAL macrocells allowing using more than one source of microinstruction address. The method of logical condition replacement is used for optimization of microinstruction addressing block. An example of proposed method application is given. Index Terms—Address transformer, CMCU, CPLD.

C

I. INTRODUCTION

omplex programmable logic devices (CPLD) are widely used for implementation of logic circuits of control units [1]. As a rule, CPLD include macrocells of programmable array logic (PAL) [2], [3]. To design a logic circuit with optimal characteristics, some peculiarities of logic elements in use and a control algorithm to be interpreted should be taken into account. If a control algorithm is represented by a linear graph-scheme of algorithm (GSA), thin it can be interpreted using a model of compositional microprogram control unit (CMCU) [4]. One of the distinctive features of CPLD is the wide fan-in of macrocells [5], [6]. It can be used for increasing of the number of sources for classes of pseudoequivalent operational linear chains [7], [8]. The method is proposed in this article based on the abovementioned feature of CPLD, as well as on the replacement of logical conditions [1]. The aim of this research is reduction of the hardware amount in logic circuit of CMCU due to simultaneous use of more than one code source and the replacement of logical conditions. The task of research is the development of design method resulted in the hardware amount decrease for blocks of microinstruction addressing and microinstruction address transformer.

II. FEATURES OF CMCU WITH MICROINSTRUCTION ADDRESS TRANSFORMER

Let GSA Γ be represented by sets of vertices B and arcs E. Let B = {b0 , bE } ∪ E1 ∪ E2 , where b0 is an initial vertex, bE is a final vertex, E1 is a set of operator vertices, where E1 = M, and E2 is a set of conditional vertices. A vertex

( )

bq ∈ E1 contains a microinstruction Y bq ⊆ Y , where

Y = {y1 ,..., y N } is a set of data-path microoperations [1]. Each vertex bq ∈ E 2 contains a single element of the set of

logical conditions X = {x1 ,..., xL }. Let GSA Γ be a linear GSA, that is a GSA with more than 75% of operator vertices. Let us form a set of operational linear chains (OLC) C = {α1 ,..., α G } for GSA Γ , where each OLC α g ∈ C is a sequence of operator vertices and each pair of its adjacent components corresponds to some arc of the GSA. Each OLC α g ∈ C has only one output Og and the arbitrary number of inputs. Formal definitions of OLC, its input and output can be found in [4]. Each vertex bq ∈ E1 corresponds to microinstruction MIq kept in a control memory (CM) of CMCU and it has an address A bq . The microinstructions

( )

can be addressed using R = ⎡log 2 M ⎤

(1) bits, represented by variables Tr ∈ T = {T1 ,..., TR } . Let

OLC α g ∈ C include Fg components and the following condition takes place: A bgi +1 = A bgi + 1 ,

(

) ( )

(2)

In equation (2) bgi is the i-th component of OLC

α g ∈ C , where i = 1,..., Fg − 1 . If outputs Oi , O j are connected with an input of the same vertex, then OLC α i , α j ∈ C are pseudoequivalent OLC Manuscript received March 7, 2009. A. A. Barkalov is with University of Zielona Gora, Poland. e-mail: [email protected] L. A. Titarenko is with University of Zielona Gora, Poland. e-mail: [email protected] A. S. Lavrik is with Donetsk National Technical University, Donetsk, Ukraine. e-mail: [email protected]

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(POLC) [2]. Let us construct the partition Π C = {B1 ,..., BI }

of the set C1 ⊆ C on the classes of POLC. Let us point out that α g ∈ C1 if

Og , BE ∉ E . Let us encode the classes

Bi ∈ Π C by binary codes K (Bi ) with

29

R1 = ⎡log 2 I ⎤

{

bits and use the variables τ r ∈τ = τ 1 ,...,τ R1

}

(3) for the

encoding. In this case a GSA Γ can be interpreted using the model of CMCU U1 with address transformer (Fig. 1).

α g ∈ C1 in such a manner that condition (2) takes place and the maximal possible amount of classes Bi ∈ Π C is represented by a single generalized interval of Rdimensional Boolean space. Such an addressing needs a special algorithm which should be developed. Let Π C = Π A ∪ Π B , where Bi ∈ Π A if this class is represented by one interval, and Bi ∈ Π B otherwise. The

Fig. 1. Structural diagram of CMCU U1

The pulse Start causes loading of the first microinstruction address into a counter CT and set up of a fetch flip-flop TF. If Fetch = 1 , then microinstructions can be read out the control memory CM. If a current microinstruction does not correspond to an OLC output, then a special variable y0 is formed together with microoperations Yq ⊆ Y . If y0 = 1 , then content of the CT is incremented according to the addressing mode (2). Otherwise, a block of microinstruction address BMA generates functions (4 Φ = Φ (τ , X ) ) to load the next microinstruction address into the CT. In the same time, a block of address transformer BAT generates functions τ = τ (T ) . (5) If the output of OLC α g ∉ C1 is reached, then y E = 1 . It causes reset of TF and operation of CMCU U1 is terminated. Such an organization of CMCU permits decrease of the number of terms in functions Φ from H1 till H 0 , where H1 , H 0 is the number of terms for equivalent Moore and Mealy finite state machines (FSM) respectively. But the block BAT consumes some macrocells or cells of PROM used for implementation of CM. In this article we propose some CMCU U 2 , where H 2 = H 0 and the block BAT

counter CT is a source of the codes for Bi ∈ Π A . If condition Π B = 0/ (6) takes place, then the block BAT is absent. Otherwise, only output addresses for OLC from classes Bi ∈ Π B should be transformed. It is enough R2 = ⎡log 2 (I B + 1)⎤ (7) bits for such an encoding, where I B = Π B and 1 is added to take into account the case when Bi ∈ Π A . Let us point out that some part of these codes can be implemented using free outputs of PROM. Let us use the hot-one encoding of microoperations [2] when CM word has N+2 bits. In this case the CM can be implemented using ⎡ N + 2⎤ R0 = ⎢ (8) ⎥ ⎢ t ⎥ chips with enough amount of cells (not less than M). Obviously, that R3 outputs of PROM are free, where R3 = R0 * t − N − 2 . (9) If condition R3 ≥ R2 (10) takes place, then the CM is a source of the codes for Bi ∈ Π B and the block BAT is absent. This approach permits to decrease the number of PAL macrocells in the logic circuit of block BMA, as well as the number of PROM chips used for the address transformation. Further optimization of the block BMA logic circuit is possible due to the logical condition replacement [1]. In this case the set X is replaced by some set P = P1 ,K PQ , where

{

}

Q 1.5 + 0.5 despite apparently infinite coefficient ∆τ in the original differential equation. Numerical convergence tests have shown that the relative error in the numerically computed electric current (20) remains under 0.1% for the considered ranges of parameter values for the grid size N θ × N τ = 1000 × 4000 . The 2+

program for the numerical simulation was written in Borland C++ Builder 6 and executed on a PC based on Intel Pentium 4 processor at 3GHz with 512MB of RAM. IV. RESULTS The analysis of the dimensionless model reveals that the current response f of the dendrimer to electrode polarisation depends on three parameters being the

36

Fig. 2. Simulated linear sweep voltammograms for K 0 = 106 , θ0 = 0.1 and scan rates (a) σ = 10 −4 and (b) σ = 10 4

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The first regime, characteristic of adsorbed species or thin layer cells, corresponds to low values of σ when the peak current is proportional to the dimensionless scan rate [8]. The peak current under the second regime of unconstrained diffusion encountered under high scan rates is proportional to the square root of the scan rate [8]. This is exemplified in Fig. 4a which shows the cross-section of the surface in Fig. 3 along the log σ axis. Thus the slope of this curve in the range log σ < −2.5 is equal to unity and it is 1/2 for log σ > 2 with a smooth transition from one limiting regime to the other.

Fig. 3. Dependence of peak current on heterogeneous kinetics and scan rate for θ 0 = 0.1

a

The variation of the peak current f p with the normalised heterogeneous rate constant is less pronounced on the scale of Fig. 3, but nevertheless it reveals the reversible ( K 0 → ∞ ) and irreversible ( K 0 → 0 ) kinetic limits for high and low values of K 0 , respectively. This is illustrated in Fig. 4b which depicts the cross-section of the log f p surface from Fig. 3 along the line log σ = −3.5 revealing the sigmoidal transition between the two limiting regimes. It may be observed in Fig. 3 that the transition between the irreversible and reversible limits shifts towards higher values of K 0 with increasing scan rate. This is again conditioned by the relative magnitudes of the kinetic time constant determined by K 0 and the time allocated to mass transport through the dimensionless voltage scan rate σ . In a real experimental situation the only readily measurable parameter is the apparent size of the dendrimer molecule r0 . However, even the determination of this parameter requires the usage of sophisticated instrumentation such as scanning tunnelling microscope. On the other hand, the actual shape of the adsorbed molecule is unknown, which in terms of the assumptions made here implies that the angle θ 0 characterising the extent of dendrimer deformation is unknown. Nonetheless this information may be accessed through electrochemical measurements over a range of voltammetric scan rates followed by a theoretical analysis of the shapes and magnitudes of recorded electric currents. To this end the working surface presented in Fig. 5 provides a means to analyse the peak current data as function of θ 0 and σ . Note here that the values of θ 0 close to π are included for completeness of the results but they correspond to a physically unrealistic situation. In fact, high values of θ 0 represent a virtually flattened molecule which means a complete loss of shape and structure. Hence the current model is not applicable under such extreme conditions. However, the values of θ 0 below ca. 2π / 3 seem

reasonable and thus the respective part of the log f p surface in Fig. 5 may be used for the analysis of experimental data. As in the results presented in Fig. 3 the peak current dependence on σ has two distinct limits the first of which corresponds to the reduction of all active centres within the dendrimer outer shell while the second limit represents unconstrained diffusion. In the first limit, the variation of log f p with θ 0 for a fixed value of σ is a decaying b Fig. 4. Cross-section of surface in Fig. 3 along the line log K 0 = 6 showing two different limiting regimes: “thin layer” regime for low values of σ (slope=1) and unconstrained diffusion for high values of σ (slope = 1/2) – (a); cross-section of surface in (a) along the line log σ = −3.5

function which is explained simply by the reduction of the exposed surface area of the dendrimer and hence the fewer active centres, whose number is proportional to (1 + cos θ0 )σ . In the second limiting situation (i.e. under unconstrained diffusion conditions) the variation of log f p

showing variation between reversible and irreversible behaviour – (b)

R&I, 2009, No2

37

with θ 0 for a fixed value of σ is not monotonic. Indeed, since in this case the dimensionless diffusion layer thickness (relative to the dendrimer radius) is much smaller than sin θ 0 (see above) the overall number of active sites that have been reduced during the voltammetric scan (and the peak current f p ) for very high values of σ is

proportional to sin θ 0 σ −1 / 2 . This is clearly observable from the computed results presented in Fig. 5.

Fig. 5. Dependence of dimensionless peak current on scan rate σ and angle θ 0 characterizing dendrimer deformation upon adsorption on electrode surface in the limit K 0 → ∞

V. CONCLUSION The numerical simulation of diffusion within the thin spherical outer shell of a dendrimer molecule has yielded general results describing the behaviour of the peak current under linear sweep voltammetry. The limiting kinetic regimes identified in this work may be readily used for determining the predominant diffusional regime within the molecular shell from experimental data. Nevertheless, a more accurate determination of the values of main kinetic parameters may require a full curve fitting procedure employing the current model. The physicochemical model considered in this work represents, in fact, a more general paradigm of twodimensional diffusion processes occurring on curved surfaces. Subsequently this paradigm has been extended for a more complicated system involving cluster formation and growth on a spherical surface leading to moving boundary of the diffusion domain and its application to a real biological experiment [11, 12]. This confirms the importance of the present work for different areas of modern science.

38

REFERENCES [1]

L. T. Calcaterra, G. L. Gloss, J. R. Miller, “Fast intramolecular electron transfer in radical ions over long distances across rigid saturated hydrocarbon spacers,” J. Am. Chem. Soc., vol. 105, pp. 670671, 1983. [2] V. Chechik, R. M. Crooks, C. J. M. Stirling, “Reactions and reactivity in self-assembled monolayers,” Advanced Materials, vol. 12, pp. 1161-1171, 1983. [3] E.J. Land, D. Lexa, R.V. Bensasson, D. Gust, T.A. Moore, A.L. Moore, P.A. Liddell, G.A. Nemeth, “Pulse radiolytic and electrochemical investigations of intramolecular electron transfer in carotenoporphyrins and carotenoporphyrin-quinone triads,” J. Phys. Chem., vol. 91, pp. 4831-4835, 1987. [4] C. Amatore, Y. Bouret, E. Maisonhaute, J.I. Goldsmith, H.D. Abruña, “Ultrafast voltammetry of adsorbed redox active dendrimers with nanometric resolution: an electrochemical microtome,” ChemPhysChem, vol. 2, pp. 130-134, 2001. [5] C. Amatore, Y. Bouret, E. Maisonhaute, J.I. Goldsmith, H.D. Abruña, “Precise adjustment of nanometric-scale diffusion layers within a redox dendrimer molecule by ultrafast cyclic voltammetry: an electrochemical nanometric microtome,” Chem. Eur. J., vol. 7, pp. 2206–2226, 2001. [6] C. Amatore, Y. Bouret, E. Maisonhaute, H.D. Abruña, J.I. Goldsmith, “Electrochemistry within molecules using ultrafast cyclic voltammetry,” C. R. Chim., vol. 6, pp. 99–115, 2003. [7] C. Amatore, F. Grün, E. Maisonhaute, “Electrochemistry within a limited number of molecules: delineating the fringe between stochastic and statistical behavior,” Angew. Chem., vol. 42, pp. 4944– 4947, 2003. [8] A. J. Bard, L.R. Faulkner, Electrochemical Methods: Fundamentals and Applications. 2nd edition, John Wiley & Sons, 2001. [9] R.D. Richtmyer, K.W. Morton, Difference Methods for Initial-Value Problems. 2nd edition, Wiley-Interscience, New York, 1967. [10] L.H. Thomas, Elliptic problems in linear difference equations over a network. Watson Sci. Comput. Lab. Rept., Columbia University, New York, 1949. [11] C. Amatore, A.I. Oleinick, O.V. Klymenko, I. Svir. “Theory of longrange diffusion of proteins on a spherical biological membrane. Application to protein clusters formation and actin-comet tail growth,” ChemPhysChem, vol.10, pp. 1586-1592, 2009. [12] C. Amatore, O.V. Klymenko, A.I. Oleinick, I. Svir. “Diffusion with moving boundary on spherical surfaces,” ChemPhysChem, vol.10, pp. 1593-1602, 2009.

R&I, 2009, No2

Optimization of Control Unit with Code Sharing Aleksander A. Barkalov, Member, IEEE, Larysa A. Titarenko, Aleksander N. Miroshkin 1

Abstract — The new design method for compositional microprogram control units with code sharing is proposed. The method targets on reduction in the number of PAL macrocells in the combinational part of control unit. Some additional control microinstructions containing codes of the classes of pseudoequivalent chains are used for operational linear chains modification. Proposed method is illustrated by an example. Various graph-scheme of algorithm (GSA) research results are illustrated with the diagrams. Most desirable GSA characteristics for using proposed method were obtained. Index Terms — Circuit synthesis, flow graphs, logic devices, minimization methods.

blocks EMB in the logic circuit of CMCU. A control algorithm is represented by a graph-scheme of algorithm (GSA) [8, 9]. II. ANALYSIS OF CMCU WITH CODE SHARING Let a control algorithm to be interpreted be represented by a graph-scheme of algorithm (GSA) Г [9]. Let this GSA be characterized by the set of vertices B = {b0 , bE } ∪ E1 ∪ E 2 and the set of arcs E , where b0 is an initial vertex, bE is a final vertex, E1 is a set of operator vertices, and E 2 is a set of conditional vertices. Each operator vertex bq ∈ E1 contains a collection

I. INTRODUCTION A control unit (CU) is one of the important blocks of any digital system [1]. The problem of hardware amount reduction is an important problem connected with implementation of logic circuits of CUs [2]. Peculiarities of a control algorithm to be implemented as well as logic elements in use should be taken into account to solve this problem. In this article we propose a method of this problem solution in case when a linear control algorithm is implemented using complex programmable logic devices (CPLD). We discuss the case when macrocells of programmable array logic (PAL) and embedded memory blocks (EMB) are used in a CPLD chip [3, 4]. In a linear algorithm there are more than 75% of operator vertices [5]. The compositional microprogram control units (CMCU) [5] are widely used for interpretation of linear algorithms. An approach based on existence of pseudoequivalent operational linear chains (POLC) is proposed in [6, 7] for optimization of CMCU with code sharing [5]. But this approach does not decrease the hardware amount for a block of microoperations. The development of this approach is proposed in this article, which is based on coding of collections of microoperations [2]. The aim of this research is CMCU logic circuit optimization due to introduction in the format of microinstruction the special fields with codes of classes of POLCs and collections of microoperations. The task of research is development of synthesis method allowing decrease for the numbers of macrocells PAL and Manuscript received March 7, 2009. Optimization of Control Unit with Code Sharing. A. A. Barkalov is with University of Zielona Gora, Poland. E-mail: [email protected] L. A. Titarenko is with University of Zielona Gora, Poland. E-mail: [email protected] A. N. Miroshkin is with Donetsk National Technical University, Donetsk, Ukraine. [email protected]

R&I, 2009, No2

of

Y (bq ) ⊆ Y ,

microoperations

where

Y = { y1, ..., y N } is a set of data-path microoperations. Each conditional vertex bq ∈ E 2 contains some element xl ∈ X ,

where X = { x1,..., x L } is a set of logical conditions (input signals). A GSA Γ is named a linear GSA [5] if the number of its operator vertices exceeds 75% of the total their number in the GSA. Let the set C = {α 1, ..., α G } be constructed for GSA Г , where α g ∈ C is an operational linear chain (OLC) [5]. Any component b g i of OLC α g ∈ C belongs to the set E1 (i = 1, ..., Fg ) . Each pair of adjacent components b g i , bg i

corresponds

to

the

arc

< bgi , b gi +1 >∈ E ,

+1

where

i = 1, ..., Fg − 1 , g = 1, ..., G . Each OLC α g ∈ C has only

one output O g and the arbitrary number of inputs. Formal definitions of OLC, its input and output can be found in [5]. Each vertex bq ∈ E1 corresponds to microinstruction MI q kept in the cell of control memory (CM) with address Aq . It is enough

R = ⎡log 2 M ⎤

(1)

bits for microinstruction addressing, where M = E1 . Let each

OLC

αg ∈C

include

Fg

components

and

Q = max( F1, ..., FG ) . Let each OLC α g ∈ C be encoded by binary code K (α g ) having

R1 = ⎡log 2 G ⎤ (2) bits and variables τ r ∈ τ be used for such an encoding, where

τ = R1 . Let each component bq ∈ E1 be encoded by binary code K (bq ) having R2 = ⎡log 2 Q ⎤

(3)

39

bits and variables Tr ∈ T be used for this encoding, where T = R2 . The encoding of components is executed in such a

manner that condition K (bgi +1 ) = K (bgi ) + 1 takes place for each OLC α g ∈ C

(4) (i = 1, ..., Fg − 1) . If

condition R1 + R2 = R (5) takes place, then the model of CMCU with code sharing U 1 can be used for interpretation of GSA Г (Fig. 1).

for transforming the OLC codes into the codes of the classes of pseudoequivalent OLC named as a code transformer (TC) [5]. But the TC consumes some resources of the chip in use. In this article we propose to use free cells of CM for this transformation. To reduce the number of EMB in the control memory, we propose to use the maximum encoding of collections of microoperations [2]. III. MAIN IDEA OF PROPOSED METHOD Let C1 ⊂ C be a set of OLC such that their outputs are not connected with the vertex bE . Let us find the partition

Р C = {B1 ,...B I } of the set C1 by the classes of POLC. Let us encode classes Bi ∈ Π C by binary codes K ( Bi ) having RB bits, where (8) RB = ⎡log 2 I ⎤ . Let us use variables v r ∈ V for this encoding, where V = RB .

Fig. 1. Structural diagram of CMCU

U1

In CMCU U 1 , a block of microinstruction addressing (BMA) implements the system of input memory functions for counter CT and register RG:

Φ = Φ (τ, X );

Ψ = Ψ ( τ, X ).

(6)

Let us point out that in the case of CMCU U1 an address of microinstruction is represented as the following one: (7) A(b q ) = K(αg )*K(b q ) , where bq is a component of OLC

αg ∈C

and “*” is a sign

of concatenation. The CMCU U 1 operates in the following order. If Start = 1 , then an initial address (all zeros) is loaded into RG and CT. In the same time a flip-flop TF is set up which causes Fetch = 1 , then microinstructions can be read out of control memory. Each cell of CM keeps microoperations y n ∈ Y and special variables y 0 and y E . If y 0 = 1 , then a current content of CT is incremented, otherwise both CT and RG are loaded from BMA. The first case corresponds to transition from any OLC component except of its output. The second case corresponds to transition from an OLC output. If y E = 1 , then the flip-flop TF is reset, signal Fetch = 0 and operation of CMCU is terminated. It corresponds to transition from the vertex bq ∈ E1 , where < bq , bE >∈ E . Pulse Clock is used for timing of CMCU. Let us point out that OLC α i ,α j ∈ C are pseudoequivalent OLC [5] if their outputs are connected with input of the same vertex of GSA Γ . The hardware amount in logic circuit of BMA can be decreased due to introduction of a special block

40

In the process of CMCU synthesis, an initial GSA Г is transformed and additional variables y 0 and y E are introduced in its operational vertices. Thus, the initial set Y is transformed in the set YC = Y ∪ { y 0 , y E } . Let the set YC includes Q1 different collections of microoperations (CMO). Let us encode each collection Yq by a binary code K (Yq ) having RY bits, where RY = ⎡log 2 Q1 ⎤ . (9) Let us use variables z r ∈ Z for this encoding, where

Z = RY . In this case the control memory includes two blocks [5], namely a block of micromemory (BMM) and a block of microoperation (BMO). The BMM generates functions Z = Z (T ,τ ) , (10) and the BMO generates variables YC = YC ( Z ) . (11) In this article we propose to include the fields K ( Bi ) and in the microinstruction format. These K (Yq ) microinstructions include RI bits, where (12) RI = RB + RY . Both BMM and BMO are implemented using EMBs having t outputs. Assume that each EMB includes q words and

q ≥ max( M , Q1 ) . (13) The block BMM has RY outputs and it is implemented using n1 blocks EMB, where

⎡R ⎤ (14) n1 = ⎢ Y ⎥ . ⎢ t ⎥ In this case, there are R3 free bits in the word of BMM, where R3 = n1t − RY . (15) These free bits can be used for keeping of some part V 1 of the code K ( Bi ) .

R&I, 2009, No2

All bits of K ( Bi ) are generated by the BMM if the following condition takes place: R3 ≥ RB . (16) Otherwise, the block of code transformer (BCT) is used to generate the rest of the bits, R4 , where R4 = RB − R3 . (17) These bits form a part V 2 of the code K ( Bi ) . This approach leads to a CMCU U 2 (Fig. 2).

α 4 =< b10 , b11, b12 > , α 5 =< b13 ,..., b16 > , α 6 =< b17 ,..., b19 > , α 7 =< b20 , b21 > , α 8 =< b22 , b23 , b24 > . Therefore, we can get the following values and sets: number of OLC G = 8 , for their encoding we use R1 = 3 variables from the set τ = {τ 1,τ 2 ,τ 3 } , maximum OLC length is Q = 4 vertexes, for their encoding R2 = 2 variables from the set T = {T1,T2 } is enough, number of operational vertices in the GSA M = 24 , R = 5 bits are necessary for their encoding. Hence, condition (5) takes place and there is possibility to use the code sharing. It is enough RB = 3 variables for encoding of the classes

Bi ∈ Π C . It means that V = {v1, v2 , v3 } . Let us encode OLC α g ∈ C and their components in the K (α 1 ) = 000 , …, K (α 8 ) = 111 , K ( B1 ) = 000 , …, K ( B5 ) = 100 . To satisfy the condition (4), let the first component of each OLC α g ∈ C have code 00, following

way:

the second 01, the third 10, and the fourth 11. It leads to microinstruction addresses A(bq ) shown in Table 1.

Fig. 2. Srtuctural diagram of CMCU

TABLE 1 MICROINSTRUCTION ADDRESSES FOR CMCU

U2

In CMCU U 2 , the block BMA implements functions Φ = Φ(V , X ) , Ψ = Ψ(V , X ) , and the block BCT implements functions V 2 = V 2 (τ ) . The following conditions take places: V 1 ∪V 2 = V ,

(18) (19)

V1 ∩V 2 = ∅ . (22) Functions of other blocks have been already discussed. Let us point out that logic circuits of BMA, CT, RG and TF are implemented using PAL macrocells, whereas circuits of BMM and BMO using EMBs. Logic circuits of BCT can be implemented using either PAL macrocells or EMBs. In this article the following synthesis method is proposed for the CMCU U 2 : 1. Construction of sets C , C1 and Р C for GSA Г . 2. Encoding of OLCs, their components and classes. 3. Encoding of collections of microoperations Yq ⊆ YC . 4. Construction of control memory contents for blocks BMM and BMO. 5. Construction of CMCU transition table. 6. Construction of BCT table. 7. Logic synthesis of CMCU logic circuit. IV. APPLICATION OF PROPOSED METHOD Let a GSA Г1 be represented by the sets C = {α 1,...,α 8 } , where α 8 ∉ C1 , and Π C = { B1,...B5 } , where B1 = {α1 } ,

B2 = {α 2 ,α 3 } , B3 = {α 4 ,α 5 } , B4 = {α 6 } , B5 = {α 7 } , α 1 =< b1, b2 , b3 > , α 2 =< b4 ,..., b7 > , α 3 =< b8 , b9 > ,

R&I, 2009, No2

000

001

010

011

100

101

110

111

b1

b4

b8

b10

b13

b17

b20

b22

01

b2

b5

b9

b11

b14

b18

b21

b23

10

b3

b12

*

b24

*

*

b15 b16

b19

*

b6 b7

*

11

*

*

*

(20) (21)

U 2(Г 1 )

Address 00

From Table 1 we can derive, for example, that A(b5 ) = 00101 , A(b15 ) = 10010 , and so on. Replacement of vertices by corresponding collections of microoperations in Table 1 results in the content of control memory (Table 2). TABLE 2 CONTROL MEMORY CONTENT FOR CMCU

Address 00

01

000

001

010

011

100

101

110

111

y0 ,

y0 ,

y0 ,

y0 ,

y0 ,

y0 ,

y0 ,

y0 ,

y1 ,

y3 ,

y3 ,

y1 ,

y3 ,

y3 ,

y6

y5

y2

y6

y9

y0 ,

y0 ,

y0 ,

y3 ,

y3 ,

y3 ,

y9

y9

y5

y3 ,

y1 ,

y2

y5

y2

y0 ,

y0 ,

y3 ,

y3 ,

y9

y9

y1 , y7

y0 , 10

y4

y3 ,

*

y8

y0 , y8

*

y8

y1 ,

y1 , y4

*

y2 *

*

y1 , y7

y3 , y6

y0 ,

y6 11

U 2(Г 1 )

y2 , yE

*

*

*

Obviously, collections of microoperations are taken from the GSA Г1 , but we do not show it. As follows from Table 2, the control memory includes Q1 = 8 collections of

41

microoperations, namely: Y1 = { y 0 , y1, y 2 } , Y2 = { y 0 , y 3 , y 9 } , Y3 = { y 4 } , Y4 = { y 0 , y 3 , y 5 } , Y5 = { y 0 , y 3 , y 6 } , Y6 = { y1, y 7 } , Y7 = { y8 } , Y8 = { y1, y 2 , y E } . They can be encoded using RY = 3 variables, therefore Z = { z1, z 2 , z 3 } . Let EMB in use have t = 2 outputs, then number of used EMB n1 = 2 . Number of non-used bits R3 = 1 . It means that one bit of the code K ( Bi ) can be generated by the block 2

1

BMM. Let variables v r ∈ V be devided between V and V 1

K ( Bi ) . In our example, the block BMM is represented by Table 3, and the variable v1 is included in the output of OLC α7 . TABLE 3 CONTENT OF BLOCK BMM FOR CMCU

01

001

10

010

11

*

001 001

010 000

U 2(Г 1 )

011 011

100 100

101 000

100

001

011

011

101

100

*

110

*

*

110

TABLE 5 FRAGMENT OF TRANSITIONS TABLE FOR CMCU

Bi B3

K ( Bi ) 010

2

in the following way: V = {v1 } , V = {v 2 , v3 } . It is enough to replace the collections in Table 1 by their codes to specify the block BMM. Each output of OLC α g ∈ Bi is complemented by value of the first bit of code

Address 000 00 000

clear from Table 5. The number of such a table rows H is determined by the number of terms in system of generalized formulae of transitions. In our case we have H = 11 .

000

110 111 100 001 110 v1 100

010

*

111

*

*

*

101

U 2(Г 1 )

bq

A(bq )

Xh

Φh

Ψh

h

b17

10100

x2

–

D1 D3

6

b20

11000

x 2 x3

–

D1 D2

7

b18

10101

x 2 x3

D5

D1 D3

8

This fragment describes the transitions for class B3 , starting from the sixth term of system (23). The table of transitions is used to derive functions (18)-(19), having the following terms ⎛ RB ⎞ Fh = ⎜⎜ ∧ v rlrh ⎟⎟ ⋅ X h ( h = 1,..., H ) . (24) ⎝ r =1 ⎠ In system (24), the symbol l rh stands for value of the bit r of code K ( Bi ) from the line h of the table: l rh ∈ {0,1} , v r0 = v r , v1r = v r ( r = 1,.., R B ) . For example, the following system can be derived from Table 5: D1 = F6 ∨ F7 ∨ F8 = v1v 2 v3 ; D2 = F6 ∨ F8 = v1v 2 v 3 x 2 ∨ v1v 2 v3 x 2 x 3 ; D3 = F8 = v1v 2 v3 x 2 x3 .

The table of BCT includes columns α g , K (α g ) , Bi ,

The block BMO is specified by a table with columns K (Yq ) , Yq , q . This table is constructed in a trivial way

K ( Bi ) , V g2 . In our example, Table 6 represents the block

(Table 4).

BCT. TABLE 4 CONTENT OF BLOCK BMO FOR CMCU

TABLE 6 SPECIFICATION OF BLOCK BCT FOR CMCU

U 2(Г 1 )

U 2(Г 1 )

K (Yq )

Yq

q

K (Yq )

Yq

q

αg

K (α g )

Bi

K ( Bi )

V g2

g

000

y 0 , y1 , y 2 y 0 , y3 , y 9 y4 y 0 , y3 , y5

1

100

5

B1

000

–

1

101

001

v3

2

110

B2

001

3

010

v3

3

111

B2

001

4

α1 α2 α3 α4 α5 α6 α7 α8

000

2

y0 , y3 , y6 y1, y 7 y8 y1, y 2 , y E

011

B3

010

v2

4

100

B3

010

v2

5

101

B4

011

v 2 v3

6

110

B5

100

–

7

111

B6

–

–

8

001 010 011

6 7 8

To construct the table of transitions for CMCU U 2 , it is necessary to construct the system of generalized formulae of transitions [4] for classes Bi ∈ Π C . Let the following system exist for our example: B1 → x1b4 ∨ x1b8 ; B2 → x3b10 ∨ x3 x 4 b13 ∨ x3 x 4 b17 ; B3 → x 2 b17 ∨ x 2 x3b20 ∨ x 2 x3b18 ;

(23)

B4 → b20 ; B5 → x1b22 ∨ x1b11. Such a system is the base for construction of CMCU transition table including the following columns: Bi , K ( Bi ) , bq , A(bq ) , X h , Φ h , Ψh , h . The purpose of each column is

42

Remind that the variable v1 is generated by the block BMM. In the same time, there is no code K ( B6 ) because α 8 ∉ C1 . Obviously, this table specifies blocks EMB. If the logic circuit of BCT is implemented using PAL macrocells, then Table 6 corresponds to Karnaugh maps for function v r ∈ V 2 . To optimize system (20), we should encode OLC α g ∈ C1 in the optimal way. The well-known method

R&I, 2009, No2

ESPRESSO [1], for example, can be used for such an encoding. We do not discuss this task in our article. Implementation of the logic circuit of CMCU U 2 is reduced to implementation of systems (18)-(19) using PAL macrocells, and tables similar to Table 3, Table 4, and Table 6 using EMB. To solve this task, a designer can use either standard tools [4] or some known methods [8]. We do not discuss this step also. Let us point out that the control memory of CMCU U 1(Г 1 ) includes 32*12=384 bits (if t = 2 ), and CMCU transition table includes 17 lines. In the CMCU U 2(Г 1 ) , the BMM includes 32*4=128 bits, the BMO requires 8*11=88 bits, and the BCT consumes 8*2=16 bits. Therefore, the control memory of CMCU U 2(Г 1 ) uses 232 bits of memory, and its transition table has H = 11 lines. It means that the CMCU U 2(Г 1 ) requires 1.5 times less of the memory, and its block BMA includes 1.54 times less amount of terms.

REFERENCES [1] [2] [3] [4] [5] [6]

[7]

[8] [9]

V. CONCLUSION In this article we propose the method oriented on decrease for the number of macrocells in the logic circuit of CMCU. The method is based on including the field with code of class of pseudoequivalent OLC into the microinstruction format. The size of CMCU control memory is decreased too due to maximal encoding of collections of microoperations. To decrease the number of macrocells in the block of microinstruction addressing, the special code transformer is used. It transforms OLC codes into codes of their classes. This block can be absent it condition (16) takes place. In this case, the transformation is executed by CMCU block of micromemory. But such an approach leads to the CMCU U 2 with less performance than this characteristic of CMCU with code sharing. Let us point out that reduction of the number of the macrocells in logic circuit can result in decrease of its levels. It can compensate the negative effect of the memory splitting by two blocks. We made some examples of synthesis using the standard package WebPack. The results show that the number of macrocells is decreased up to 30%, and the number of required memory blocks are decreased up to 50%. Comparison is given for CMCU U 1 and U 2 . In the same time, the number of levels in logic circuit of CMCU U 2 is decreased up to 2-3. Let us remind, that the proposed method can be applied only for linear GSA, when condition (5) takes place. The scientific novelty of proposed method is determined by use of the classes of pseudoequivalent OLC and free resources of EMB for decreasing the number of macrocells in block of microinstruction addressing. Besides, application of encoding of collections of microoperations allows decrease for required memory resources. The practical significance of the method is determined by decrease for the number of macrocells and EMB in CMCU logic circuit, It allows to design the circuits with less amount of hardware in comparison with known control units oriented on linear GSAs.

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De Micheli G. Synthesis and Optimization of Digital Circuits. – NY: McGraw-Hill, 1994. – 636 pp. Barkalov A.A., Wegrzyn M. Design of Control Units with Programmable Logic. – Zielona Gora: UZG Press, 2006. – 150 pp. Macrocell Configurations in CoolRunner XPLA3 CPLDs. http://www.xilinx.com/support/documentation/application_notes/xa pp335.pdf Kania D. Two-level logic synthesis on PALs // Electronic Letters. – 1999, № 7. – pp. 879 – 890. Barkalov A., Titarenko L. Logic Synthesis for Compositional Microprogram Control Units – Berlin : Springer, 2008. – 272 pp. Barkalov A.A., Kovalyov S.A., Bieganowski J., Miroshkin A.N. Synthesis of control unit with code sharing and modified linear chains. Machinebuilding and Technosphere XXI // Proc. of XV Int. Scientific Conf. Sevastopol 15-20 September 2008. – Donetsk: DonNТU, 2008. Vol. 4. – P. 54-59. (in Russian). Barkalov А.А., Krasichkov А.А., Miroshkin А.N. Control Device Synthes with code devising and modification of operator line chains. Sc. Trans. of Donetsk National Technical University. Series "Informatics, Cybernetics and Calculate Techniques". Issue 9 (132) – Donetsk: DonNТU. – 2008. – P. 183-187. (in Russian). Solovjev V.V. Digital circuit design with CPLD. – Moscow: Hot Line-Telecom, 2001. – 636 pp. (in Russian) Baranov S. Logic Synthesis for Control Automata – Boston: Kluwer Academic Publishers, 1994 – 312 pp. Aleksander A. Barkalov – Doctor of Science, Professor of DonNTU (Ukraine), Professor of University of Zielona Gora, Poland. Dr. Barkalov’s scientific interests: digital control units, SoPC Address: Campus A, Budynek Dydaktyczny / A-2 prof. Z. Szafrana str. 2, 65-516 Zielona Gora E-mail: [email protected]

Larysa A. Titarenko - Doctor of Science, Professor of Kharkiv National Univercity of Radioelectonics (KNURE), Professor of University of Zielona Gora, Poland. Dr. Titarenko’s scientific interests: Digital, adaptive and spatial-time processing of signals in telecommunication. Management and control in communication networks Research of modern digital telecommunication systems and nets.

Aleksander N. Miroshkin – Assistant of Donetsk National Technical University. Scientific interests: digital control units.

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Statistical Properties of Spread Spectrum Signals Synchronization System Inna O. Tkalich, Helen V. Kharchenko and Yegor I. Vdovychenko

Abstract—In this paper the method of digital spread spectrum signals (DSSS) processing concluding digital matched filtration, synchronization and decision making about transmitted signals, FPGA-usage orientated from different vendors is presented. Special attention is attended to the research of synchronization algorithms in the non-Gaussian and nonstationary noise influence conditions. The system synchronization probability-timing characteristics are obtained. Index Terms— Density of distribution, digital recirculator, DSSS, FPGA, synchronization system

I. INTRODUCTION uring receiving signals with long base, one of the main problems is providing high quality characteristics for the synchronization system [1]. It is known that decreasing locking in synchronism time is possible using spread spectrum signals and two-step procedure of synchronization [1]. At once, in the first stage clocking synchronization is provided which consists in determination signal elements convolution monitoring meaning moments, which are the signals either with base [2]

D

II. DSSS SYNCHRONIZATION In the actual communication systems the synchronization subsystem is functioning in the conditions of a prior uncertainty, relatively to the receiving signal parameters, nonGaussian and nonstationary noise influences, and that’s essentially limits the possibility of providing. In the connection with this, it is necessary to use synchronization algorithms efficiency of those would not be dependent on receiving signal intensity and also faintly dependent on kind of noise distribution density parameters for the complex influence, i.e. – on rabastic algorithm. Clocking synchronization procedure concludes, firstly, in the strong correlation zone determination of spread spectrum signal receiving element and, secondly, in the timing position estimation for the maximum element of convolution, where the maximum signal-to-noise ratio level is detected. For the strong correlation zone determination the following algorithm is offered. The signal clocking interval is divided by L subintervals, each one of them has its own number (address) (see fig.1): a – conditional beginning of signal interval, b – conditional beginning of the next signal interval.

BEL=τEL·∆FEL, where τEL – element duration, sec; ∆FEL – effective element spectrum bandwidth. In the second stage the spread spectrum signal matched filtration is performed using signal samples which had been taken in the points of time corresponding signal elements meaning moments. Then, the spread spectrum signal beginning (ending) corresponding meaning moments are determined – i.е. frame synchronization is performed. Manuscript received April 14, 2009. This work was supported by Ukraine Central State Designs Bureau “Proton” (Ministry of Industrial Policy of Ukraine), Kharkov National University of Radio Electronics, A.Y.Usikov IRE NAS of Ukraine. Inna O. Tkalich – Researcher of Radio-electronic systems department, Kharkov National University of Radio Electronics, Ukraine (phone: 370-050963-0332; e-mail: [email protected]) Helen V. Kharchenko – Phd-student of A.Y.Usikov IRE NAS of Ukraine (phone: 370-095-331-1420; e-mail: [email protected]) Yegor I. Vdovychenko – Software engineer of Ukraine Central State Designs Bureau “PROTON” (phone: 370-095-827-6431; e-mail: [email protected])

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Fig. 1. The conditional partition of signal interval

It is determined and remembered the address of jth subinterval where the observed process maximum value is situated. If to suppose that the signal convolution element is detected in the jth subinterval, then with probabilities q exactly in this subinterval will be found the observed process maximum value. For the given trustworthiness providing of a sound decision about subinterval address, where the element convolution is presented, the procedure is repeated as long as the address of jth subinterval (or any others subinterval) is repeated m times. Once, the probability of the false synchronization is equal to m ⎛1⎞ (1) Pfs = ⎜ ⎟ , ⎝L⎠ the composite probability of strong correlation interval determination for k intervals is defined by the expression [1]:

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⎧ ⎪0 k < m; ⎪⎪ PΣ (k) = ⎨qm + (k − m)Q m ≤ k ≤ 2m; ⎪ k −2m ⎪qm + (k − m)Q − Q ∑ PΣ (m −1 + j) k > 2m, ⎪⎩ j=1

(2)

where Q = qm (1-q); q – is a probability of a sound decision about meaning moment position in the jth interval. Obviously, the signal energy to power noise spectral density ratio, in the moment of signal element convolution maximum is not high, as far as for the signal receiving in general it is supposed following matched filtration and for the fast and reliable jth subinterval detection is necessary to take steps providing rising element energy ratio to power noise spectral density N0 E ηEL = EL . N0 At the same time it is necessary to create conditions for the frame synchronization. For this purpose, it is proposed to use the device with structural schema presented in figure 2, where: MF“1” – the filter matched with signal element corresponding transmitted logical “1”; MF“0” – the filter matched with signal element corresponding transmitted logical “0”; SLD – square-law detector of envelope.

Fig. 3. Differential channel of synchronization

the cumulative function, in the absence of a signal, equals [4] Ψ (t) = − ln (1 + β2 ⋅ t 2 ) ,

(6)

where β = 2σ2. Cumulants of the i-order, calculated according to expression (6) may be defined as [4] ⎧χ1 = 0; ⎪ 2 ⎪⎪χ 2 = 2β ; χ k = ⎨χ = 0; 2n-1 ⎪ ⎪χ = (2n)! β2n , ⎪⎩ 2n n

(7)

where n = 1, 2,… . Cumulants possess two important properties, which allowing executing calculation of cumulants any order for the sum of independent random variables with any weighting factors [9]: 1) The cumulant of a k-order for the multiplication of a random variable y by a constant a is equal to χ k (ay) = a k χ k (y) (8) 2) The cumulant of an independent random variables sum is defined by expression N

N

n =1

n =1

χ k (∑ y n ) = ∑ χ k (y n )

(9)

If random variables yi are identically distributed Fig. 2. Square-law detector of a signal envelope N

In the absence of a signal in the output of the matched filter (see fig. 2) [6] instant values of observable process are distributed by the normal law [5] with a variance σ 2 = N 0 ⋅ E EL W(x) =

1

−

X

2

2 σ2

(3) 2πσ In the output of the square-law detector the density of distribution of a signal envelope in the reference moments of time ti is distributed by the exponential law, U − 1 2 W(U = x 2 ) = 2 e 2 σ , (4) 2σ and the difference of exponentially distributed random values (see fig. 3) is distributed according to Laplace’s law (double exponential distribution) e

W(y = U 2 − U 2 ) =

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− 1 e 2 4σ

y 2 σ2

,

(5)

χ k (∑ y n ) = Nχ k (yi )

(10)

n =1

In consideration of specified above, it is simple to obtaine cumulants of any order in the output of memory device with exponential weight function (recirculation system) ∞

ZШ = ∑ d l yl ,

(11)

l=0

and according to expressions (7) - (9) and (11) the cumulants will be equal ∞ (2n)! 2n (2n)! 2n ∞ l (12) χ 2n = ∑ d l β = ⋅β ⋅ ∑ d n n l=0 l=0 when d < 1 ∞ 1 d l = 1 + d + d 2 + ... = ∑ 1− d l=0 and 1 (2n)! 2n (13) χ 2n = ⋅ ⋅β , 1− d n where n = 1, 2, … .

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Under central limit theorem, the distribution of a sum of independent random variables converges to the normal law of distribution. The degree of convergence can be appreciated by coefficient of skewness χ3 (14) k= 3 (χ 2 ) 2 and by kurtosis χ (15) γ= 42 (χ 2 ) For random variable Z, under (7), (14) and (15) follows ⎪⎧ k Z = 0; (16) ⎨ ⎪⎩ γ Z = 3 (1 − d). From expression (16) follows, that at 0.97 ≤ d