J Comput Electron (2010) 9: 108–113 DOI 10.1007/s10825-010-0336-5
Random variability modeling and its impact on scaled CMOS circuits Yun Ye · Samatha Gummalla · Chi-Chao Wang · Chaitali Chakrabarti · Yu Cao
Published online: 27 October 2010 © Springer Science+Business Media LLC 2010
Abstract Random variations have been regarded as one of the major barriers on CMOS scaling. Compact models that physically capture these effects are crucial to bridge the process technology with design optimization. In this paper, 3-D atomistic simulations are performed to investigate fundamental variations in a scaled CMOS device, including random dopant fluctuation (RDF), line-edge roughness (LER), and oxide thickness fluctuation (OTF). By understanding the underlying physics and analyzing simulation results, compact models for random threshold (Vth ) variations are developed. The models are scalable with device specifications, enabling quantitative analysis of circuit performance variability in future technology nodes. Using representative circuits, such as the inverter chain and SRAM cell, key insights are extracted on the trend of variability, as well as the implications on robust design. Keywords Threshold variation · Random dopant fluctuation · Line-edge roughness · Oxide thickness fluctuation · Atomistic simulation · Predictive modeling · Inverter · SRAM performance variability
induced variations. Process-induced variations arise from the imperfection in silicon fabrication, and vary from foundries to foundries. On the other hand, intrinsic variations are limited by fundamental physics. They are inherent to CMOS structure, considered as one of the ultimate barriers to continual scaling of CMOS devices. The primary intrinsic variations include random dopant fluctuation (RDF), line-edge roughness (LER) and oxide thickness fluctuation (OTF), as illustrated in Fig. 1. • RDF: This well known effect is caused by the uncertainty in charge location and numbers, such as the discrete placement of dopant atoms in the channel region that follow a Poisson distribution [2]. As the device size scales down, the total number of channel dopants decreases, resulting in a larger variation of dopant numbers, and significantly impacting threshold voltage (Vth ). • LER: Related to gate material, LER is the distortion of the gate edge, which is induced by gate etching and the lithography process [3]. Although the etching technology has been improved, the trend of LER induced Vth variation does not scale accordingly [4]: due to increasingly severe
1 Introduction CMOS technology is expected to enter the 10 nm regime for future integrated circuits (IC) [1]. Such aggressive scaling leads to vastly increased variability, posing a grand challenge to robust IC design. Variations in CMOS are often divided into two types: intrinsic variations and processY. Ye () · S. Gummalla · C.-C. Wang · C. Chakrabarti · Y. Cao School of Electrical, Computer and Energy Engineering (ECEE), Arizona State University, Tempe, AZ 85287-5706, USA e-mail:
[email protected]
Fig. 1 Fundamental variations in a CMOS device
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short-channel effect, such as DIBL, LER contributes to a significant amount of Vth variation. • OTF: It is induced by the atom-level interface roughness between silicon and gate dielectric [5]. Such a surface roughness causes the fluctuation of the voltage drop across the oxide layer, further changing Vth . OTF becomes more pronounced as gate dielectric thickness (tox ) is approaching the height of the atoms. In this work, atom-level TCAD simulations incorporating these three intrinsic variations are performed to develop scalable variation models. Leveraging long-range potential based equivalent charge density model [6], RDF effect is able to be simulated in a commercial TCAD tool [7]. Moreover, the geometric roughness due to LER and OTF is generated by Inverse Fourier Transform (IFT) from the power spectrum [5, 8], which is further integrated into the TCAD simulation. Based on the simulation results and physical derivations, a set of predictive models are developed to capture intrinsic Vth variability in scaled CMOS devices. These predictive models indicate the scaling trend of random Vth variations, and help benchmark the impact on circuit performance.
Fig. 2 Simulated Vth variation due to combined sources
advanced process technology, the correlation length of LER (Wc ) is set as 10 nm [11] and its standard deviation (σ LER) equals to 0.5 nm [1, 11]. The correlation length (λ) of oxide surface roughness is assumed as 2 nm [8], and the height of one silicon atom layer (H ) is 2.71 Å to simulate the atom-level OTF [5, 8]. 2.2 Total Vth variation 200 iterations of TCAD simulations are performed in each case. Assuming that σ Vth due to these three sources is independent on each other, the total σ Vth is obtained as (2): 2 2 2 2 = σ Vth,(RDF) + σ Vth,(LER) + σ Vth,(OTF) σ Vth,(total) 2 + σ Vth,(RTN)
2 Atomistic simulation of random CMOS variations 2.1 Simulation setup In this work, TCAD Monte Carlo simulations are performed at first. Then the Vth variations are extracted from TCAD results for compact modeling. The parameters and nominal IV characteristics are calibrated with 22 nm Predictive Technology Model (PTM) [9]. The gate width is set to be 15 nm. To be realistic, a retrograde doping profile is applied to suppress RDF and DIBL effects [9]. Dopant fluctuations in both channel and source/drain regions are taken into account. To simulate discrete dopants in the silicon substrate, an equivalent doping density profile is applied as shown in Fig. 1 [6, 10]: ρ(r) =
qkc3 sin(kc r) 2π 2 (kc r)3
(2)
Figure 2 validates this equation. From TCAD simulation results, RDF is still the major source at the 22 nm node, while OTF is the second contributor to Vth variability. LER induced variability is relatively small, due to better control in advanced etching process, as well as the retrograde doping with high peak concentration.
3 Compact modeling of random Vth variations Based on the customized 3-D atomistic simulation result, a suite of scalable models is derived in this section. From first principles, the variance of Vth is modeled as functions of key device parameters, such as Nch and tox . 3.1 RDF
(1)
where kc is the inverse of screening length, and r is the distance to the center of atom. In the simulations we treat kc as a fitting parameter. The coefficient of the expression on the right side in (1) is normalized such that the integral of the doping density over the entire space becomes unity as suggested by [7] and [10]. Such a fitting keeps our method consistent with Sentaurus simulation under nominal uniform doping. For random geometry change, the gate edge profile of LER is generated by using IFT [8]. To track the trend of
In our 22 nm simulation, σ Vth due to body RDF is 35.2 mV, which is indeed the dominant one among all variations (Fig. 2). Vth variation due to RDF is expressed as [12]: Nch Wdep q × 1.2 (3) σ Vth = CINV 3W L where W , L, Nch , Wdep are the channel width, channel length, effective channel doping (Nch ) and depletion width respectively. In this model, the non-uniformity along lateral directions and the fluctuation of Wdep are ignored and thus, a factor of 1.2 is used to correct the result. By expanding the
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Fig. 3 (a) The dependence of LER induced σ Vth on Nch and tox ; (b) Vds dependence of LER induced σ Vth
Wdep term and ignoring other second order terms, a more explicit expression is obtained: 1 toxe 2εSi Nch 4 q σ Vth(RDF) = C1 √ q 3W L εox
(4)
where C1 is a fitting parameter accounting for surface potential and the correction term; tox , εSi , εox , and q are the equivalent oxide thickness, permittivity of silicon, permittivity of the oxide layer, and elementary charge, respectively. Equation (4) suggests that RDF induced Vth variation is propor0.25 . Note that in this work other potential tional to tox and Nch RDF related variation sources, such as RDF induced mobility variation [13], have not been included. Upon the availability of atomistic simulation tools or experimental data, our methodology is able to cover those additional factors.
To the first order, the shift in Vth due to short-channel effect can be expressed as (5) and (6) [14]: 1 (2Vbi − φs ) + Vds 2 cosh(L/ l ) − 1 2εSi φs 1/4 εSi toxe · l = εox η qNch
(5) (6)
where Vbi is the built-in voltage of the source/drain junction, and η is a parameter to model the average depletion width along channel. Assuming the fluctuations of two gate edges are uncorrelated, random variation of channel length due to LER is calculated by using the following equation [3]: σL =
2 · σ LER 1 + W/Wc
where C2 is a fitting parameter that is associated with junction built-in voltage induced short-channel effect [14]. C3 is a fitting parameter associated with surface potential. Figure 3 shows the comparison of model scalability with TCAD simulations. 3.3 OTF
3.2 LER
Vth = −
where σ LER and Wc is the standard deviation and auto correlation length of the gate edge, respectively. By differentiating (5), and substituting (7), the following expression is obtained: 2 (C2 + Vds ) sinh(L/ l ) σ Vth(LER) = · σ LER 2l (cosh(L/ l ) − 1)2 1 + W/Wc (8) 1/4 εSi toxe 2εSi l = C3 · (9) εox qNch
(7)
Similar to LER, OTF leads to the geometric fluctuation of averaged oxide thickness, and further affects the voltage drop across the oxide layer. For a bulk device, Vth is expressed as the following [15]: Vth = VFB + φs +
toxe 2qNch εSi φs εox
(10)
The oxide thickness changes with surface roughness in the interfaces of gate-SiO2 and SiO2 -substrate. The minimum magnitude of OTF is the height of one silicon atom layer (H = 2.71 Å). The correlation length (λ) of OTF is typically from 1–3 nm [12], which is still much smaller than gate length. Assuming that the two interfaces are uncorrelated, the standard deviation of oxide thickness fluctuation is expressed as (11): Bλ σ tox = H √ 2W L
(11)
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111 Table 1 Minimum length, Vdd and P-N width ratios of inverter for the different technologies
Fig. 4 Nch and tox dependence of OTF induced σ Vth
Technology
L (nm)
Vdd (V)
P to N ratio
45 nm
45
1.0
1.02
32 nm
32
0.9
0.96
22 nm
22
0.8
0.91
16 nm
16
0.7
0.80
12 nm
12
0.65
0.84
LER is strongly dependent on the lithography and etching process. In this study, the standard deviation of LER is assumed to be fixed at 0.5 nm [1, 11]. Under this assumption, it is observed that LER induced Vth variation may dominate total Vth variability in future technology nodes, due to the ever-increasing short-channel effect. On the other hand, OTF induced Vth variation exhibits a faster increasing rate with technology scaling, because of its square-root dependence on Nch . 4.2 Circuit performance benchmarking
Fig. 5 The trend of σ Vth in device scaling
Furthermore, representative digital circuits, including an inverter chain and SRAM cell, are used to study the impact of random of Vth variation on circuit performance variability. During statistical circuit simulation, Vth is treated as a random variable with its variance from the model, and other model parameters are fixed at the nominal values. 4.2.1 Inverter chain
where λ denotes the correlation length of oxide surface roughness, and B is a fitting parameter. Moreover, from (10) and (11), the standard deviation of OTF induced Vth variation is derived as: √ qNch εSi λ H (12) σ Vth = C4 √ εox 2W L
4 Scaling trend of Vth variation
A 7-stage inverter chain is adopted, with both NMOS and PMOS device at the minimum gate length. The width of the NMOS device is assumed to be 8 times the length, while the ratio of PMOS to NMOS width in the inverter is optimized by equating the rising and falling times. Table 1 lists the P to N ratios obtained in this way for the different technology nodes. To study the effect of variation of Vth we consider the delay metric. This is measured across fourth inverter because it is well isolated from effects of input waveform and output loading. Random Vth variations, as described in previous sections, are considered in the simulation, assuming they are uncorrelated in all 14 transistors in the 7-stage inverter chain. Figure 6 illustrates the mean and standard deviation of inverter delay during technology scaling. While the scaling successfully speeds up the nominal circuit performance, the variability of inverter delay keeps increasing, as the result of the rapidly exacerbated random variations.
4.1 Impact on device variability
4.2.2 SRAM cell
Based on the PTM model, Fig. 5 illustrates the projection of Vth variation toward the 12 nm node. The amplitude of
A SRAM cell represents the most sensitive circuit unit to process variations. A typical 6-T SRAM is used in this
where C4 is a fitting parameter. Figure 4 validates this equation with TCAD simulations. From Fig. 4, OTF induced Vth change is independent on oxide thickness. Moreover, Vth variation due to OTF is much more sensitive to Nch , as compared to that due to RDF (4). This fact suggests that as channel doping concentration increases in future CMOS devices, OTF induced Vth variation will become increasingly important over that induced by traditional RDF effect.
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Fig. 6 The scaling trend of the mean and standard deviation of inverter delay under random variations
analysis. All six transistors have the minimum gate length. The pull up PMOS is assumed to be at the minimum width. The widths of access transistors and pull down NMOS are tuned to achieve the same read and write noise margins. To evaluate the operation speed of a SRAM cell, Read Access Time (RAT) is examined. Assuming that sense amplifiers are able to measure 10% of Vdd drop on either BL or BL, read access time is calculated as the time when BL or BL reaches 90% of Vdd . Monte Carlo simulations are performed to extract the statistics, considering Vth variations in all transistors are uncorrelated. Figure 7 illustrates the scaling trend of the 3σ corner of RAT. To suppress the variation, one technique is L biasing: increasing gate length by 10% is able to reduce Vth variation by >28% at the 12 nm node (Sect. 3). Although this may not be practical today due to the overhead in the nominal RAT (Fig. 7), such a technique benefits future technology nodes: with 10% L biasing at the 16 nm node and below, the reduction in the excessive variability overwhelms the change of the nominal value (Fig. 7) and thus, the corner value of RAT decreases. This tradeoff highlights the importance of variability control for future IC design. Finally, the variability in SRAM Read Noise Margin (RNM) is decomposed into different variation sources, as shown in Fig. 8. For a first order analysis Read Noise Margin of SRAM is considered to be linear function of mismatches between Vth of transistors. The following six mismatches are considered and all are taken to be independent. 1. Mismatch between M1, M2 and between M3, M4 2. Mismatch between M1, M3 and between M2, M4 3. Mismatch between M2, M5 and between M4, M6 The variations in Vth of each transistor are directly mapped to mismatch between pairs as listed above. The variation of mismatch is considered to be summation of variation of both transistors as given in (12). 2 2 2 = σ Vth,(M1) + σ Vth,(M2) σ Vth,(M1M2)
(13)
Fig. 7 The 3σ corner of SRAM RAT can be effectively reduced by suppressing random Vth variations
Fig. 8 The decomposition of RNM variability
The variation in RNM is calculated from variation of mismatches and β coefficients as given in: 2 2 σ RNM 2 = β12 σ Vth,(M1M2) + β22 σ Vth,(M4M4) 2 2 + β32 σ Vth,(M1M3) + β42 σ Vth,(M2M4) 2 2 + β52 σ Vth,(M2M5) + β62 σ Vth,(M4M6)
(14)
Similar as that in inverter delay, LER and OTF rapidly increase as major contributors to RNM variability, with RDF being relatively constant along with the technology scaling. This behavior is mainly because the device dimension is approaching fundamental atomistic limits, which are not scalable.
5 Conclusion In this work, random Vth variation under RDF, LER, and OTF is studied through 3-D atomistic simulation with commercial TCAD device simulator. With the simulated result,
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a suite of scalable and predictive compact models are proposed. Furthermore, random Vth variation is projected to advanced technology nodes, illustrating the trend and importance to future device and circuit performance.
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