Reconfiguration of Convolutional Encoder by ... - SSRG Journals

International Conference on Explorations and Innovations in Engineering & Technology (ICEIET - 2016)

Reconfiguration of Convolutional Encoder by optimizing the XOR 1

2

ARUNA JAYASHREE R

Assistant Professor Department of Electronics and Communication Engineering TRP Engineering College (SRM GROUP), Tiruchirappalli – 621 105, India

Abstract—This

paper proposes a reconfiguration of convolution encoder by using optimized XOR. In VLSI domain, power consumption plays a vital role for implementing low power design. XOR consumes less dynamic power when compared to basic gates like AND and OR. The FPGA implementation of new architecture uses Look up Table (LUT) for storing the parity bits. The design and implementation is carried out by using optimize XOR algorithm. The proposed algorithm reduces the dynamic power, improves the hardware cost and propagation delay. Here the circuit simulation is obtained by using XilinxSpartan 3E with modelsim and the respective analysis of the waveform is done.

RAMYASHRI S, 3 SELVARANI S, 4 SHARMILA M

UG Scholar B.E.(E.C.E) TRP Engineering College (SRM GROUP), Tiruchirappalli – 621 105, India performs modulo- 2 additions. The code rate is expressed as r=k/n bits/symbol. Few attractive heuristic approaches are reported in literature to minimize adder count by eliminating The redundant computation. Such approaches are mostly based on Common Sub-expression Elimination (CSE) method which depends upon the commonalities of the used polynomials involving modulo two adders and consume more power.[4]

Keywords—Optimized XOR, dynamic power, Look up Table (LUT), Propagation delay.

I. INTRODUCTION The convolution encoder core is used to encode the data prior to transmission over a channel. In basic convolution encoder two or three bits are transmitted over the channel for every input bit. The conventional convolution encoder is realized with a Shift Register (SR) using delay elements and modulo-2 adders (XOR gates). In the convolution process the main operation is multiplication, which is implemented using shifts and adds .[1] The basic architecture of convolution encoder is shown in figure 1.The incoming data is brought into constrain register a bit at a time, and output bits are generated by module-2 addition of the required bits from the constrain register. The bits to be XOR are selected by the convolution codes. Each input bit enters a shift register and the output of the encoder is obtained by combining the bits in the shift register. Convolutional codes are generally specified by the three parameters (n,k,m).Where n=number of output bits ,k = number of input bits and m = number of memory register[3]. Convolutionally encoding the data is accomplished using a shift register and accompanied by a combinational logic that

ISSN: 2348 - 8549

Figure1. Basic Architecture of Convolution encoder This paper describes a new algorithm to implement an convolution encoder of a chosen generator polynomial having constraint length (k