development (TD) phase, which will lengthen the production ramp-up period, and further affect the product profit. To shorten the time-to-market of a new ...
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Editorial: Reduce Time-to-Market by Considering Reliability Tradeoffs Abstract—Yield and reliability susceptibility would become obvious with the increase in the complexity of manufacturing technology. Yield and reliability enhancement is always our pursuit. However, tradeoffs between yield and reliability, or between Fab and assembly house, are often observed during the technology development (TD) phase, which will lengthen the production ramp-up period, and further affect the product profit. To shorten the time-to-market of a new technology, some practical experiences on solving tradeoffs in semiconductor manufacturing are reported; a generic procedure to handle the tradeoff problem is proposed, and the effectiveness was also proved. Early detection capability, baseline knowledge management, fully understanding customers’ requirements, and effectively consolidating all parties’ efforts are considered to play key roles in the procedure. It is believed that such a procedure can be also applied to solve the tradeoff problem in other industries. Index Terms—Baseline, early detection, integrated circuit, knowledge management, reliability, time-to-market, tradeoff, yield.
PFA
Physical failure analysis.
IFR
Increasing failure rate.
GND
Ground.
OOC
Out of control.
SPC
Statistical process control.
DOE
Design of experiment.
Cpk
Complex process capability index.
CPI
Chip package interaction.
WB
Wire bonding.
DUP
Device under pad.
PV
Point via.
ESD
Electro-static discharge.
GOI
Gate oxide integrity.
ACRONYMS NOTATION
IC
Integrated circuit.
Fab
Fabrication.
Averaged defect density.
ppm
Part per million.
Yield.
WAT
Wafer acceptance test.
WLRC yield.
CP
Chip probing.
WAT yield.
FT
Final test.
WLRC
Wafer level reliability control.
Number of comb fingers per unit length of the WLRC structure.
CA
Construction analysis.
Number of comb fingers per unit length of the WAT structure.
WIP
Work in process.
Reliability critical areas.
IMD
Inter-metal dielectric.
Yield critical areas.
FA
Failure analysis.
Reliability.
CMP
Chemical mechanical polish.
Maximal internal stress.
TD
Technology development.
Maximal moment.
EM
Electro-migration.
Permissible stress.
HTOL
High temperature operation lifetime.
Anti-bending strength.
EFR
Early failure rate.
Width.
CD
Critical dimension.
Height.
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TR.2012.2222471
TERM Via
Contact layer in an integrated circuit.
0018-9529/$31.00 © 2012 IEEE
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I. INTRODUCTION
T
HE advance of nanometer scale semiconductor manufacturing technology delivers integrated circuit (IC) chips with high density, high speed, and low power. However, the scaling down of the fabrication technology also results in defect susceptibility levels that reduce process yield and reliability. For the manufacturing of electronic products, yield is an essential requirement for most customers, though reliability is also fundamental. The time to enhance and to stabilize yield becomes longer than what it took before. Usually, high yield leads to high reliability [1], but sometimes a tradeoff is observed between yield and reliability [2]–[4]. It then requires certain process tuning to determine a window to suit both needs. Besides the tradeoff between yield and reliability, there are also tradeoffs among different reliability items (e.g., between device hot carrier and inter-metal dielectrics breakdown), and between foundry and assembly processes. The solutions of these tradeoffs are usually time consuming, and have negative impacts on time-to-market and profitability. On the other hand, the process or approach to identify, solve, and balance the tradeoff provides valuable guidance for the development of both current and next generation products. And based on our practical experiences, it can greatly shorten the time-to-market of new products if baseline knowledge is adequately managed. The tradeoffs in the semiconductor industries are frequently encountered. To optimize yield, and to reach acceptable reliability levels, the industry uses advanced optimization solutions, built in and leveraged at different phases of the chip realization flow [5], [6]. Even for matured technologies, it is reported [7] that the optimization of the performance will often encounter a strict tradeoff between performance and reliability. In this paper, several practical examples to solve the tradeoff between yield and reliability of semiconductor manufacturing and assembly were introduced, and a generic procedure on how to handle the tradeoff is proposed, aiming to timely resolve the tradeoff for earlier production releases. The proposed procedure can be applied in almost all industries. And we also indicate the importance of employing systematic problem-solving and statistical knowledge on manufacturing processes, especially the most complicated ones like semiconductor fabrications. We found that faster time-to-market can be realized only if we best consolidate technology development approaches and statistical problem-solving methodologies, which are in fact very fundamental skills.
II. SOME PRACTICAL EXAMPLES In most cases, we find that a high yield results in a high reliability in semiconductor industries, as depicted by curve 1 in Fig. 1. However, tradeoff exists almost everywhere. Besides the tradeoff between yield and reliability in a semiconductor fabrication (Fab) as shown by curve 2 in Fig. 1, there is also a tradeoff between Fab and the assembly process (curve 3 in Fig. 1), where we find a high Fab yield does not lead to a high assembly yield, though it is shown that higher assembly yields usually lead to
Fig. 1. Tradeoff between yield and reliability, and between Fab and assembly yield.
higher end-product reliabilities. We present some practical examples to illustrate the relationship between these tradeoffs. Case 1: The Higher the Yield, the Better the Reliability: Usually, a high yield leads to a high reliability [8], and we find most yield or reliability issues are defect related; the efforts to improve yield usually accompany a side benefit of an increased reliability. To detect such yield or reliability killer defects, whose levels have become very low ( 200-ppm), we must introduce baseline management and stability monitoring programs at both technology evaluation and mass production stages. It is quite challenging to detect and reduce part per million (ppm)-level defects. What we need is a full-coverage system incorporating the correlation between wafer acceptance test (WAT) and chip probing (CP) or final test (FT) for the yield killers, and the employment of wafer level reliability control (WLRC) [9] for reliability defects. It is proven that an effective WLRC program must be coupled with proper arrangements on inline defect scans, construction analysis (CA), and aligned WAT setups. Though not all WAT structures are tested, WAT is done on each production wafer, whereas CP and FT might be skipped in some occasions if for example the yield is higher than a pre-specified level (mainly to save test costs). It is worthwhile mentioning that both WLRC and CA are conducted on products under mass production, with a certain amount of work in process (WIP), and a comparably long product life cycle. However, unlike WLRC whose wafers can still be shipped, the wafers for CA are also production wafers; but we need to scrap them for the destructive analyses. Due to the high investment, we must best utilize the information acquired from CA (by for example fast responses to recurring defects) to maximize its effectiveness on timely detections. These ideas are further elucidated by a practical example below. A product under mass production failed IMD-1 (the intermetal dielectrics between metal 1 and 2) Vramp tests at both WAT and WLRC (see Fig. 2). This product was also found to have random yield loss ( 1%). In this case, a kind of defect (i.e., contact CMP induced W slice residues) observed at CA was quickly proven to have a negative impact on yield, and reliability by WAT, and WLRC, respectively. Failure analysis (FA) revealed that, from WAT and WLRC failed samples, the difference in the defect was only on the size: the WAT failed samples had a larger size of W slice defect [see Fig. 3(a)], while WLRC failed samples showed a much smaller W slice [see Fig. 3(b)]. The WLRC test patterns
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as expressed in (2), and (3), respectively. , and respectively represent the WLRC, and WAT yield; , and respectively correspond to the number of comb fingers per unit length of the WAT, and WLRC test structure; and is the averaged defect density. (1) (2)
Fig. 2. IMD-1 Vramp: (a) failure distributions; (b) SPC. (a) Nonconformance. (b) IMD-1 Vramp SPC.
(3) From (2) and (3), we can get (4) Further, (5) Using to replace reliability and yield:
, we can get the relationship between
(6) Fig. 3. TEM images of the metal slice defect for M1 IMD Vramp fail samples: (a) WAT (the defect size is about 150 nm); (b) WLRC (the defect size is about 50 nm).
This result is similar to Huston and Clarke’s expression of the relationship between defect reliability and yield [11] as in (7)
Fig. 4. Comb finger of the WAT and WLRC test structure; the finger number . per unit length
have more on-rule vias (a via is a contact layer in an IC), and have higher detect-ability on this IMD defect, which may not be caught at WAT. The test structures of WAT and WLRC may not be identical because, for example, customers may particularly specify the WAT test structures. Wafer manufacturers will work with customers to align the test methodologies as much as possible so WAT results can also benefit from reliability assessments. A typical test structure of two metal combs for WAT or WLRC IMD tests or both is conceptually illustrated in Fig. 4, in which one metal comb is connected to ground (GND), and the other to the positive end of the power supply during test. In the Poisson yield model in (1) [10], if replacing the chip area with the number of comb fingers per unit length, we can obtain the yields predicted by WAT, and WLRC test structures,
, and are the reliability, and yield critical areas respectively; is the wafer yield, and represents the reliability. For this case, because , the calculated will be less than , which means our WLRC detect-ability is superior to that from WAT. And this result is also verified from WAT and WLRC records. Because the WAT test is only done on part of the structures on a wafer, and WLRC is implemented at the sampling base (i.e., not all lots and wafers are tested), unless we increase the sample sizes, we cannot detect low-ppm (e.g., 200-ppm or less) defects in a short period of time. But, as long as WAT and WLRC SPC systems are sufficiently sensitive, we can still detect the signal [as the out-of-control, OOC, point in Fig. 2(b)]. The statistical process control (SPC) sensitivity can also be enhanced by applying trend tests [12], which are proven to be effective especially for WAT and WLRC SPC charts. As a final remark on WAT, tighter controls (e.g., a larger sample size or a more stringent passing criterion) must be applied on reliability related items like gate oxide and dielectrics breakdown. After improvements mainly on CMP, the 1% yield loss was solved, and we also found the WLRC SPC chart became normal [see Fig. 2(b)]. From this case, through extensive integrations among CA, WAT, WLRC, and CP, we proved the current procedure is sufficiently effective to sustain an acceptable yield and reliability. Case 2: A Tradeoff between Yield and Reliability: Electromigration (EM) is a critical metal reliability test. It is a required evaluation during the TD phase of a new technology [3], [13]. In practice, via EM lifetime has become much shorter as technology advances to 55 nm and below. When developing a deep sub-micron ( 55 nm) technology, we faced a challenge on via
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Fig. 5. EM test results: (a) via A; (b) via B.
Fig. 6. EM results with different via CD; (a) lognormal plot; (b) Weibull plot.
EM, whose slope is very small [ 1; Fig. 5(a)]; and this challenge clearly indicates we have fundamental issues on the processes or the test structures or both; this conclusion is based on previous experiences, and from the fact that EM depicts the wear-out behaviors of metals, and we must have an increasing failure rate (IFR). Comparing with the EM results on other structures [whose EM slopes are all 2.7; Fig. 5(b)], and based on clean high temperature operation lifetime (HTOL) or early failure rate (EFR) data and the much better via profiles from physical failure analysis (PFA) on production dice, we narrowed the problems to the via size (the via critical dimension (CD)) of the EM test structures; the larger the via size, the longer the EM lifetime, but the lower the yield, which can be seen from Figs. 6 and 7, respectively. In Fig. 6, two kinds of plots, lognormal plot [see Fig. 6(a)] and Weibull plot [see Fig. 6(b)], are used to evaluate the via EM performance. The use of lognormal for EM was quite arbitrary, but by reasonable fit. We could also use other distributions (like Weibull) as long as the fitting (which is evaluated by in Figs. 5 and 6) is good (e.g., ). One significant merit of the Weibull plot resides in the fact that its slope closely relates to failure rate. For wear-out behaviors like EM
and TDDB, the slope in the Weibull plot must be larger than 1, so we have an IFR. Because of this attractive merit, we strongly suggest always using Weibull plots for EM tests as a quick check if there is a serious defect, whose Weibull slope is usually less than 1. To be more specific, for EM, based on our experience, a slope of 1.2 can be considered as a failure criterion, while a slope of 1.6 can be taken as the minimum for an engineering pass standard. More tests on other wafers and lots are needed if the slope is between 1.2 1.6. For years, such guidelines have worked reasonably well, and have become an engineering baseline for EM. From Fig. 7, we also find that a particular EM test structure is more sensitive than others, and it does show earlier signals that a larger via size will lead to a lower yield. But for the via CD corresponding to better EM performance in Fig. 6, the yield can still be kept at an acceptable level, as represented by CD X2 X3 in Fig. 7. Finally, the via CD X4 in Fig. 6(a) was selected as the solution to the tradeoff problem in this case. Due to this tradeoff between yield and reliability, to avoid a great deal of effort on process changes (which require re-qualifications, and will seriously delay production ramp-up), we need to identify a proper window to balance EM lifetime and
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Fig. 7. Yield versus via CD.
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Fig. 9. CPI Cu WB low yield FA: (a) M4–M6 burnout; (b) cross-sectional profile showing thinner M6.
is 60%. FA showed M4-M6 burnout [see Fig. 9(a)], while no burnout was found on the non-bonding sample. Moreover, from the cross section, we found that the failed sample has a thinner M6 [see Fig. 9(b)]. The thinner metals will result in a weak anti-bending strength for M6. This result can also be deduced from (8) [14]. (8) is the maximal internal stress generated in the cross section of the material; is the maximal moment forced on the material; is the permissible stress of the material; represents the anti-bending strength of the material. For a cubic bulk material with and , Fig. 8. Three-dimensional conceptual plot on the relationship among yield, reliability, and via CD.
yield. After conducting process design of experiments (DOE) for both screening and optimization, we successfully derived a suitable process window with a qualified EM result and acceptable yields. The conceptual 3-D relationship of yield, reliability, and via CD is shown in Fig. 8. Windows A and B are within the acceptable change regions, and no re-qualification is needed. Therefore, the tradeoff between yield and reliability can be resolved by a comparably minor process change (i.e., from window A to window B), although we have a smaller process window from the solution (window B). After production release and at ramp-up, the challenge to Fab is on maintaining a high complex process capability index (Cpk) of certain processes because of the much smaller window. Further process optimization is deemed necessary to achieve a 1.33 process capability. This example also depicts the importance of DOE, which can quickly display the interactions among various parameters, and is much more valuable (in terms of time and resources) than the one-variable-each-time splits at process window optimizations. Case 3: A Tradeoff Between Fab and Assembly Yield: This case is for the chip package interaction (CPI) copper wire-bonding (WB) qualification of a 45 nm low leakage process in which an ultra low-k dielectric was used, and it has a weak mechanical strength due to the loose structure in nature. From FT results, we have low yields mainly from a device under pad (DUP) point via (PV) structure whose failure rate
(9) From (8) and (9), it is obvious that a small (e.g., the thinner M6 thickness in this case) will lead to a small , and further a large . So the thinner M6 will be easier to bend or crack under the vertical bonding stress. Further, after checking the layout, we found that the PV structure has a low M5 density, which may induce an M6-M4 short under the bonding pressure. So, M6 thickness, bonding pressure, and M5 density are the key factors for this CPI qualification. But after these impact factors were improved, another failure mechanism, the ESD induced failure, appeared and was verified in the subsequent CPI re-qualification. We found weak ESD protection designs on the package substrate. Such ESD related failures were enshrouded by the more severe weakness on the process recipe and the test structure designs, which made them hard to be distinguished at the beginning. Then another ESD related qualification cycle had to be started again, and the time-to-market was seriously impacted. In this case, the CP yield has a reverse behavior to the assembly yield as curve 3 indicated in Fig. 1. Performing reliability tests (e.g., temperature cycling and high temperature storage), we found similar burnout and cracks on the failed samples, which indicated reliability had a positive correlation with the assembly yields. So, to improve the reliability of this product, the assembly yield must be firstly improved, which can be realized through the proper CPI substrate design, and the optimal fabrication processes. For this case, the optimized fabrication process was proved to have a great improvement on the assembly yield at the price of a slightly lower CP yield ( 1%).
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Fig. 10. Procedure for the solving of yield and reliability tradeoff problem.
The CPI qualification is usually time-consuming as it requires extensive communication and design refinements between Fab and the assembly house. A longer time will be needed for, e.g., geographical locations of Fab and the assembly house, the lack of electrical tests (e-test) at the assembly house, inadequate assembly DOEs (due to the unavailable e-test results as DOE inputs), and the package design weakness (which usually cannot be timely distinguished). The lessons learned from this case can be outlined as: 1) CPI design details were not reviewed in advance; 2) assembly DOE was not planned in the beginning; and 3) information sharing was not timely and sufficient between different parties such as assembly, TD, subcontract team, and Fab, which means the corrective actions could not be timely implemented. Hence, to shorten the CPI qualification, a systematic approach needs be established before qualification to ensure smooth information sharing on, e.g., customer requirements, product applications, assembly limitations, and reliability targets. Section III is just for this purpose. III. PROPOSED PROCEDURE Besides semiconductor industries, the tradeoff between yield and reliability is also common in other industries; and how to better solve it has become an urgent topic. We propose a procedure (see Fig. 10) based on our practices in semiconductor industries to resolve the tradeoff, and serve as a guideline. In the development stage of a new technology, one important work is to collect necessary information for this technology so
that we can have an accurate evaluation on its marketing position, and the detailed reliability specifications. The necessary information should include the customer’s requirements, the field applications, the best practice of similar technologies, and internal knowledge base on yield and reliability. Based on these collected information, we define evaluation and qualification criteria on yield and reliability. For previous failures and marginal reliability items, we need have earlier surveys, and clearly specify enhanced evaluations at TD stage to ensure sufficient margins so as to reverse the trends; serious reliability excursions easily happen when process variations exceed the small margins. It is thus extremely important to enlarge reliability allowance whenever possible. Lacking the necessary information may result in project delay like in Case 3. But before realizing this purpose, we firstly must prioritize the collected information based on yield and reliability targets. For example, some products may quickly phase out (e.g., 1 year) after being put into market; for such cases, a very rigorous reliability requirement for this product may not be suitable; and under the alignments with customers, we may properly sacrifice the reliability window some to strive for higher yields. Moreover, because customer orientation is always a golden guideline for service providers, there is no doubt that customers’ requirements should always be respected during the definitions of yield and reliability targets. In some cases, customers waive some reliability qualification items to quickly catch the market. If no field returns arrive after a certain
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Fig. 11. Time lines of the 1st and 2nd generations of some flash technology.
amount of shipment, such reliability relaxations can actually be part of the reliability knowledge-base for similar technologies and application profiles. This approach again reflects the importance of information feedback from customers and end users. Next, we need to have an overall analysis on all screening stages (e.g., WAT/ CP/ FT/ WLRC data) to get a clear image of the yield and reliability performance of this technology. The relevant test key designs, test methodologies, test coverage, and test times can also be verified and evaluated during this stage. By studying the trend chart of yield and reliability versus some process parameters, we may decide if there exists a tradeoff between yield and reliability. The early detection and evaluation of the tradeoff is critical to shorten production ramp-up. From practices, for the tradeoff decision in Fig. 10, we can outline the followings as major steps. 1) List all involved process steps and the corresponding process windows. 2) Do reliability tests on the selected corners and splits, and record the corresponding yields. 3) Using the outputs from step 2 as DOE inputs, perform DOE to screen the most significant factors, and analyse the reliability-yield correlation. 4) Implement optimization DOE, and obtain the sensitivity analysis on the key variables. 5) Evaluate tradeoffs based on the results of yield and reliability tests. After these efforts, if no tradeoffs are found, namely the yield and reliability trend charts are consistent versus process parameters, our efforts must focus on improving both yield and reliability to acquire pre-specified margins. Otherwise, we need to tune related processes, and setup a process window to balance the tradeoff between yield and reliability. It is very important that we evaluate tradeoffs before official qualification. Experience shows that fatal delays will occur almost surely if missing this task. And this tradeoff confirmation is the most critical step of our proposed procedure. Unless both yield and reliability meet the requirements, we should continue process tuning and DOE. Meanwhile, all screening methodologies should be further polished to compensate the time spent on the developments. After completing the process reliability qualification and the product reliability tests, we then release the product for mass production. At this stage, Cpk will be a key index for process
capability, and to ensure the effectiveness of future yield enhancements. At mass production, we must incessantly enrich our knowledge base, and strengthen the baseline management to incorporate lessons learnt on, e.g., equipment release and expansions, tool matching, manufacturing stability (inline and offline SPC, facilities and equipment SPC, WAT SPC, and WLRC), in-process monitor efficiency, screening methodologies (like inline GOI, WAT, CP, and FT). Case 1 introduced in Section II is a perfect example of the benefit from SPC and baseline management. We must point out that the proposed flow to solve tradeoffs is not a one-way route but a close-loop flow. The collected experience and feedback from customers and end-users are most precious for current production, as well as for the development of next generation technology. It greatly helps shorten learning cycles and to realize early time-to-market, as shown by an actual case in the next section. IV. EVALUATION OF THE EFFECTIVENESS THE PROPOSED PROCEDURE
OF
The effectiveness of the proposed procedure to solve the tradeoff was practically verified by the development of the 1st and 2nd generations of Flash memory technology. During the development of the 1st generation technology, qualification failed for unaligned reliability targets. Not knowing the criticality of erase time for the final application profiles, these data were not collected, and the stress was not properly applied during cycling, which is the most important test item for non-volatile memories. Instead of collecting the erase time of each sample under test, we only indicate the pass and fail of the samples. But for reliability tests, it is very important to strive for transforming binary data (i.e., pass or fail) into continuous data (e.g., leakage current, threshold voltage, Vcc min, and the erase time in this case). The information-rich continuous data can help decision making using much fewer samples at the same confidence level. Moreover, due to the complexity of stress and testing, reliability tests for the deep submicron devices have altered from stress-to-fail to stress-to-target, which heavily relies on the continuous data of, e.g., performance degradation. All these reasons for the qualification failure just elucidate the importance of collecting the necessary information like customers’ requirements, field applications, benchmarking, and the internal database on yield and reliability at the early stage of technology development.
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To improve the erase performance, we refined processes on tunnel oxide at the price of relaxing gate-oxide integrity (GOI) requirements, which was just an example of detecting and evaluating the tradeoff between different reliability items. In fact, for this product, the GOI performance has been marginal from the beginning. Fortunately, as the end-user clearly indicated the preference for cycling rather than GOI reliability, we re-formulated the yield and reliability guidelines, and successfully balanced the tradeoff between these two reliability tests by proper process tuning. The products were released for mass production after almost one year of development (the upper time scale in Fig. 11). From the qualification process of the 1st generation technology, besides the tradeoff handling experiences, we identified one other major mistake: information sharing, especially of the customer expectations (i.e., erase time is a key index), and the final production applications (i.e., GOI is not a concern as long as it passes a more relaxed threshold). It is a great loss for both the manufacturer and the customer that the production took almost a year. Under the current environment of rapidly changing markets, closer bonds between suppliers and customers have become a key element for success. Some positive outcomes from this 1st generation product are the baseline knowledge about this technology, and the setups of both wafer-level and product-level reliability test capability; the latter capability significantly reduces the data feedback from 2 months to 2 weeks. These two factors (i.e., the learning of baseline knowledge, and the setup of test capability) are later proven to play key roles on a much shorter time-to-market of the 2nd generation product (the lower time scale in Fig. 11). Based on the experience from the 1st generation technology, we focused our efforts on the erase cycling performance, and adopted the special process to ensure the erase cycling margin when starting the 2nd generation Flash technology development. Because • the reliability requirements have been clearly understood, • reliability qualification items are early prioritized, • related process tuning is commenced earlier, and • cycling results are obtained much faster, we save a lot of time when qualifying the 2nd generation product, whose production release is a total success in a much shorter time (3 months), as illustrated in Fig. 11. The qualification process of the 2nd technology has formed a closed loop, and the methodology implemented in the qualification follows what is in Fig. 10, whose effectiveness is successfully verified by an actual industrial project. The product shipment for the 2nd technology only took 3 months, which is a tremendous reduction from the 12 months for the 1st technology. V. CONCLUSION Time-to-market is a very important factor for the development of a new technology because it directly relates to market share, profits, and even the survival of a company. To shorten the production ramp-up period of a technology, early detecting and solving of problems can be the most efficient way, which needs a knowledge base of baseline management. And SPC is well known to play a critical role for early detection, which can
also be amplified by best utilizing the test structures with good detectability like ILD via-intensified designs in Case 1. The early detected items could be yield or reliability susceptibility. In most cases, a high yield often corresponds to a high reliability. But sometimes a tradeoff happens among reliability, between reliability and yield, and between foundry and assembly processes as illustrated in this paper. To best utilize customers’, end-users’, and subcontractors’ feedback (i.e., the “closed loop” flow) to fine-tune the processes is proven to be efficient and necessary to shorten the learning cycle to quickly solve such tradeoffs. If more effective information sharing is implemented at the beginning, similar outcomes of the case reported in Section IV and in Fig. 11 can be expected. Therefore, to effectively consolidate all parties’ efforts is a key to achieve cost-efficient manufacturing. Our proposed procedure in Fig. 10 is applicable for most manufacturing industries. Although the gating stages in some fields may be different from our mentioned WAT, CP, FT, and WLRC, the tradeoff evaluation we propose may still apply. ACKNOWLEDGMENT The authors would like to thank A. Zhao for his assistance on data collection of the actual cases. Wei-Ting Kary Chien, Guest Editor Semiconductor Manufacturing International Corporation Shanghai, 201203, China Ming Li, Guest Editor Semiconductor Manufacturing International Corporation Shanghai, 201203, China REFERENCES [1] W. Kuo, W.-T. K. Chien, and T. Kim, Reliability, yield, and stress burn-in—A unified approach for microelectronics systems manufacturing and software development. Boston, USA: Kluwar Science, 1998, ISBN; 0-7923-8107-6. [2] J. Yang, M. Masuduzzaman, K. Joshi, S. Mukhopadhyay, J. F. Kang, S. Mahapatra, and M. A. Alam, “Intrinsic correlation between PBTI and TDDB degradations in nMOS HK/MG dielectrics,” in Reliability Physics Symposium (IRPS), 2012 IEEE International, pp. 5D.4.1–5D.4.7. [3] G. B. Alers, D. Dornisch, J. Siri, K. Kattige, L. Tam, E. Broadbent, and G. W. Ray, “Trade-off between reliability and post-CMP defects during recrystallization anneal for copper damascene interconnects,” in Reliability Physics Symposium, 2001. Proceedings. 39th Annual. 2001 IEEE International, pp. 350–354. [4] A. P. Karmarkar, X. P. Xu, V. Moroz, G. Rollins, and X. Lin, “Analysis of performance and reliability trade-off in dummy pattern design for 32-nm technology,” Quality of Electronic Design, pp. 185–189, 2009. [5] Y. Zorian and V. L. D. Gizopoulos, “Guest Editors’ introduction: Design for yield and reliability,” IEEE Design and Test, vol. 21, no. 3, pp. 177–182, 2004. [6] A. Venkataraman and I. Koren, “Trade-offs between yield and reliability enhancement,” in Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT), 1996, pp. 68–76. [7] C. Zambelli, M. Indaco, M. Fabiano, S. Di Carlo, P. Prinetto, P. Olivo, and D. Bertozzi, “A cross-layer approach for new reliability-performance trade-offs in MLC NAND Flash memories,” in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, pp. 881–886. [8] W.-T. K. Chien and C. H. J. Huang, “Practical building-in reliability (BIR) approaches for semiconductor manufacturing,” IEEE Trans. Reliability, vol. 51, no. 4, pp. 469–481, Dec. 2002. [9] T. Kim, W. Kuo, and W.-T. K. Chien, “Burn-in effect on yield,” IEEE Trans. Electronics Packaging Manufacturing, vol. 23, no. 4, pp. 293–299, October 2000.
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[10] W. Kuo and T. Kim, “An overview of manufacturing yield and reliability modeling for semiconductor products,” Proceedings of the IEEE, vol. 87, no. 8, pp. 1329–1344, 1999. [11] H. H. Huston and C. P. Clarke, “Reliability defect detection and screening during processing—Theory and Implementation,” in Proc. Int. Reliability Physics Symp., 1992, pp. 268–275. [12] W.-T. K. Chien and F. Yang, “Using reverse arrangement test for semiconductor manufacturing and reliability tests,” International Journal of Reliability, Quality, and Safety Engineering, vol. 15, no. 6, pp. 497–514, Dec. 2008.
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[13] J. C. A. Huang, W.-T. K. Chien, and C. H. J. Huang, “Some practical concerns on isothermal electro-migration tests,” IEEE Trans. Semiconductor Manufacturing, vol. 14, no. 4, pp. 387–394, 2001. [14] X. F. Sun, “Strength of materials,” Higher Education Press..
Wei-Ting Kary Chien (S’01–M’03) was born in Taiwan in 1965. He received his Ph.D. degree in Industrial Engineering from Texas A&M University in 1994. Before he came back to Taiwan for industrial jobs in semiconductor manufacturing in 1995, he did post-doc researches with HP, and IBM for a year on software reliability modeling, and highly reliable system optimization, respectively. After being with Nan-Ya Technology Corporation, Intel, and TSMC, he joined SMIC in Shanghai in 2001. In 2010, he was Deputy Operation Director with STMicroelectronics in Singapore. He re-joined SMIC in 2011 as Q&R Associate Vice President until now. His current assignments cover quality system management; incoming, in-process, and outgoing quality control; subcontractor quality; reliability engineering; process and product qualification; failure analysis; and ESH (environment, safety, and hygiene). He is Senior Member of IEEE, Member of Phi-Tau-Phi Scholastic Honor Society, and a member of Shanghai 1000-Person Plan.
Ming Li received his B.S. (in 1992) and M.S. (in 1994) degrees in Materials Science from Shanghai Jiao Tong University, and Ph.D. (in 1997) degree in Materials Physics and Chemistry from Shanghai Institute of Metallurgy, Chinese Academy of Science. Since he joined SMIC in 2001, he has been working in the filed of failure analysis. Now he is an Assistant Technical Director of Analytical Laboratory in SMIC. His major job is currently involved in the failure analysis technology development with TEM, SEM, FIB, and Auger for reliability and in-line processes.
