Reducing OLTP Instruction Misses with Thread Migration
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Reducing OLTP Instruction Misses with Thread Migration
Transactions Running Parallel. 6. T1. T2. T3. Instruction parts that can fit into L1-I. Threads. Transaction. T123. Comm
Reducing OLTP Instruction Misses with Thread Migration Islam Atta Pınar Tözün Anastasia Ailamaki Andreas Moshovos University of Toronto École Polytechnique Fédérale de Lausanne
OLTP on a Intel Xeon5660 Shore‐MT Hyper‐threading disabled 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0%
0.8
Breakdown of Core Stalls
Instructions per Cycle
better
0.9
Resource (includes data) Instructions
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
TPC‐C
TPC‐E
TPC‐C
TPC‐E
IPC threshold => Migrate
8
TMi Transaction A T1 T2
CORES 0 1
time
T1 T2 T1 T1
Where to migrate?
• Check the last N misses recorded L1I in other caches 1) No matching cache => Move to an idle core if exists T1 2) Matching cache => Move to that core T2 3) None of above => Do not move T2
9
Experimental Setup • Trace Simulation – – – – –
PIN to extract instructions & data accesses per transaction 16 core system 32KB 8‐way set‐associative L1 caches Miss‐threshold is 256 Last 6 misses are kept
• Shore‐MT as the storage manager – Workloads: TPC‐C, TPC‐E
10
Impact on L1‐I Misses Misses per k‐Instruction
better
45 40 35
Instruction
30 25 20 15 10 5 0 No Migration
TMi TPC‐C
TMi Blind
No Migration
TMi
TMi Blind
TPC‐E
Instruction misses reduced by half
11
Impact on L1‐D Misses Misses per k‐Instruction
better
45 40 35
Write Data Read Data Instruction
30 25 20 15 10 5 0 No Migration
TMi TPC‐C
TMi Blind
No Migration
TMi
TMi Blind
TPC‐E
Cannot ignore increased data misses
12
TMi’s Challenges • Dealing with the data left behind – Prefetching
• OS support needed – Disabling OS control over thread scheduling
13
Conclusion • ~50% of the time OLTP stalls on instructions • Spread computation through thread migration • TMi – Halves L1‐I misses – Time‐wise ~30% expected improvement – Data misses should be handled
