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Reduction of Leakage and Low-Frequency Noise in MOS Transistors Through Two-Step RTA of NiSi-Silicide Technology Rong Yang, W. Y. Loh, M. B. Yu, Yong-Zhong Xiong, S. F. Choy, Y. Jiang, D. S. H. Chan, Y. F. Lim, L. K. Bera, L. Y. Wong, W. H. Li, A. Y. Du, C. H. Tung, K. M. Hoe, G. Q. Lo, N. Balasubramanian, and D.-L. Kwong
Abstract—A two-step rapid thermal annealing (RTA) nickel salicidation process was employed to fabricate 0.1-µm gate length CMOS transistors. Excess salicidation, common in the conventional one-step RTA NiSi process, is effectively suppressed by this approach, which is confirmed by transmission electron microscopy (TEM) images. More improvements due to two-step NiSi are observed in NMOS than in PMOS transistors: The n+ −p junction diode with two-step NiSi exhibits lower reverse leakage and higher breakdown voltage than the one-step silicided diode. For the first time, it is found that two-step NiSi NMOS exhibits significant reduction in OFF-state leakage (∼ 5×) and low-frequency noise (up to two orders of magnitude) over one-step NiSi NMOS, although there is not much difference in PMOS transistors. Index Terms—Breakdown voltage, CMOS, diode, leakage, low-frequency noise, NiSi salicidation.
I. I NTRODUCTION
N
ICKEL salicide has been widely adopted for the CMOS technology nodes, 65 nm and beyond, due to several advantages over TiSi2 or CoSi2 [1]–[3]. The conventional NiSisalicide technology employs one-step rapid thermal annealing (RTA) processing [1]–[3]. However, excess silicidation was found with this one-step RTA NiSi approach for narrow poly lines and small active areas, leading to reverse linewidth effect of sheet resistance, increased diode leakage, and lower diode breakdown issues [3]–[9]. To address these issues, a two-step RTA NiSi process, which limited excess nickel diffusion, was proposed for CMOS applications, and some promising results were demonstrated for n+ −p diode [3]–[5]. However, the results for p+ −n diode and especially for CMOS transistors were not shown. This letter evaluates the two-step RTA NiSi SALICIDE for CMOS applications, in comparison with the one-step RTA NiSi and nonsilicided devices. Compared to one-step approach, twostep NiSi significantly improves in reverse leakage and breakdown voltage of n+ −p diode, while only slightly improves in the breakdown voltage of p+ −n diode. For the first time, it is Manuscript received April 26, 2006; revised July 21, 2006. The review of this letter was arranged by Editor C. Chang. R. Yang, W. Y. Loh, M. B. Yu, Y.-Z. Xiong, S. F. Choy, Y. F. Lim, L. K. Bera, L. Y. Wong, W. H. Li, A. Y. Du, C. H. Tung, K. M. Hoe, G. Q. Lo, N. Balasubramanian, and D.-L. Kwong are with the Institute of Microelectronics, Science Park II, Singapore 117685 (e-mail:
[email protected]). Y. Jiang and D. S. H. Chan are with the Institute of Microelectronics, Science Park II, Singapore 117685. They are also with the Department of Electrical and Computer Engineering, National Singapore University. Digital Object Identifier 10.1109/LED.2006.882567
found that two-step NiSi promises significant reduction in OFFstate leakage (∼ 5×) and low-frequency noise (up to two orders of magnitude) for NMOS transistors. II. D EVICE S TRUCTURE AND F ABRICATION In device fabrication, the gate stack (80-nm poly-Si and 3-nm thermal oxide) received preimplantation of As+ /15 keV/3.5 × 15 1015 cm−2 /7◦ and BF+ cm−2 /7◦ , while 2 /10 keV/4 × 10 source/drain implantation was performed with As/25 keV/6 × 1015 cm−2 /7◦ and BF2 /20 keV/2 × 1015 cm−2 /7◦ , for n- and p-MOSFET, respectively, followed by an anneal of 1015 ◦ C/2 s in N2 ambient. Then, silicide-formation experiments were carried out as follows: 1) Before 10-nm Ni deposition, standard H2 SO4 /H2 O2 , dilute HF dip (2%, 120 s) and degas were done for wafer surface pretreatment. 2) The first RTA (280 ◦ C, 300 s, N2 ) was used to form Ni2 Si phase, followed by selective Piranha etching (70 ◦ C, 180 s), removing unreacted Ni. 3) Highresistivity Ni2 Si phase was transformed into low-resistivity NiSi phase by the second RTA (480 ◦ C, 30 s, N2 ). Step 2 was skipped for the one-step RTA NiSi samples. Devices without NiSi were also fabricated for reference. The sheet resistance in wide areas was measured as ∼17, ∼ 8 Ω/ after steps 2 and 3, respectively, for both n- and p-MOSFET, consistent with the resistivity of Ni2 Si (∼ 33 µΩ · cm) and NiSi (∼ 16 µΩ · cm) [3]. III. R ESULTS AND D ISCUSSION Fig. 1 shows the transmission electron microscopy (TEM) cross-sectional images of 0.1-µm gate length transistors. Compared with the one-step device [Fig. 1(a)], the NMOS transistor with two-step RTA NiSi [Fig. 1(b)] shows shallower NiSi thickness at the edges between source/drain and spacer regions (∼21 versus ∼24 nm); more clearly, in the gate regions, the maximum NiSi thickness is much smaller (∼40 nm) in two-step device than that in one-step sample (∼54 nm). The NiSi/poly-Si interface in Fig. 1(b) is also smoother, indicating significant suppression of excess diffusion of Ni from spacers regions to gates in two-step case. No difference can be found in the AFM scanning images of NiSi surface (not shown here): for all cases, i.e., NiSi silicides in gate or source/drain regions with one- or two-step process, either in PMOS or NMOS, the silicide surface roughness is similar (rms ranges from 1.0 to 1.2 nm). In PMOS, no significant excess silicidation was found for one-step process as that in NMOS, as shown in Fig. 1(c) and (d).
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YANG et al.: REDUCTION OF LEAKAGE AND LOW-FREQUENCY NOISE IN MOS TRANSISTORS
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Fig. 3. Transfer characteristics of 0.1-µm gate length MOSFETs with nonsilicided, one- and two-step RTA NiSi SALICIDE (inset shows the output characteristics).
Fig. 1. TEM images of 0.1-µm gate length MOSFETs: (a) One-step NMOS, (b) two-step NMOS, (c) one-step PMOS, and (d) two-step PMOS.
Fig. 2. Forward and reversed I–V characteristics of n+ −p and p+ −n diodes with nonsilicided, one- and two-step RTA NiSi silicides [insets are (a) I–V curves of diodes with one-step long time RTA NiSi and (b) TEM image of NMOS transistor].
Fig. 2 shows the forward and reversed current–voltage (I–V ) curves of diodes with nonsilicided, one- and two-step NiSi samples. For forward bias, both p+ −n and n+ −p diodes show no significant differences in I–V curves. However, when reverse voltage is applied, for n+ −p diodes, no much distinction was shown in the 0–6-V range among these samples, but the one-step NiSi diode shows increasing leakage current and soft breakdown when further increasing the bias, while the two-step NiSi and nonsilicided diodes keep very low leakage until the sharp breakdowns. Accordingly, the breakdown voltages are 9.7, 7.8, and 9.7 V for nonsilicided, one- and two-step RTA NiSi n+ −p diodes, respectively. These are consistent with the results of n+ −p diodes in literature [4]. However, different from n+ −p diodes, no significant
distinctions are found for leakages, and only minor breakdownvoltage difference is shown in p+ −n diodes (−9.7, −9.2, and −9.7 V for nonsilicided, one- and two-step RTA NiSi diodes, respectively). The distinctions between p+ −n and n+ −p diodes are probably due to the easier activation of BF+ 2 dopant than that of As+ dopant using the same RTA condition after implantation, which results in slower nickel diffusion in p+ −n diodes. Similarly, Jiang et al. found rougher NiSi/Si interface in As+ -doped sample than that in B+ -doped sample using the same postimplantation RTA condition [10]; Lauwers et al. also observed that the presence of B+ in high doses could slow down the silicide formation significantly [3], as confirmed by our TEM results. Another possible cause is that, in the BF+ 2doped case, the F segregation to the silicide/Si(001) interface and silicide grain boundaries retards NiSi grain growth, leading to much smoother layers and inhibits NiSi2 nucleation [11], which may reduce the reverse leakage. To confirm the assumptions, for the samples with source/drain anneal at lower temperature 1000 ◦ C, 5 s, the silicidation RTA conditions were intentionally raised to 480 ◦ C, 300 s, and the reverse leakage of n+ −p diode was found up to a tremendous degree [inset (a)] while no obvious degradations were found in the p+ −n diode. This difference can be explained from the clear NiSi2 spiking found inside silicon substrate in NMOS transistors [inset (b)], however, which cannot be found in PMOS devices (not shown here). This observation supports above assumptions. The transfer curves are shown in Fig. 3 for 0.1-µm gate length transistors. For nonsilicided, one- and two-step RTA NiSi devices, the NMOS/PMOS transistors are with similar threshold voltages, drain-induced barrier lowering (DIBL) factors, and subthreshold swings. However, for NMOS devices, two-step RTA NiSi process promises less OFF-state leakage than one-step process, although still a little higher than nonsilicided process. In retrospect, the OFF-state leakage differences between NMOS and PMOS just agree well with the leakage distinctions between n+ −p and p+ −n diodes. As shown in inset of Fig. 3, output curves are compared among these devices. The drive-current improvements of two-step RTA NiSi devices are found comparable to the improvements resulting from one-step NiSi. In addition to the suppression of excess silicidation issues, the two-step RTA NiSi devices do not lead to any drive-current degradations.
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CMOS transistors. Compared to the conventional one-step NiSi process, the two-step one results in less leakage and higher breakdown in the n+ −p diode. For MOS transistors, two-step NiSi promises less OFF-state leakage and low-frequency noise for NMOS, in comparison with one-step process. This is found mainly due to the difference in excess gate silicidation of onestep process between PMOS and NMOS. ACKNOWLEDGMENT
Fig. 4. Low-frequency-noise characteristics of 0.1-µm gate length MOSFETs with nonsilicided, one- and two-step RTA NiSi SALICIDE [insets show (a) frequency dependence and (b) depth profiles of nickel concentration].
It is interesting to compare the low-frequency-noise characteristics in Fig. 4. As shown in the inset (a), each curve agrees with 1/f noise property. Although all PMOS transistors show similar noise regardless of gate biases, one-step NiSi NMOS exhibits higher noise (up to two orders of magnitude) than nonsilicided and two-step NiSi devices. This is the first time to observe 1/f noise improvements in NMOS using two-step RTA NiSi SALICIDE. Although to date the mechanisms of 1/f noise is not very clear, it is believed relating to surface/interface defects or impurities [12], [13]. One of the dominant theories, the carrier number fluctuation model, is regarded more suitable for nMOSFETs [14], [15], which attributes 1/f noise to the random trapping and detrapping processes of charges in the oxide traps near the Si/SiO2 interface. The interface trap densities (Dit ) were extracted from capacitance–voltage (C–V ) measurements, and it was found one-step RTA NiSi nMOSFET has higher density (4.12 × 1011 cm−2 ), while nonsilicided and two-step RTA NiSi devices show the similar densities (9.42 × 1010 and 1.34 × 1011 cm−2 ). As shown in the inset (b), this higher Dit in one-step process can be attributed to more serious nickel diffusion from gate to channel; however, for PMOS case, although nickel diffusion is also faster in one-step process, the interface nickel concentrations are one order of magnitude lower than those in NMOS, which may impact less on Dit in PMOS, thus no major differences is found among nonsilicided, one- and two-step process PMOS transistors, and their noise characteristics are similar as shown in Fig. 4. These Dit and noise differences, consistent with the discrepancies in NiSi thickness and interface roughness between NMOS and PMOS shown in the TEM images, probably explain why only the nMOSFET has improved 1/f noise characteristics by employing two-step NiSi process. It is believed that gate silicidation plays a major role while source/drain silicidation plays a minor role (may be negligible since source/drain excess silicidation is found much slighter than that of gate as shown in Fig. 1) in nickel depth profiles, and thus in Dit and noise characteristics. IV. C ONCLUSION To suppress excess silicidation issues, two-step RTA NiSi salicidation was employed to fabricate 0.1-µm gate length
The authors would like to thank all the staff of the Semiconductor Process Technologies Laboratory of the Institute of Microelectronics, Singapore, for their support and assistance in device fabrication and characterization. R. Yang would like to thank Prof. Q. Xu and D. Wang in the Institute of Microelectronics of Chinese Academy of Sciences, for their useful advice and discussion. R EFERENCES [1] H. Iwai, T. Ohguro, and S. Ohimi, “NiSi SALICIDE technology for scaled CMOS,” Microelectron. Eng., vol. 60, no. 1, pp. 157–169, Jan. 2002. [2] C. Lavoie, F. M. d’Heurle, C. Detavernier, and C. Cabral, Jr., “Towards implementation of a nickel silicide process for CMOS technologies,” Microelectron. Eng., vol. 70, no. 2–4, pp. 144–157, Nov. 2003. [3] A. Lauwers, J. A. Kittl, M. Van Dal, O. Chamirian, M. A. Pawlak, M. Potter, R. Lindsay, T. Raymakers, X. Pages, B. Mebarki, T. Mandrekar, and K. Maex, “Ni based silicides for 45 nm CMOS and beyond,” Mater. Sci. Eng. B, vol. 114/115, no. 1, pp. 29–41, 2004. [4] J. P. Lu, D. Miles, J. Zhao, A. Gurba, Y. Xu, C. Lin, M. Hewson, J. Ruan, L. Tsung, R. Kuan, T. Grider, D. Mercer, and C. Montgomery, “A novel nickel SALICIDE process technology for CMOS devices with sub-40 nm physical gate length,” in IEDM Tech. Dig., 2002, pp. 371–374. [5] J. Foggiatoa, W. S. Yooa, M. Ouakninea, T. Murakamib, and T. Fukadab, “Optimizing the formation of nickel silicide,” Mater. Sci. Eng. B, vol. 114/115, no. 1, pp. 56–60, 2004. [6] K. Funk, X. Pages, V. I. Kuznetsov, and E. H. A. Granneman, “NiSi contact formation process integration advantages with partial Ni conversion,” in Proc. IEEE Int. Conf. Adv. Therm. Process. Semicond., 2004, pp. 94–98. [7] B. Froment, M. Muller, H. Brut, R. Pantel, V. Carron, H. Achard, A. Halimaoui, F. Boeuf, F. Wacquant, C. Regnier, D. Ceccarelli, R. Palla, A. Beverina, V. DeJonghe, P. Spinelli, O. Leborgne, K. Bard, S. Lis, V. Tirard, P. Morin, F. Trentesaux, V. Gravey, T. Mandrekai, D. Rabilloud, S. Van, E. Olson, and J. Diedrick, “Nickel vs. cobalt silicide integration for sub-50 nm CMOS,” in Proc. 33rd Conf. Eur. Solid-State Device Res., 2003, pp. 215–218. [8] J. A. Kittl, A. Lauwers, O. Chamirian, M. Van Dal, A. Akheyar, M. De Potter, R. Lindsay, and K. Maex, “Ni- and Co-based silicides for advanced CMOS applications,” Microelectron. Eng., vol. 70, no. 2–4, pp. 158–165, Nov. 2003. [9] H. X. Mo, P. Bontanti, B. Zhu, D. Gao, H. M. Wu, J. Chen, H. Z. Wu, Y. L. Jiang, G. P. Ru, and F. Chen, “Ni silicide and Ni germanosilicide selfaligned process for 65 nm and beyond CMOS technology by 2-step rapid thermal annealing,” in Proc. Int. Integr. Circuits and Solid-State Technol., 2004, pp. 464–467. [10] Y. L. Jiang, A. Agarwal, G. P. Ru, G. Cai, and B. Z. Li, “Nickel silicide formation on shallow junctions,” Nucl. Instrum. Methods Phys. Res. B, Beam Interact. Mater. At., vol. 237, no. 1–2, pp. 160–166, 2005. [11] A. S. W. Wong, D. Z. Chi, M. Loomans, D. Ma, M. Y. Lai, W. C. Tjiu, S. J. Chua, C. W. Lim, and J. E. Greene, “F-enhanced morphological and thermal stability of NiSi films on BF+ 2 -implanted Si(001),” Appl. Phys. Lett., vol. 81, no. 27, pp. 5138–5140, Dec. 2002. [12] M. Golio, RF and Microwave Handbook. Boca Raton, FL: CRC Press, 2001. [13] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge, U.K.: Cambridge Univ. Press, 1998. [14] L. K. J. Vandamme, X. S. Li, and D. Rigaud, “l/f noise in MOS devices, mobility or number fluctuations?,” IEEE Trans. Electron Devices, vol. 41, no. 11, pp. 1936–1945, Nov. 1994. [15] J. M. Chang, A. A. Abidi, and C. R. Viswanathan, “Flicker noise in CMOS transistors from subthreshold to strong inversion at various temperatures,” IEEE Trans. Electron Devices, vol. 41, no. 11, pp. 1965–1971, Nov. 1994.
