Hindawi Publishing Corporation EURASIP Journal on Embedded Systems Volume 2010, Article ID 593264, 11 pages doi:10.1155/2010/593264
Research Article Word Length Selection Method for Controller Implementation on FPGAs Using the VHDL-2008 Fixed-Point and Floating-Point Packages I. Urriza, L. A. Barrag´an, D. Navarro, J. I. Artigas, and O. Lucia Departamento de Ingenier´ıa Electr´onica y Comunicaciones, Universidad de Zaragoza, Mar´ıa de Luna 1, 50018 Zaragoza, Spain Correspondence should be addressed to I. Urriza,
[email protected] Received 23 December 2009; Revised 9 April 2010; Accepted 29 July 2010 Academic Editor: Miriam Leeser Copyright © 2010 I. Urriza et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. This paper presents a word length selection method for the implementation of digital controllers in both fixed-point and floatingpoint hardware on FPGAs. This method uses the new types defined in the VHDL-2008 fixed-point and floating-point packages. These packages allow customizing the word length of fixed and floating point representations and shorten the design cycle simplifying the design of arithmetic operations. The method performs bit-true simulations in order to determine the word length to represent the constant coefficients and the internal signals of the digital controller while maintaining the control system specifications. A mixed-signal simulation tool is used to simulate the closed loop system as a whole in order to analyze the impact of the quantization effects and loop delays on the control system performance. The method is applied to implement a digital controller for a switching power converter. The digital circuit is implemented on an FPGA, and the simulations are experimentally verified.
1. Introduction The advances in FPGAs technology [1, 2] have had a big impact on the implementation of digital control algorithms [3]. With the introduction of advanced FPGA architectures, it has become affordable to implement fixed-point [4–8], and floating-point [9–13] data formats and operations in these FPGAs. In addition to implementing these algorithms directly in hardware, FPGAs also allow an HW/SW realization of these algorithms using soft-core or hard-core processors. This work will focus on the first option. The best representation, fixed-point or floating-point, depends on the application. So, the designer must analyze which is the suitable representation for his application. On one hand, floating-point implementations will consume more FPGA hardware resources and achieve lower speed. On the other hand, digital controllers are designed considering real number coefficients and signals, and floating-point to fixed-point conversion may become a difficult and timeconsuming process. In fact, this process has been identified
in a recent survey [14] as the most difficult aspect of implementing a fixed-point algorithm on an FPGA. VHDL is a standard Hardware Description Language that allows high flexibility and technology independence. However, VHDL hardware description is considered as a low abstraction level tool and, in order to reduce design time and effort, some fixed-point implementations use tools such as Altera DSP Builder [4] Xilinx System Generator [6] that directly generates VHDL from Matlab/Simulink, or Handle-C [7]. This work shows how to implement digital controllers in fixed-point using the VHDL-2008 fixed-point package fixed pkg [15], and in floating point using the VHDL-2008 floating-point package float pkg [16]. These packages are included in the IEEE Standard VHDL LRM 1076–2008. The utilization of these packages simplifies the design of arithmetic operations, shortens the design cycle, and makes VHDL competitive with other alternatives. These packages also allow customizing the word length of fixed and floating point representations. This method can also be applied
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to the implementation of any infinite impulse response filter. Several techniques based on bit-true simulations or analytical analysis have been proposed to determine the word length in fixed-point implementations of digital signal processing applications [17–23] and digital controllers [24– 27]. There are fewer methods [28] that offer a uniform treatment for bit-width selection of both fixed-point and floating-point designs. However, in [28] analytical analysis is applied to data flows without feedback, while in this work, the whole system is simulated in closed loop. We perform bit-true simulations using the new types defined in the VHDL-2008 fixed-point and floating-point packages, and a word length that maintains an acceptable closed-loop performance in both cases is determined using an approach very closely related to the method presented in [17, 22]. Thus, our method covers both fixed-point and floating-point word length selection. Except on [25, 27], Matlab/Simulink or C/C++ is used to perform bit-true simulations, and then VHDL is automatically generated by the tool. Using the types defined in the packages has the advantage that the simulated code is also the synthesized one. This paper further develops the work described in [12, 27], developing a framework that offers and unifies treatment for fixed-point and floating-point designs. The remainder of this paper is organized as follows. Section 2 provides a brief description of fixed-point and floating-point numerical representations. Section 3 shows the traditional approach to implement arithmetic operations in VHDL using the numeric std package, and how the new packages simplify the design of fixed and floatingpoint operations. Section 4 presents the proposed word length selection procedure that is applied to an application example in Section 5. Section 6 shows the experimental results obtained using the proposed method and VHDL2008 packages, and finally in Section 7 some conclusions are drawn.
2. Numerical Representations Figure 1 shows the data format of a fixed-point two’s complement representation. The values are coded in w bits with nq bits after the point (fractional word length). A fixed-point data format is expressed as w, nq. The value of a w-bit binary number in this representation is x · 2−nq , where x is the integer equivalent of the two’s complement w bit binary number. The MSB position with respect to the binary point is ni = w −nq − 1. The resolution of the fixed point number is 2−nq , and the range is
ni
ni
−nq
−2 , 2 − 2
.
(1)
FPGAs are not constrained to work with a specific number of bits w to represent data. However, in fixed-point DSPs, w is kept constant because it is constrained by the DSP architecture. Floating point numbers are represented using an exponent and a mantissa following the format shown in Figure 2, where s is the sign bit (0 for positive and 1 for negative
w bits nq bits
MSB s
i
q
ni
−nq
−1
0
Figure 1: Fixed-point format. 1 bit
ne bits
n f bits
s
e
f LSB
MSB
Figure 2: Floating-point format.
numbers), e is the exponent, and f is the unsigned fractional part of the mantissa. The floating-point is “normalized” when it uses a hidden bit, so that the mantissa value is 1 + f . The exponent is biased with bias = 2ne−1 − 1, where ne is the number of bits in the exponent field. Then, the value of the normalized number is
(−1)s · 1. f · 2e−bias .
(2)
The range of normalized numbers is composed of the intervals [−max, −min] and [min, max] where min = 2emin −bias = 21−bias ,
max = 2 − 2−n f · 2emax −bias = 2 − 2−n f · 2bias .
(3)
A single precision floating point number in the standard IEEE-754 [29] is encoded in 32 bits with ne = 8, bias = 127, and n f = 23. A double precision floating point number in this standard is encoded in 64 bits with ne = 11, bias = 1023, and n f = 52. Again, FPGAs, unlike DSPs, are not constrained to work with these standards to represent data. Certain values of e and f are reserved for representing special numbers, such as 0, NaNs (Not-a-Number) that indicates exceptions, ±∞ (Infinity), and denormalized numbers. These special values are as follows. (i) If e = 0 and f = 0, it represents a 0. (ii) If e = 11. . .1 and f = / 0, it represents an NaN. (iii) If e = 11. . .1 and f = 0, it represents ±∞ depending on sign. (iv) If e = 0 and f = / 0, it is a denormal number with value:
(−1)s · 0. f · 2−bias+1 .
(4)
3. Fixed and Floating-Point Number Representations in VHDL The traditional approach to make arithmetic operations between vectors of std logic elements is to use numeric std or std logic arith packages. Both packages define the signed
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vector type and arithmetic and comparison operations between objects of this type. From now on, we will use the first package. In order to sum two operands in fixed-point format, the VHDL designer has to align the binary points, and take into account that the add operator produces a result vector whose length is equal to the length of the longest operand. The following code shows how the signal with the smallest number of fractional bits is left shifted to align the binary point. Besides, sign extension has to be explicitly described in VHDL to manage the carry.
sA
sB
eA
eB 8
Sign calculator
1. fB
1. fA 8
Exponent comparator
24 Exponent difference
24
Shifter
+/ −
Rounding & normalizer
signal A: signed(8 downto 0); -- format
8 sR
signal B: signed(7 downto 0); -- signal Y: signed(11 downto 0); --
eR
24 1. fR
Figure 3: Floating point adder block diagram.
-Y
