Available online at www.sciencedirect.com
ScienceDirect
Available online at www.sciencedirect.com
Procedia Computer Science 00 (2018) 000–000
ScienceDirect
Procedia Computer Science 132 (2018) 843–848
www.elsevier.com/locate /procedia
International Conference on Computational Intelligence and Data Science (ICCIDS 2018)
Resource Utilization Optimization with Design Alternatives in FPGA based Arithmetic Logic Unit Architectures 1,2
Rakhi Nangia1, Neeraj Kr. Shukla2 VLSI Group, Department of Electrical, Electronics & Communication Engineering, School of Engineering & Technology, THE NORTHCAP UNIVERSITY,Gurgaon, (Haryana), India
Abstract Designing Arithmetic Logic Unit (ALU) is a combinational logic problem. As ALU has a regular pattern, it can be broken into identical stages connected into cascade through carry chain. We have designed one stage of ALU and then duplicated it depending upon the size required. The design has been tested for 4, 8, 16, 32 and 64- bit width. The idea is resource sharing and functionality sharing technique to design an ALU that leads to a significant saving of resources. Different functionality has been obtained by using a single resource (parallel adder) with different inputs at different times through control circuit. The design through this approach leads to a significant reduction in hardware requirement. The design is implemented in 3s700anfgg484-4 FPGA. Significant reduction in hardware has been achieved. The hardware used has been compared with normal function by function design. Resources saving of 66% have been observed for 4-bit wide ALU implementation on FPGA. For 8 and 16-bit implementation the saving obtained is 65%. A hardware saving of 60% has been obtained for 32 and 64-bit implementation. © 2018 2018 The Authors. Published Published by by Elsevier ElsevierB.V. Ltd. © The Authors. This is an open access article under the CC BY-NC-ND license (https://creativecommons.org/licenses/by-nc-nd/3.0/) Peer-review under responsibility of the scientific committee of the International Conference on Computational Intelligence and Peer-review under responsibility of the scientific committee of the International Conference on Computational Intelligence and Data 2018). Data Science Science (ICCIDS (ICCIDS 2018). Keywords:ALU; functionality sharin;, resource sharing; bit-slice;
1. Introduction An ALU is a multi-operation, combinational digital logic circuit. It can perform a set of basic arithmetic operations and a set of logic operations by decoding a number of select lines.To perform distinct operations resources are picked from the available hardware of the device being used. However, some HDL coding style may lead to perform several operations with a common resource. This resource sharing approach leads to significant saving of hardware [1]. As resource utilization directly affects the hardware cost [2], the resource sharing technique ultimately reduces the cost of the hardware. The technique is based on the change of order of operation and data selection [3]. * Corresponding author. Tel.: +91-9911289672;
1877-0509 © 2018 The Authors. Published by Elsevier B.V. Peer-review under responsibility of the scientific committee of the International Conference on Computational Intelligence and Data Science (ICCIDS 2018). 1877-0509 © 2018 The Authors. Published by Elsevier Ltd. This is an open access article under the CC BY-NC-ND license (https://creativecommons.org/licenses/by-nc-nd/3.0/) Peer-review under responsibility of the scientific committee of the International Conference on Computational Intelligence and Data Science (ICCIDS 2018). 10.1016/j.procs.2018.05.096
Rakhi Nangia, Neeraj Kr. Shukla/ Procedia Computer Science 00 (2018) 000–000 Rakhi Nangia et al. / Procedia Computer Science 132 (2018) 843–848
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The technique can be applied to arithmetic operations and thus can be utilized in communication systems [4]. Without resource sharing each HDL operation is built with a separate circuitry. For example, every addition operation with non-computable operands will cause a new adder to be built. If (select) Sum
