Building blocks in RF system and basic performances. • Device characteristics in
RF application. • Low noise amplifier design. • Mixer design. • Oscillator design ...
RF circuit design: Basics
Akira Matsuzawa Tokyo Institute of Technology 1
Contents • Building blocks in RF system and basic performances • Device characteristics in RF application • Low noise amplifier design • Mixer design • Oscillator design
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Basic RF circuit block RF systems are composed of limited circuits blocks. LNA, Mixer, and Oscillator will be discussed in my talk. Receiver
1) Low Impedance Noise Matching Amp.
Transmitter
2) Mixer Filter
3) Oscillator Power Amp.
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Basic functions of RF building blocks Amplifier, frequency converter (mixer +oscillator), and filer are basic function blocks in RF system.
2) Mixer+ Oscillator Undesired Down conversion dB
3) Filter
dB
Desired
1) Amplifier
Frequency conversion
Log (f)
Up conversion
Log (f)
4
RF Amplifier • Gain: Amplify small signal or generate large signal. • Noise: Smaller noise and larger SNR. • Linearity: Smaller non-linearity. Non-linearity generates undesired frequency components.
vout (t ) = α1vin (t ) + α 2 vin2 (t ) + α 3vin3 (t ) + ..... (cos(ω1t ) + cos(ω2t ))2 = 2 + cos(2ω1t ) + cos(2ω2t ) + cos((ω1 − ω2 )t ) + cos((ω1 + ω2 )t )
(cos(ω1t ) + cos(ω2t ))
3
1 1 = cos((2ω1 − ω2 )t ) + cos((2ω2 − ω1 )t ) + .... 2 2 5
Input and output characteristics Distortion and noise are important factors in RF amplifier, as well as power and gain. Pout IP3
OIP3 1dB Pout (1dB) IMD3
Fundamental SFDR
Slope=1
Noise Floor
SNR min
Slope=3
SNR min
SFDR BDR NoiseMDS Floor
Pin CP1dB
IIP3 6
Dynamic range Noise Floor = −174dBm + NF + 10 log BW kT limitation
Bandwidth
SFDR: Spurious free dynamic range The input power range over which third order inter-modulation products are below the minimum detectable signal level.
SFDR =
2 (IIP3 − Noise Floor ) − SNR min 3
BDR: Blocking dynamic range
BDR = P1dB − Noise Floor − SNR min MDS: Minimum detectable signal level= Noise Floor +SNRmin
7
Non-linearity CP1dB: The input level at which the small signal gain has dropped by 1dB. CP1dB = 0.145
α1 α3
IMD3: The third order inter modulation term
IP3: The metric third order intercept point. It is the point where the amplitude of third order inter modulation is equal to the that of fundamental.
AIP 3 =
4 α1 3 α3
IIP3: Input referred intercept point OIP3: Output referred intercept point
Pout − IMD3 = 2 ⋅ (IIP3 − Pin )
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MOS transistor Intrinsic gate voltage and gm are the most important factors in RF CMOS.
Drain Gate
G Body
Source MOS Transistor
rg vg’ Cgd Cgs
rds
gmvg’
D Cds S, B
Equivalent Circuit
9
Cutoff frequency: fT For higher fT, increase gm and decrease Cin. Ii
Io
fT: Frequency at which the current gain is unity.
G D Cin
Ii
Vi
gmVi
S
Ii = Iio sin(ωt ) Iio Vi = cos(ωt ) ωCin
Input current Gate voltage
gmIio cos(ωt ) Io = gmVi = ωCin
gm ∴ fT = 2πCin
Output current
Proportional to gm Inversely proportional to Cin
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Amplifier gain For higher voltage gain, increase gm, fT, ro (Q), and decrease input and gate resistance Ig rs Vs Vg
Id Cin
Log (G)
ωg =
gmVg
ro
1 rsCin G≈
G=gmr0
ωT = ωT r 0 ⋅ ω rs
ω0 = For the larger gain
gmro r0 = ωT rsCin rs
1
Fundamentally larger gmr0 G ≈ gmro ≈ Higher fT and lower rs
gm Cin
Ids ⎛ Veff ⎜ ⎝ 2
Log (f)
⎞ ⎟ ⎠
⋅ ro
Veff is difficult to reduce
Larger Ids or ro Larger Q
Q Qro = Qω0L = ω0C
Æ Distortion and Cin increase
11
Characteristics of gm (Basic) Gm is proportional to the Ids and inversely proportional to the Veff. Veff is proportional to square root of Ids and inversely proportional to square root of (W/L) ratio. Square law region
μCOX ⎛ W ⎞
μCOX ⎛ W ⎞
⎜ ⎟(Vgs − VT ) = ⎜ ⎟Veff 2n ⎝ L ⎠ 2n ⎝ L ⎠ dI μCOX ⎛ W ⎞ gm ≡ ds = ⎜ ⎟Veff dVgs n ⎝L⎠
Ids =
gm =
2
2 μCOX ⎛ W ⎞ ⎜ ⎟ Ids n ⎝L⎠
Veff
∝
L
2
1 Ids gm , = gm = ⎛ Veff ⎞ Ids ⎛ Veff ⎞ ⎜ ⎟ ⎜ ⎟ ⎝ 2 ⎠ ⎝ 2 ⎠
Veff =
Ids = L ⋅ Jds W
2n
1 L ⋅ ⋅ ⋅ Ids μ Cox W
Scaling
W/L ratio
Veff is proportional to square root of drain current density. 12
Non-ideal effects to square low region At larger Veff and lower Veff, two non-ideal effects are not negligible . Sub-threshold region
⎛ Vgs Ids = Iso exp⎜⎜ ⎝ nU T Ids gm = nU T
25.083
⎞ ( Weak inversion) ⎟⎟ ⎠ gm 1 eff( 0.4 , 10 , Veff) = eff( 0.2 , 5 , Veff) Ids nU T Gm/Ids (S/A)
Low Veff
30
gm 1 = = const Ids nUT
25
20
gm 2 = Ids Veff
15
10
High Veff
μ≈
Mobility degradation
μ0 μ , θ ≈ θ0 + 0 1 + θVeff vcL
5
1.302
0
0.2 0.2
0
0.2
0.4 Veff
Veff (V)
0.6
0.8 1
This effect becomes larger at large Veff and short channel length. 13
Distortion Lower Veff gives higher gm, bur results in higher distortion. To obtain lower distortion ( higher IIP3), we must increase Veff. Higher gm and lower distortion means higher Ids. 3
1 d 3 Ids + ⋅ ⋅ ⋅ ⋅ a3 ≡ 6 dVeff 3
4 a1 IIP 3 = 3 a3
L=0.1um L=0.2um L=0.4um IIP3
gm/Ids (S/A)
100
10
1 -0.1
Veff (V)
10
1
IIP3 (V)
Ids = a1Veff + a 2Veff + a 3Veff 2
0.1 0
0.1
0.2
0.3
0.4
0.5
Veff (V) 14
LC resonator LC resonator can be regarded as resistance at the resonance frequency.
Q
C L
Substrate
ω0 =
r0
1 LC
Q ro = Qω 0 L = ω 0C 15
Substrate effect Substrate should be treated as resistive network. This substrate resistance causes RF power loss and noise generation. Shielding can reduce this effect. Gate
RF power loss and noise generation
Gate PAD
S D S D S
S D S D S
PAD
Shield layer
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Power loss in substrate Very low resistance or high resistance realizes low power loss. C
Gp
Rp
Higher C and moderate Rsub results in higher power loss.
Cp
Equivalent
G
C
ϖ
p
p
p
=
1 R p
= C
=
⎛ ω ⎜ ⎜ ϖ p ⎝ ⋅ ⎛ ω 1 + ⎜ ⎜ ϖ ⎝ 1
⎛ ω 1 + ⎜ ⎜ ϖ ⎝ 1 R pC
p
⎞ ⎟ ⎟ ⎠
⎞ ⎟ ⎟ ⎠
2
⎞ ⎟ ⎟ ⎠
p
2
Gp(mS)
1
2
Cp(pF) 1
MOS: 10Ωcm GaAs: 1GΩcm
10
100 Rp(Ω）
0.1 1K
10K
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GHz operation by CMOS The cutoff frequency of MOS becomes higher than that of Bipolar. Over several GHz operations have attained in CMOS technology 0.13um 100G
0.18um 0.25um
50G
Frequency (Hz)
0.35um
fT : CMOS fT : Bipolar (w/o SiGe) fT /10 (CMOS )
20G
RF circuits
10G 5G
Cellular Phone
CDMA
5GHz W-LAN
fT /60 (CMOS )
gm fT ≡ 2πCin vsat fTpeak ≈ 2πLeff
Digital circuits
2G 1G
IEEE 1394 D R/C for HDD
500M 200M 100M
1995
2000
2005
Year 18
Effect of parasitic capacitance to fT fT of actual circuit is reduced by a parasitic capacitance. There is an optimum gate width to obtain highest fT. 10 60 6 .10 10 5.786 .10
gm fT ≡ 2π (Cgs + Cgd + Cp ) Cin
Vi
4 .10 4010
fti 0.2 , W , 5 .10 gmVi
3
,0
fti 0.2 , W , 5 .10
3
, 0.1 .10
12
fti 0.2 , W , 5 .10
3
, 0.5 .10
12
fT (GHz)
Cp
Ids=5mA L=0.2um
Cp=0
Cp=0.1pF
(1) 10 2 .1020
(2)
Cin=Cgs+Cgd Cp=0.5pF Region(1); Increased by increasing1.576 gm.109 Region(2); Decreased by increasing Cin
00 0 10
200
400
600 W
W(um)
800
1000 1 .10
3
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fT: MOS vs. Bipolar Even if fT of MOS is the same as that of Bipolar, fT of MOS is easily lowered by a parasitic capacitance. Because, gm of MOS is ½ to ¼ of that of Bipolar at the same current. Small parasitic capacitance is a key for RF CMOS design. MOS
gm fT ≡ 2πCin
Ids gm ≡ ⎛ Veff ⎞ ⎜ ⎟ ⎝ 2 ⎠ Veff min = 2nU T
Ic gm ≡ UT UT ≡
n: 1.4
Veff/2: 50-100mV (actual ckt.)
Bipolar
kT ≈ 26mV q
gmCMOS
4Veff (Full swing) VLO
VLO = ALO cos(ωLOt ) RF spectrum
IF spectrum
FLO dB
dB
Fimage Fdes
Freq
Freq FIF FIF
FIF 30
Image-reject mixers The quadrature mixing realizes image-suppression. Gain and phase matching is needed. LPF Vin (t)
45°
cos(ωLOt ) +
sin (ωLOt ) LPF
Vout(t)
− 45°
Vin (t ) = Ades cos(ωdest ) + Aim cos(ωimt ) Vout (t ) = AdesAc cos(ωIFt ) + AimAcIR cos(ωIFt ) Ac: Conversion gain, IR: Image rejection IR=0 if I/Q phase difference is 90° and Channel conversion gains are equal. 31
Gain mismatch and phase error
Pspur 1 + γ 2 − 2γ cos φ = Pdesired 1 + γ 2 + 2γ cos φ
γ
: Gain ratio
φ
:Phase error
A. Rofougaran, et al., IEEE J.S.C. Vol.33, No.4, April 1998. PP. 515-534.
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Passive FET mixer MOS can realize a passive mixer easily. Ultimately low power, but take care of isolation. Passive FET mixer Vin
Lo
Lo
Vo
Vo
Lo
Lo
Low power High linearity No 1/F noise No conversion gain No isolation, Bi-directional
Vin 33
Active mixers Single balanced mixer
Double balanced mixer Very small direct feed through and even order distortion
Vo
ZL
Lo
ZL Vo M2
M3
ZL Vo
Lo M2 M3
Lo
Vin M1 Zs
ZL Vo
M2’ M3’ Lo
Vin
Lo
Vin M1 Zs
M1’ Zs
34
Active mixer design The larger Ids is needed for high dynamic range and shorter switching time for low 1/f noise. Mixer gain
Gmix =
2
π
gm1ZL , or =
2 ZL π Zs
when Zs is used R : Resistive component in ZL
L Thermal noise v = 8kTRL⎛⎜1 + 2γIRL + γgm1RL ⎞⎟ ≈ 8kTR 2γgm1 L ⎝ πALO ⎠ v on2 γ Veff 2 2 2 2 π π γ kT kT SSBvin = ≈ ≅ 2 Ids gm1 ⎛2 ⎞ 1 L gm R ⎜ ⎟ ⎝π ⎠ A larger dynamic range needs larger current IIP3 ≈ Veff 1/F noise 2 on
1) Switch transistor (M2, M3)
vn , o =
4Ts vn , sw TLO
1 vn2 , sw ≈ WL
∝
1 Cgs
Ts
TLO
Phase modulation
Shorter switching time or larger Ts/TLo ratio 2) Load transistors
Directly produces 35
Oscillator There is an optimum Ids for low phase noise. Vdd Vo
L
L
Vo
L
Q
-1/gm C
C
r0
-1/gm
C
Vc
1) Amplitude condition M3
M2
Oscillation amplitude
Vb
I M1
Vosc =
ro = Qω 0 L =
4 Iro
Headroom limit
π πVdd πVddωoC = Iopt = 2 ro Q
Q ω 0C
2Vdd
(a) 2) Oscillation condition
gm 2,3 >
2 , ro
I>
ωoCVeff , 2,3 Q 36
Phase noise of oscillator Phase-frequency relation and resonator characteristics determine phase noise.
v(t ) = A cos[ω 0t + φ (t )]
1 2QL = Bw ω 0 R Z ( jω )
dφ = jωφ dt
ωm
Sω (ωm) = ωm2 Sφ (ωm )
Sω (ωm)
:Noise spectrum density on offset angular frequency
Sφ (ωm )
:Noise spectrum density on phase
ωm = Bw
0.7R
Δθ =
ω φ
dφ =
2QL
ω0
ω ω0
dω
ωm Bw
=
2QL
ω0 2
ωm
⎛ ω0 ⎞ ⎟⎟ SΔθ (ωm ) Sω (ωm) = ⎜⎜ ⎝ 2QL ⎠ 2
Δθ SΔθ (ωm )
: Offset angular frequency
Phase error between in and out :Noise spectrum density on phase error
ωm < Bw 2
⎛ ω0 ⎞ 1 ⎛ ω0 ⎞ ⎟⎟ 2 SΔθ (ωm ) = ⎜⎜ ⎟⎟ SΔθ (ωm ) Sφ (ωm) = ⎜⎜ ⎝ 2QL ⎠ ωm ⎝ 2QLωm ⎠ 37
Phase noise of oscillator Z (ω 0 + ωm ) ≈ j L
Q
C
-1/gm
-1/gm
r0 ω0L
(Filter action)
⎛ ω0 ⎞ vn2 in2 2 ⎟⎟ = ⋅ Z = 4kTro⎜⎜ Δf Δf ⎝ 2Qωm ⎠
R 0.7R
Q=
ωm
