RF low-noise amplifiers in BiCMOS technologies - Circuits and

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 46, NO. 7, JULY 1999

is a crucial component in the DC ZEDS, and this first set of units has established a landmark for future endeavors. Control algorithms were evaluated based on specification requirements and implementation issues. DSP hardware was iteratively designed to meet all transient and paralleling requirements. Further, the units are now being retrofitted with a programmable universal controller that is TMS320 based. This will present a totally digital solution for the controller and allow flexibility in algorithm modification. REFERENCES

Fig. 5. Plot of the output voltage for two parallel SSCM’s during a transient from 100 to 150 kW and from 150 to 100 kW (10 V/div and 0.1 s/div).

speed of the algorithm significantly. Therefore, the card was not used for the main control algorithm, but was used to set the converter switching frequency, monitor-sensored voltages and currents, and establish an RS422 port. With the control law jumper in digital mode, the chopper operated, but was unable to maintain a nominal output voltage within 625 V, given a 50% step load change. Further, when paralleling two units while operating in regulated mode, the output voltage oscillated at approximately 1 Hz (the frequency difference between each of the SSCM control units’ crystal clocks). A final complete digital solution is now being implemented using a programmable universal controller developed at NSWC. The new digital card is the subject of a future paper. VI. EXPERIMENTAL RESULTS The SSCM with analog control was found to satisfy all system specifications during each hardware test. A step load change of 50%–100%–50% caused a transient in the output voltage (750 V nominal) of less than 67 V, as shown in Fig. 4. The transient performance of the two SSCM units operating in parallel is documented in Fig. 5 for a step load change of 100–150–100 kW. The output bus voltage transient decays rapidly with a variation of less than 65 V from the nominal value. While paralleling the units at 200 kW, the output current was matched to within 1%. However, at 25 kW, which is near discontinuous conduction, the matching was only within 15%, but quickly improved to within 3.5% as the power level was increased to 50 kW. The mismatch at low power levels is more pronounced, since the converters were calibrated at full load. Consequently, there is a small variation in the droop slope between units. Isolated units remained stable over all ranges of voltage and power. The units operating in the discontinuous region had significantly longer settling times and larger output voltage transients when given step load changes. VII. CONCLUSION The U.S. Navy has selected dc distribution and a more-electric approach for the 21st century surface combatant vessels. The SSCM

[1] T. Dade, “Advanced electric propulsion, power generation, and power distribution,” Naval Eng. J., vol. 106, no. 2, pp. 83–92, Mar. 1994. [2] C. Petry and J. Rumburg, “Zonal electrical distribution systems: An affordable architecture for the future,” Naval Eng. J., vol. 105, no. 3, pp. 45–51, May 1993. [3] N. Doerry and J. Davis, “Integrated power system for marine applications,” Naval Eng. J., vol. 106, no. 3, pp. 77–90, May 1994. [4] J. Mayer and F. Salberta, “High-frequency power electronic converter for propulsion applications,” Dept. Elect. Eng. Applied Res. Lab., Pennsylvania State Univ., University Park, PA, Jan. 1997. [5] J. Dabney and T. Harman, Mastering SIMULINK 2. Englewood Cliffs, NJ: Prentice-Hall, 1998. [6] P. Liu and P. Sen, “A novel method to achieve zero-voltage regulation in buck converter,” IEEE Trans. Power Electron., vol. 10, pp. 292–301, May 1995. [7] B. Choi, B. Cho, F. Lee, and R. Ridley, “Three-loop control for multimodule converter systems,” IEEE Trans. Power Electron., vol. 8, pp. 466–474, Oct. 1993. [8] F. Garofalo, P. Marino, S. Scala, and F. Vasca, “Control of DC-DC converters with linear optimal feedback and nonlinear feedforward,” IEEE Trans. Power Electron., vol. 9, pp. 607–615, Nov. 1994. [9] J. Kassakian, M. Schlect, and G. Verghese, Principles of Power Electronics. Norwell, MA: Addison-Wesley, 1991. [10] SBC31 Hardware Manual, Innovative Integration, Westlake Village, CA, 1994.

RF Low-Noise Amplifiers in BiCMOS Technologies Flora Carreto-Castro, Jose Silva-Martinez, and Roberto Murphy-Arteaga

Abstract— This paper deals with the design of low-noise amplifiers (LNA) fabricated in BiCMOS technologies. The LNA’s are based on an active inductor, which makes the topologies less sensitive to temperature variations and reduces the effects of process parameter tolerances. Experimental results show a 10-dB voltage gain at 1 GHz and unitygain frequencies of 3.6 GHz. The noise figure, measured at 1 GHz, is 3.4 dB. The preamplifier has been fabricated using a 10-GHz BiCMOS technology.

I. INTRODUCTION Due to the growing demand for monolithic radio frequency (RF) receivers for wireless communications, much attention has been paid to the design of low-noise amplifiers (LNA’s) and mixers Manuscript received October 16, 1998; revised March 12, 1999. This work was supported in part by CONACYT under Contract 2112-90-5-CO32A. This paper was recommended by Guest Editors F. Maloberti and G. Roberts. The authors are with the National Institute for Astrophysics, Optics, and Electronics, Electronics Department, Integrated Circuits Design Group, 72000 Puebla, Mexico. Publisher Item Identifier S 1057-7130(99)05650-5.

1057–7130/99$10.00  1999 IEEE


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Fig. 1. Active implementation of a grounded inductor. Fig. 3. A single-stage low-noise amplifier employing the active inductor.

(a)

(b)

Fig. 2. (a) Bipolar transistor implementation of the active inductor and (b) small signal equivalent circuit. Fig. 4. A two-stage low-noise amplifier.

in a single-integrated circuit [1]–[6], [8]. It has also been shown that important parameters such as noise figure, reduced harmonic distortion components, low power consumption, small silicon area, and low sensitivity to temperature variations are difficult to satisfy at the same time. Nevertheless, a good tradeoff can be obtained by using special design techniques [2]. Inductors are fundamental elements for the implementation of RF circuits; they are typically implemented by using circular or rectangular spirals. The on-chip inductors consume silicon area, are sensitive to temperature variations, their quality factor is limited, and they are not precise even if the technology is well characterized [3], [4], [6]. Active inductors have been extensively used for lowfrequency applications [7], and more recently, for the design of mixers [8]. In this work, a high-frequency active inductor that presents a high quality factor is proposed. In addition, other important specifications, such as noise figure and harmonic distortion components, can be maintained at low levels. Based on this inductor, two low-noise preamplifiers have been developed. The paper is organized as follows. The active inductor is described in Section II. The LNA’s are introduced in Section III. In Section IV, experimental results for the two-stage low-noise preamplifier are presented. At the end of the paper, some conclusions are given. II. ACTIVE INDUCTOR FOR HIGH-FREQUENCY APPLICATIONS A grounded inductor can be implemented by using voltage-tocurrent transducers [7], as shown in Fig. 1. By using typical circuit analysis techniques, it can be easily shown that the input impedance is given by

zi =

vi ii

=g

C s m gm

(1)

where gm and gm are the small-signal transconductances of OTA1 and OTA2, respectively. In this topology, the input voltage is converted to current by OTA1, and it is integrated by the capacitor; then the resulting voltage is converted to current by OTA2 and injected to the input. Based on this circuit, a grounded inductor can be implemented by the structure shown in Fig. 2(a). The behavior of

the topology can be explained by exploring its simplified small-signal equivalent circuit depicted in Fig. 2(b). 0 In the equivalent circuit, RP represents the series of RP and the transistor’s base resistance. The transistor’s parameters gm ; r; C ; and C are the small-signal transconductance, base–emitter resistance, base–emitter capacitance, and base–collector capacitance, respectively. For simplicity, we are neglecting the collector–emitter resistance and the parasitic capacitors associated with both collector and current source. At frequencies such that the effects of r and C 0 1=!C ; then RP0 converts the input can be neglected, and if RP voltage to current and this current is integrated by C . The voltage v is converted to current by the voltage controlled current source and fed back to the input. Since the collector current is larger than the base current, and considering the small-signal equivalent circuit shown in Fig. 2(b), the input impedance can be obtained as

v Zi = i ii

= 1

gm

1 + sRp C (1 + sRp C ) 1 + sC 1 +rg 0

0

:

(2)

m r

Note that the input impedance of the next stage has not been considered in this analysis, it will be accounted for in the next section. 0 For frequencies such that (RP C )01 < ! < (RP0 C )01 (2) can be approximated as follows:

R0 R0 C Zi (3) = s gpm = s !Tp = sLeq where !T (=2fT = gm =C ) is the transistor’s unity-gain fre-

quency. In accordance with (3), at medium frequencies the structure 0 and behaves as an inductor. The inductance is proportional to RP inversely proportional to the transistor’s unity gain frequency; these 0 < 300

characteristics will be exploited in the next sections. For RP and fT = 10 GHz, inductances in the range of 5–20 nH can be efficiently implemented. The low-frequency behavior of the inductor 0 C )01 ; for practical designs it is is limited by the zero located at (RP 0 C )01 ; in the range 100–200 MHz. The high-frequency pole, at (RP is typically around 2–3 GHz.

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Fig. 5. Microphotograph of the LNA’s and calibration structures.

For high gain amplifiers, the LNA’s noise level is dominated by the first stage [2]; in this case, the noise figure can be approximated as follows:

TABLE I SUMMARY OF THE EXPERIMENTAL RESULTS FOR THE TWO-STAGE LNA

NF =1+

rb1 RS

2 qIC 1 + jZ1 +g2rbj1Z+1 j2RS j 42kT RS m1

where

Z1 = r1

III. LOW-NOISE AMPLIFIERS

= 0 !T 1 RP !T 2 R 0

0

S

1 1 CL RP 1 + s 1 !T 2 1 + C2 + RL + s2 0

RP CL !T 2 0

(4) where gm1 is the transconductance of Q1; RS is the equivalent input resistance (source resistance, base resistance of Q1; and emitter inductance reflected to the base); RL and CL are the load resistance and load capacitance, respectively. Below the pole’s frequency, the voltage gain is determined by the ratio of resistors; hence it presents low sensitivity to temperature variations. Note from (4) that the voltage gain presents a low-pass behavior, wherein the frequency of the poles is given by 0

!P

=

!T 2 RP CL 0

=

1

Leq CL

:

(5)

According to this expression, the higher the active inductance, the lower the amplifier’s bandwidth is. It is important to reduce the input capacitance of the next stage, otherwise the frequency response could be further degraded. From (4), the pole’s quality factor of the LNA is

Q =

1

1 + CCL2

+ RRPL 0

!T 2 RP CL : 0

:

In (7), we have considered that IC 1 is high enough (>0.5 mA). The noise figure is clearly limited by the base resistance rb1 ; in order to achieve low noise figures, small base resistance transistors and optimum input bias conditions are required. Because the active inductor is at the output of the LNA its noise contribution is reduced due to the gain factor, the LNA is biased using the technique proposed in [2], further details can also be found in [9].

Based on the inductor of Fig. 2, a single-stage LNA can be implemented, as shown in Fig. 3. The inductor Le is used to match the input impedance, sometimes another inductor connected at the base of Q1 is also used [1]. By employing typical circuit-analysis techniques and considering that the active inductor is characterized by (3), the small-signal voltage gain can be shown to be

v0 vi

1

j!C1

(7)

(6)

Peaking effects in the voltage gain of the LNA are avoided if Q < 1; this can be easily guaranteed by increasing RL . If the first-stage’s voltage gain is not high enough, then a second stage can be used, as shown in Fig. 4.

IV. EXPERIMENTAL RESULTS The low-noise amplifiers were fabricated in a 1.2-m BiCMOS technology. A microphotograph of the chip is shown in Fig. 5. The single-stage and two-stage LNA’s are located at the right and left hand side of the microphotograph, respectively. For characterization purposes, several calibrating structures have also been included. Bias currents for transistors Q1 and Q2 were 2.5 and 1 mA, respectively. The inductance of Le is around 0.5 nH. The active area, including the pads, of the two-stage LNA is only 0.6 mm2 ; the area of the entire chip is 2.2 mm2 . The preamplifiers are biased with a 3 V supply voltage. Simulated results for the two-stage LNA, 15-dB voltage gain, have shown noise figures of 3.1 dB at 1 GHz, and input reflection coefficients of 010 and 012 dB at 1 and 2 GHz, respectively. Temperature simulations for 050 , 27 , and 80 have shown variations in the midband voltage gain of 61 dB. This result was expected because the maximum voltage gain depends of the ratio of resistors. For the same temperature variations, the 10-dB gain frequency varies within the range of 1.6–0.95 GHz; from (5), it can be noted that the frequency of the poles is more sensitive to temperature variations. The measured voltage gain for the two-stage LNA, upon deembedding [10], is shown in Fig. 6. At medium frequencies, e.g., 0.5–1 GHz, the voltage gain is around 12.5 dB; the LNA was designed for 15-dB voltage gain. This error is due to the process parameters 0 tolerances, especially in RP . The voltage gain is larger than 10 dB for frequencies up to 1 GHz, while the unity gain frequency is 3.6 GHz. Experimental results for the bipolar transistors have shown unity gain frequencies of 9–10 GHz. The input reflection coefficient at 1 GHz is around 08 dB. Fig. 7 shows the measured output spectrum for the two-stage LNA performed at the 1-dB compression level. According to this result, the input 1-dB compression level is around 025 dBm. The measured


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Fig. 6. Measured voltage gain and input reflection coefficient for the two-stage LNA.

use of expensive technologies. For a voltage gain of 10 dB at 1 GHz, noise figures below to 3.4 dB have been achieved. ACKNOWLEDGMENT The authors wish to thank the reviewers for their fruitful comments. The chip was characterized using the facilities of the Microwave Laboratory of the Large Millimeter Telescope (INAOE). The support, during the characterization of the chip, of R. Rojas, C. Juarez, and M. Mendez is also recognized. REFERENCES

Fig. 7. Measured output spectrum for the two-stage LNA.

noise figure at 1 GHz is around 3.4 dB, this value is in good agreement with the expected one. A summary of the results is given in Table I. Similar results have been obtained for the one-stage LNA but the voltage gain is limited to 8 dB [9]. V. CONCLUSION An active inductor for high-frequency applications has been proposed. The inductor is based on the gyrator principle, and a resistor controls its inductance. Using this active inductor, two low-noise amplifiers have been designed. The performances of the two-stage’s LNA are comparable to previously reported structures but avoid the

[1] P. Mole and K. Searle, “RF design in GaAs and BiCMOS,” in Circuits and Systems Tutorials, ISCAS’94, ch. 9.3. [2] R. G. Meyer and W. D. Mack, “A 1-GHz BiCMOS RF front-end IC,” IEEE J. Solid-State Circuits, vol. 28, pp. 350–355, Mar. 1994. [3] J. R. Long and M. A. Copeland, “A 1.9 GHz low-voltage silicon bipolar receiver front-end for wireless personal communications systems,” IEEE J. Solid-State Circuits, vol. 30, no. 12, pp. 1438–1448, Dec. 1995. [4] D. H. Shen, C. M. Hwang, B. B. Lusignan, and B. A. Wooley, “A 900-MHz RF front-end with integrated discrete-time filtering,” IEEE J. Solid-State Circuits, vol. 31, pp. 1945–1953, Dec. 1996. [5] A. N. Karanicolas, “A 2.7-V 900-GHz CMOS LNA and mixer,” IEEE J. Solid-State Circuits, vol. 31, pp. 1939–1996, Dec. 1996. [6] D. K. Shaeffer and T. H. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE J. Solid-State Circuits, vol. 32, pp. 745–759, May 1997. [7] J. Silva-Mart´ınez, M. Steyaert, and W. Sansen, High-Performance CMOS Continuous-Time Filters. Norwell, MA: Kluwer, 1993. [8] P. R. Kinget and M. S. J. Steyart, “A 1-GHz CMOS up-conversion mixer,” IEEE J. Solid-State Circuits, vol. 32, pp. 370–376, Mar. 1997. [9] F. Carreto-Castro, “Low-noise amplifiers in BiCMOS technologies,” Ph.D. dissertation, National Inst. Astrophysics, Optics, Electron., Puebla, Mexico, Mar. 1998. [10] R. Murphy-Arteaga, “Prospects for the MOS transistor as a high frequency device,” Ph.D. dissertation, National Inst. Astrophysiccs, Optics, Electron., Puebla, Mexico, July 1997.