This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
1
Robust Hybrid Memristor-CMOS Memory: Modeling and Design Baker Mohammad, Member, IEEE, Dirar Homouz, and Hazem Elgabra
Index Terms— Emerging technology, low power, memristor, nonvolatile memory, semiconductor memory.
I. I NTRODUCTION
U
SING symmetry arguments, the memristor was postulated by Chua [1], [2] in 1971 as the fourth fundamental circuit element. The memristor is an element that connects magnetic flux to electric charge in the same way that resistor connects voltage to current, capacitor connects voltage to charge, and inductor connects flux to current [Fig. 1(a)]. Chua showed that memristors are characterized by a pinched hysteresis loop [Fig. 1(c)]. It was also shown that memristors cannot be described by one equation. Characterizing a memristive system requires at least two equations. The memristor was realized as a physical device only recently by HP labs. The HP memristor consists of a bipolar TiO2 thin film [3] [Fig. 1(b)]. This discovery spurred a great interest in memristors. Memristors are considered as one of the possible future alternatives to current CMOS technology. Memristor-based technology provides much better scalability, higher utilization when used as memory, and overall lower power consumption [4]. One obvious and an important field in which memristors can have a major impact is memory. Current CMOS-based Manuscript received December 31, 2011; revised September 24, 2012; accepted October 18, 2012. This work was supported by the Khalifa University of Science, Technology and Research, Abu Dhabi, United Arab Emirates. The authors are with Khalifa University, Abu Dhabi 127788, UAE (e-mail:
[email protected];
[email protected]; 100032876@ kustar.ac.ae). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TVLSI.2012.2227519
(c) 1
1
0
0
-1
-1
0 x 10
(b)
-4
Current I [A]
x 10
Voltage v [V]
(a)
Current I [A]
Abstract— In this paper, we explore various aspects of memristor modeling and use them to propose improved access operations and design of a memristor-based memory. We study the current mathematical and SPICE modeling of memristors and compare them with known device specifications. Based on this survey of existing models, we adopt an improved mathematical model of the memristor that captures the well-established features of memristive devices. This modeling is used to analyze the time and voltage characteristics of stable read and write operations. The tradeoffs between the various design parameters such as voltage, frequency, noise margin, and area are also analyzed. Based on the device modeling, we propose a hybrid CMOS-memristor memory cell and architecture that addresses the limitations of memristor such as state drift, cell-cell interference, and refresh requirements. Memristor is used as a state element, and CMOSbased transistors are used to isolate, control, decode, and inter operate the logic. We verify our design using SPICE simulation using a 28-nm model for CMOS and a modified memristor model.
1 0.5 0 -0.5 -1 -1.5 -1.5
-4
-1
0.5 Time t [s]
1
-0.5 0 0.5 Voltage v [V]
1.5
1
1.5
Fig. 1. (a) Memristor as the fourth fundamental circuit element. (b) HP memristor device consisting of a thin film of TiO2 of width D. This thin-film is divided into an O2+ doped region (of width w) and an undoped region. (c) Behavior of a memristor when driven by a sine wave source (top). The current starts slow in first quarter wave (high resistance), and then becomes higher in the second quarter (low resistance). This mode of operation is characterized by the pinched hysteresis loop in the I −V diagram (bottom).
memory technology faces many challenges in its pursuit to meet the increasing demand for faster processing and larger data size. For instance, static random access memory (SRAM), the most widely used on-chip memory (due to its fast access time and relatively small size) is reaching its physical limits in achieving higher densities and lowering power consumption. In addition, progress in utilizing other emerging memory technologies (such as eDRAM, mRAM, and PCRAM) is hindered by their lack of compatibility with CMOS, their slow access time, and their limited scalability [5]. Thus, memristors can play an important role in improving the scalability and efficiency of existing memory technology. A memristor is a two-terminal circuit element that operates in one of two nonvolatile resistive states (ON or OFF). These unique characteristics of memristors give them an important role in shaping the future of semiconductors, as they hold many advantages over transistors. Memristors consume much less power than transistors as they do not require a minimum voltage to sense their state (threshold voltage) or need power to retain; thus, it is a leakage-free nonvolatile memory. In addition, the small size of a memristor (
BL
BLB
W ordline decode
2
T1
MR
1 W L
N um ber of W L (row s)
W L
BL BL
C ol. ad dress
I/O circu it
T1
I/O circu it
w l0
BL
B LB WL
T1
MR
R o w address
clock
Re ad/w rite
I/O circu it
MR
I/O circu it
D ata
A rra y
B LB
WL
W L
C o n tro l
B LB
w l1
P e rip h e ry lo g ic
M e m o ry ce ll BL
B LB
B LB
T4
P re _ ch
T2
T3
clk w re n
V ref
P re-ch a rg e rd e n
BL
(c)
w re n
S e n se_e n
V re f
of state drift in memristors during read or write access. For example, a positive read access bias at the doped region of the memristor will cause the state of the memristor to drift toward the ON state. On the other hand, a negative bias will cause a drift toward the OFF state. Thus, reading a memristor in the ON state with a negative voltage will ultimately destabilize this state, whereas reading it in the OFF state with a positive bias will ultimately destabilize this state as a result of the repeated reads. The other issue that one has to deal with is the stability of the write operation. The repeated writing process will cause the state of the memristor to drift one way or the other. The design of the memristor-based memory subsystem using memristor needs to tackle all of these limitations and mitigate them. Our mathematical and SPICE modeling of the device enable us to explore all parameters that affect device stability. The following are some of the important points emerging from our detailed analysis. 1) The voltage level has a big impact on the state drift. Thus, low voltage during read access is desirable. 2) The width of the read pulse also impacts the state drift (increased flux). 3) Using a decaying voltage enhances the read stability. 4) Read current should be applied in the OFF direction because: a) the discharge time for the ON state is much smaller than OFF state; b) switching the device OFF is much slower than turning it ON. 5) Number of read operations also impacts the state, as it also increases the flux and causes state drift.
D ata_out
D ata_in
D a ta _In
Proposed hybrid RRAM showing read (write) current direction.
D ata_out
Fig. 9.
IO C ircu it D ata_in
S e n se _ e n
Fig. 10. (a) Proposed memory array architecture with major signal interfaces. (b) Detailed schematic representing one column and detailed slice of the array. (c) Detailed schematic of the IO slice showing logic used to control the read and write access.
is connected to the bitline bar (BLB) and the WL control transistor that is connected to the BL line. The memory cell design reduces the impact of state drift and enhances the overall cell stability. This is achieved by restricting the read current to only go from the BLB to BL (OFF switching direction). As stated above, pushing the memristor from the ON state toward the OFF state is always slower than driving in the other direction especially at low voltage (read voltage). In addition, if the memristor is already in the OFF state, then the read operation effect is minimal. In our proposed cell, the nMOS transistor T1 is used to control access to the memristor MR. When WL is at logic 1 (high) for either read or write, T1 is on and it can pass current in both directions. When the T1 is at logic 0 (OFF), the memristor is in retention state and no current can flow through it. No power is needed to maintain state for the memristor. So, this cell design supports nonvolatile memory. Fig. 10 shows how the memory cells are organized in the proposed memory array. The array contains the main blocks, which include control block to generate the control signals to trigger memory access, the wordline (WL) block to select the entry (row), and the IO block to sense and relate the input and output data from and to the array. All control signals and logic are similar to those of SRAM-based memory [24]. The detailed description of the memory operations using the 1T1M cell are given in the following subsections. C. Write Operation
B. 1T1M Memory Cell In this paper, we present a memory cell design that takes the above points into consideration. Our proposed memory cell is shown in Fig. 9. The cell is made of only one access control transistor (T1) and a memory storage memristor (MR). Fig. 9 shows one memory cell and its possible interface connections to other cells as well as the IO circuitry. The memory cell
Memory access starts with selecting the row from the array (Fig. 10). BL and BLB are then connected to data (d) and the complement of data (db), respectively, and the write current flows through the MR which might change the device state (resistance). Thus, if we maintain the current for sufficient time, we can write the device in one of the two states. If data is logic 1, then the write current Iwrite goes clockwise and MR will be turned on (low R). If, on the other hand, the data
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. MOHAMMAD et al.: ROBUST HYBRID MEMRISTOR-CMOS MEMORY
Fig. 11.
9
(a) Write operation showing write time for different voltage level. (b) Read operation for both states of the memristor.
is at logic 0, then db is at logic 1 and current flows in the counterclockwise direction, which pushes the memristor state toward the OFF state. To reduce the effect of the state drift during the write process, we plan to always carry out the read operation before any write. If the stored data in a specific column has the same value as the current write data, then write enable will be off for that column. However, the write operation proceeds whenever the stored data and write data are different. The detailed IO schematic in Fig. 10(b) shows one implementation of the read-write operation. This approach saves write power because write operations require higher voltage and longer time to finish. The read operation time is much shorter than that of write operation, so the added cost to total write timing is minimal. D. Read Operation For a read operation, a voltage sense amplifier is used which requires the BLB node to be always preconditioned to logic 1 (pre charged high) before the read cycle. Also, during the read phase, the BL node will be pulled low and the selected row WL will be asserted (ON), which causes a discharge of the BLB node through the MR element. The voltage level on BLB is now controlled by the value of M R through the RC constant. At the end of read phase, the sense amplifier gets activated and latches the data to be ready for output. VI. M EMORY A RCHITECTURE AND SPICE S IMULATION A. Memory Architecture We propose a memory array architecture compatible with mainstream memory (SRAM) technology, like the one shown in Fig. 10(a). CMOS-based logic is used for selecting and
sensing the data, while the memristor element is used as a nonvolatile storage. This design facilitates the fabrication process with the existing CMOS practices. We envision that the thin-film memristor can be realized using the stacking and metallization layers of the basic CMOS technology, and all the substrate layers can be dedicated to logic and control active devices. Interface signals needed to access the array are also compatible with mainstream CMOS-based memory where read, write, address, data in, and data out are the main signals. The readbefore-write operation needed for cell stability is implemented in the column IO circuit to minimize overhead. Since this operation is not normally needed by the program flow, it can be made transparent to the system and will only look like a write operation. Fig. 10(b) shows the proposed IO logic for one slice of the array; RDEN and WREN are the read enable and write enable, respectively, and PRE_CH is used to condition the BL line for read access. Fig. 10(c) shows the detail of one column of the memory array with as many cells as the number of rows. All BLB and BL of the cells are shorted together and then fed into the IO circuitry. B. SPICE Simulations We start our SPICE simulation using the SPICE netlist similar to the one in [10] for the memristor and a 28-nm CMOS process technology from predictive models [25]. A voltage sweep of the memristor write operation is done to identify the write time and write voltage. Fig. 11(a) shows the waveform of the write voltage and the state node switching time from the OFF state to ON state. Since the 28-nm maximum voltage is 1 V, we selected that voltage which corresponds to ∼50 ns ON switching time for the memristor. For the read
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. 10
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
operation, we precharge the BLB line to precondition the cell. We also characterize the read operation for both states 0 (high R) and state 1 (low R) of the memristor. Fig. 11(a) shows the waveform of WL and BLB as a function of time. There is a clear separation between state 0 and state 1 of the memristor. After studying the memristor HSPICE model and running stand-alone read and write to verify that the model is working, we built one column schematic similar to Fig. 10(c) using cadence tools and 28-nm process technology. Fig. 11(b) shows the waveform of multiple write and read cycles. The frequency limiter for this design is the write operation, as discussed earlier, so we propose using two cycles to write and one cycle to read. The sequence of signal transitions is as follows: Access starts by selecting the word line. If we do a read access only, RDEN will be asserted and then the sense amplifier will be asserted after a small delay. If a write operation is needed, then RDEN first will be asserted to access the stored data and, after that is finished, the WREN will be activated. The logic guarantees that, if the write data is the same as the stored data, write will be disabled for the corresponding column. Fig. 11(b) illustrates the waveform from SPICE simulation of different basic operations of write and read. A write operation is shown in Fig. 11(b) in cycle 1. The state variable of the memristor, x, transitions from logic 0 to logic 1. The next cycle is used to precondition the BLB to logic 1 by de asserting the PRE_CH signal. Cycle 3 is a read operation; BLB is shown to be discharging slowly through the MR element while BL is discharged much faster as it does not go through the MR element. Since the MR state is in the ON state, the voltage discharges fast during this operation. Cycle 4 is a write cycle to put the MR in the OFF state. Cycle 5 is another read cycle, and one can notice the difference between BLB and BL, where BLB almost stayed at logic 1 because MR is in OFF state and its resistance is high in the mega ohm order. The results of our simulations of this discharge [Fig. 11(a)] show a clear separation between logic 0 and logic 1 during the read operation. We used 20 fF on the BL and BLB to account for BL capacitance. This is a typical capacitance for the 128-row memory array in 28-nm technology. The design is scalable and more rows can be added to design to tradeoff speed with area utilization. The other cell parameter that we looked at is the number of read operations that can go through without destabilizing the memory cell. Fig. 12 shows the SPICE simulation results of repeated read operations where the state of the memristor is represented by voltage V (w) in the SPICE model. The state drifted from the 0.95 to 0.93, which is still within the noise margin between state 0 and state 1 of the memristor (Fig. 8). Our estimate is that state 1 can go down from x = 0.95 to x = 0.83 and still have enough noise margin to separate it from state 0. This noise margin allows us to do ∼10 000 read accesses before requiring a refresh write cycle. VII. S UMMARY AND F UTURE W ORK In this paper, we analyzed the write and read behavior for a memristor-based memory. This analysis was based on
Fig. 12. SPICE simulation of multiple read operations with state drift from 0.95 to 0.934.
surveying three different types of existing mathematical models: linear, nonlinear, and exponential drift models. This survey showed that the exponential model is the most appropriate one to describe real memristor devices. The exponential model is highly nonlinear in voltage, which captures the effects of large fields that drive the memristive behavior. In addition, it provides the model with the necessary voltage sensitivity needed to represent flexible behavior. Our MATLAB simulations results using the exponential memristor model showed that there is an important tradeoff that has to be considered when designing a memristor-based memory. Memristors with stable read behavior tend to have large switching (or writing) times. To alleviate this conflict, we suggested reading the memristor by a decaying voltage. This could be achieved by discharging a precharged capacitor through the memristor. This RC constant for a memristor is much smaller in the ON state. Thus, the difference between the two states can be read in a very short time. With this approach, we can have more control on managing and enhancing the read stability. This can be done by applying a negative voltage to the doped region. This voltage will have no effect on the stability of the OFF state. It will also have a minor effect on the ON state because of the small RC constant. The enhanced stability achieved via this read process will reduce the rate of data refresh cycle, there by reducing the power consumed. In terms of the write access, high voltage will be used to achieve fast switching. In addition, we avoid rewriting the same data by running a read operation before every write. This added step will eliminate the state drift during the write access and also save time and power due to the fact the read access is much faster and consumes less power with its small signal swing. Our results also highlight some of the inherent problems in existing memristor models. First, there is a large difference in the behavior of different models. Most of the existing models do not agree with the little available experimental data on memristors. We plan to continue this thorough investigation
This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. MOHAMMAD et al.: ROBUST HYBRID MEMRISTOR-CMOS MEMORY
of these mathematical models in order to introduce a more realistic model. We plan to design this model to address the drawbacks in existing models and also to take into consideration the natural asymmetry between the two switching times (ON and OFF). This difference can play a major role in optimizing the write and read process in a memristor-based memory. ACKNOWLEDGMENT The authors would like to thank I. Farahat, A. Al-Hosani, and O. A. Rayahi, for their help. R EFERENCES [1] L. O. Chua, “Memristor-the missing circuit element,” IEEE Trans. Circuit Theory, vol. 18, no. 5, pp. 507–519, Sep. 1971. [2] L. O. Chua and S. M. Kang, “Memristive devices and systems,” Proc. IEEE, vol. 64, no. 2, pp. 209–223, Feb. 1976. [3] D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, “The missing memristor found,” Nature, vol. 453, pp. 80–83, May 2008. [4] O. Kavehei, A. Iqbal, Y. S. Kim, K. Eshraghian, S. F. Al-Sarawi, and D. Abbott, “The fourth element: Characteristics, modelling and electromagnetic theory of the memristor,” Royal Soc. A, Math. Phys. Eng. Sci., vol. 466, pp. 2175–2202, Aug. 2010. [5] International Technology Roadmap for Semiconductor. (2010) [Online]. Available: http://www.itrs.net/ [6] J. J. Yang, M. D. Pickett, X. M. Li, D. A. A. Ohlberg, D. R. Stewart, and R. S. Williams, “Memristive switching mechanism for metal/oxide/metal nanodevices,” Nature Nanotechnol., vol. 3, pp. 429–433, Jul. 2008. [7] M. D. Pickett, D. B. Strukov, J. L. Borghetti, J. J. Yang, G. S. Snider, D. R. Stewart, and R. S. Williams, “Switching dynamics in titanium dioxide memristive devices,” J. Appl. Phys., vol. 106, no. 7, pp. 0745081–074508-6, Oct. 2009. [8] T. Prodromakis, B. P. Peh, C. Papavassiliou, and C. Toumazou, “A versatile memristor model with nonlinear dopant kinetics,” IEEE Trans. Electron Devices, vol. 58, no. 9, pp. 3099–3105, Sep. 2011. [9] Y. N. Joglekar and S. J. Wolf, “The elusive memristor: Properties of basic electrical circuits,” Eur. J. Phys., vol. 30, no. 4, pp. 661–675, 2009. [10] Z. Biolek, D. Biolek, and V. Biolkova, “SPICE model of memristor with nonlinear dopant drift,” Radio Eng., vol. 18, no. 2, pp. 210–214, 2009. [11] D. B. Strukov and R. S. Williams, “Exponential ionic drift: Fast switching and low volatility of thin-film memristors,” Appl. Phys. A, Mater. Sci. Process., vol. 94, pp. 515–519, Mar. 2009. [12] E. Lehtonen and M. Laiho, “CNN using memristors for neighborhood connections,” in Proc. 12th Int. Workshop Cellular Netw. Appl., 2010, pp. 1–4. [13] E. Lehtonen. (2010). Modeling the HP Memristor with SPICE [Online]. Available: http://www.neurdon.com/2010/07/23/modeling-the-hpmemristor-with-spice/ [14] K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzagolo, D. Murray, N. Vallepalli, W. Yih, B. Zheng, and M. Bohr, “A 3-GHz 70 MB SRAM in 65 nm CMOS technology with integrated column-based dynamic power supply,” IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 146–151, Jan. 2006. [15] B. Mohammad, D. Homouz, O. AlRayahi, H. Elgabra, and A. AlHosani, “Hybrid Memristor-CMOS memory cell: Modeling and design,” in Proc. IEEE Int. Conf. Microelectron., Dec. 2011, pp. 1–6. [16] D. B. Strukov and R. S. Williams, “Four-dimensional address topology for circuits with stacked multilayer crossbar arrays,” Proc. Nat. Acad. Sci. United States Amer., vol. 106, pp. 20155–20158, Dec. 2009. [17] H. Manem, G. S. Rose, X. He, and W. Wang, “Design considerations for variation tolerant multilevel CMOS/nano memristor memory,” in Proc. Great Lake Symp. VLSI, 2010, pp. 287–292. [18] M. Terai, S. Kotsuji, H. Hada, N. Iguchi, T. Ichihashi, and S. Fujieda, “Effect of ReRAM-stack asymmetry on read disturb immunity,” in Proc. IEEE Int. Rel. Phys. Symp., Mar. 2009, pp. 134–138. [19] M.-C. Wu, Y.-W. Lin, W.-Y. Jang, C.-H. Lin, and T.-Y. Tseng, “Lowpower and highly reliable multilevel operation in ZrO2 1T1R RRAM,” IEEE Electron Device Lett., vol. 32, no. 8, pp. 1026–1028, Aug. 2011.
11
[20] W. Y. Cho, B.-H. Cho, B.-G. Choi, H.-R. Oh, K. Sangbeom, K.-S. Kim, K.-H. Kim, D.-E. Kim, C.-K. Kwak, H.-G. Byun, Y. Hwang, S. Ahn, G.-H. Koh, G. Jeong, H. Jeong, and K. Kim, “A 0.18-μm 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM),” IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 293–300, Jan. 2005. [21] L. Goux, K. Sankaran, G. Kar, N. Jossart, K. Opsomer, R. Degraeve, G. Pourtois, G. M. Rignanese, C. Detavernier, S. Clima, Y. Y. Chen, A. Fantini, B. Govoreanu, D. J. Wouters, M. Jurczak, L. Altimime, and J. A. Kittl, “Field-driven ultrafast sub-ns programming in WAl2 O3 TiCuTebased 1T1R CBRAM system,” in Proc. Symp. VLSI Technol., 2012, pp. 69–70. [22] B. Butcher, S. Koveshnikov, D. C. Gilmer, G. Bersuker, M. G. Sung, A. Kalantarian, C. Park, R. Geer, Y. Nishi, P. D. Kirsch, and R. Jammy, “High endurance performance of 1T1R HfO based RRAM at low (< 20 μA) operative current and elevated (150 °C) temperature,” in Proc. IEEE Int. Integr. Rel. Workshop Final Rep., May 2011, pp. 146–150. [23] M. Terai, Y. Sakotsubo, S. Kotsuji, and H. Hada, “Resistance controllability of Ta2 O5 /TiO2 stack ReRAM for low-voltage and multilevel operation,” IEEE Electron Device Lett., vol. 31, no. 3, pp. 204–206, Mar. 2010. [24] B. Mohammad, M. Saint-Laurent, P. Bassett, and J. Abraham, “Cache design for low power and high yield,” in Proc. 9th Int. Symp. Qual. Electron. Design, 2008, pp. 103–107. [25] Predictive Models. (2008) [Online]. Available: http://ptm.asu.edu
Baker Mohammad (M’07) received the B.S. degree from the University of New Mexico, Albuquerque, the M.S. degree from Arizona State University, Tempe, and the Ph.D. degree from the University of Texas at Austin, Austin, all in electrical communication engineering. He is currently an Assistant Professor of electronic engineering with Khalifa University, Abu Dhabi, United Arab Emirates. He was a Senior Staff Engineer and the Manager with Qualcomm, Austin, TX, where he was engaged in designing high-performance and low-power DSP processor used for communication and multimedia application. He was with Intel Corporation, where he was involved in research on a wide range of microprocessors design from highperformance, server chips >100 W (IA-64), to mobile-embedded processor low-power sub 1 W (xscale). He has over 15 years of industrial experience in microprocessor design, particularly on memory, circuit, and physical design. His current research interests include power-efficient computing, particularly low-power, high-yield embedded memory, emerging technology such as memristor, STTRAM, and computer architecture. He has four issued U.S. patents and six pending patents. He has authored or co-authored several papers in digital system design, testing, and yield optimization.
Dirar Homouz received the Ph.D. degree from the University of Houston, TX, in 2007. He is an Assistant Professor of physics with the Department of Applied Math and Sciences, Khalifa University, Abu Dhabi, United Arab Emirates. His current research interests include computational biophysics where he uses molecular dynamics simulations to model protein folding in cell-like environment, and modeling memristive devices for use in hybrid CMOS memory applications
Hazem Elgabra is currently pursuing the B.S. degree in electronic engineering with Khalifa University, Abu Dhabi, United Arab Emirates. His current research interests include nonconventional electronic devices, very large scale integration, and system-on-chip design.
