Sampling of Discontinuous Voltage and Current ... - Semantic Scholar

IEEE Industry Application Society Annual Meeting New Orleans, Louisiana, October 5 - 9, 1997

Sampling of Discontinuous Voltage and Current Signals in Electrical Drives
A System Approach Vladimir Blasko and Vikram Kaura

Walter Niewiadomski

Rockwell Automation - Allen Bradley 6400 W. Enterprise Drive Mequon, WI 53092 USA

SuperTel Technologies 8660 154th Avenue NE Redmond, WA 98052 USA

Abstract – Various methods for sampling of voltage and current signals in electrical drive are analyzed and compared. Two new methods for sampling the discontinuous voltage and current signals in a PWM drive are proposed. The methods are based on sampling the instantaneous values and locally averaged values (over one carrier period) of signals. Analytical expressions for adjustment of digital current regulators and achievable bandwidths with the various sampling methods are derived. The results are experimentally verified.

I. INTRODUCTION The control board of a modern electrical drive comprises of a digital computational processing unit with a certain number of analog and digital inputs and outputs. This basic configuration is universal enough to support, with software changes only, operations of various drives such as: constant V/Hz, encoderless, vector control, DC and regenerative drives. All control algorithms are implemented in software and executed on high speed Digital Signal Processors (DSP) or Motorcontrollers (MC), processing speed no longer being a limiting factor. Shrinking control boards with high degree of component integration, powered by fast processors are not without some problems common to all digital drives. Most of the critical issues which remain to be solved are associated with the interaction between the computing unit ( DSP / MC ) and the rest of the drive. One of these, probably the most important for drive performance, is the conversion of the analog signals into digital signals and their introduction into the computing unit. Sampling of the motor voltages and currents is particularly troublesome because of their discontinuous nature caused by the PWM. These problems have not been investigated and attempts to solve them have been reported in few references only [1-2]. Theoretical background and a practical solution for sampling of average value of motor current (locally averaged over a sampling interval ) is provided in [1]. Using a voltage to frequency (V/F) converter, the input signal (current) was first converted into a pulse train with the frequency of the pulse

train proportional to the input signal. The pulse train was then counted / integrated by a counter which was read every sampling interval. The value in the counter was proportional to the average value of the input signal accumulated over the sampling interval. The authors of [1] were skeptical about sampling the instantaneous value of current due to subharmonics in sampled current signal caused by the ripple current. On the other hand, [2] suggested that it was possible to detect the fundamental component of current by sampling the current at the mid points of zero space vectors in a PWM pulse pattern; the instantaneous value sampled at these points being equal to the fundamental current component. This paper deals with both sampling methods. It proposes original and cost effective solutions for sampling (a) instantaneous value of current of a PWM feed inductive load (like ac motor) and (b) locally averaged values of the load current and the load voltage. Achievable bandwidths of the synchronous reference frame digital current control loops are used as benchmarks for the comparison of various sampling methods. All analytical results are experimentally verified. II. SAMPLING METHODS A. Sampling of instantaneous value of current Reference [3] correlates the space vector PWM with the traditional triangle comparison method. It shows that the mid points of the zero states in the space vector PWM correspond to the peaks of triangle carrier; shown by maximum and minimum points of ut ( at ks=0,1,2...) in Fig. 1(a). Per unit values of the carrier ut, ripple current ia and ripple voltage ua~ are shown for the phase a of a three phase inductive load driven by a triangle comparison PWM in Fig.1(c). A carrier frequency fcarr=1/(2Tsmin) much higher than the frequency of the PWM reference signal was assumed in the analysis. Note that the ripple component passes through zero at peaks of the triangle at kS=0,1,2.. Thus current sampled at these instants corresponds to the fundamental component and is ripple free as suggested in [2]. Sampling period Ts can be selected equal

1

07803-4070-1/97/$10.00 (c) 1997 IEEE

ut

[pu]

1

T s min

0

1

T carr 2

3

ch1

ia k s =t/T s min 4

ch2

ic

A/D

5

MC

-1

ch8

(a)

Ts

cs

T PWM

MUX

T2

(a) Ts

T PWM

cs

T2

t ia

(b) 1

ut

[pu]

ut ic

ic

ia

ch1 ch2 ch2 ch1

u a~

ch8 ut

0.5

(b) 0 Fig. 2. Block diagram of an 8 channel A/D converter (a) and associated timing diagram (b)

ia ~

-0.5 -1

B. Sampling of average value of current or voltage 0

0.5

1 (c)

t/T s min 1.5

2

The average value of a signal uin over carrier period Tcarr=2Tsmin is defined as:

Fig. 1. (a) Triangle wave form ut with definition of sampling and carrier period and (b) triangle voltage ripple components of voltage and current ua~ and ia~ for a three phase PWM controlled load

to (Ts=Tcarr =2Tsmin) or two times smaller (Ts= 0.5Tcarr=Tsmin) than the carrier. A sampling scheme with an A/D converter and an eight channel multiplexer is shown in Fig. 2(a). Conversion start signal (cs), synchronized to the peak of ut with a small advance, is issued by the motor controller MC. This initiates ten consecutive conversions in the order shown in Fig. 2(b). It is assumed that only current signals change substantially during Tsmin and that the other signals on channels 3 to 8 are relatively constant over Tsmin. Phase currents ia and ic are symmetrically sampled before and after the triangle peak. Average of these symmetrical samples is used for further processing. This sampling method gives the values of the currents at the center of the triangle, eliminating the need to use a sample and hold element in current feedback to ensure “simultaneous” sampling of currents ia and ic. Currents sampled at instant ks are available for use in the following interval, practically without any delay. The results of processing of control algorithms are written into the PWM at ks+1.

1 u= 2 Tsmin

( 2 + k s ) Tsmin

∫ u dt

in k s Tsmin

(1)

As a first approximation, the “locally” averaged value u corresponds to the fundamental component of the input signal uin in the middle of the integration interval, i.e. at the instant (ks+1)Tsmin. Because the locally averaged signal u is available for sampling at (ks+2)Tsmin, this method provides very small feedback delay of Tfb=Tsmin= Tcarr /2. Formula (1) also eliminates the induced noise and the need for additional filtering in the feedback signal. Because the feedback signal experiences a very small delay of Tsmin due to local averaging, it still can be used for current feedback. The method to average over a sampling interval is particularly suitable for sampling of more discontinuous signals like PWM created motor voltage. Sampling of the instantaneous value of motor voltage would require heavy filtering with adverse effect on the speed of the control. The hardware implementation of (1), the “averager” with a charge balancing circuit to prevent saturation is shown in Fig. 3. The integration is carried out over the carrier period Tcarr, the sampling interval now being Ts=Tcarr=2Tsmin. The charge on the integrating capacitor is balanced by applying the inverted result of integration from the previous sampling interval (k-1)Ts to the input of the integrator during

07803-4070-1/97/$10.00 (c) 1997 IEEE

the current interval k. For the circuit in the Fig. 3(a) the following is valid : 1 kTs uout (k) =− (2) ∫ (u +U ) dt + uout (k −1) , RC (k −1)Ts in da

by the timer in MC keeps the charge balance of the integrator. Solution presented in fig. 3(b) is a modification of the solution presented in [4], to enable operation with ac quantities.

RC u out ( k − 1)] . (3) Ts Uda is a voltage from D/A converter used for charge balancing. Average value of the input voltage is computed from (2) based on a known Uda , the current sampled value of output and the sampled previous values of the output. To accommodate tolerances of the capacitor, the exact value of time constant RC≈Ts is determined during power up of the drive by applying known calibrating voltage to the input of the averager. Note that the D/A, the A/D and the microprocessor are parts that already exist in the drive irrespective of the use of the averager. The D/A converter in the charge balancing circuit does not have to be of a particularly high resolution. The round off error due to the lack of resolution in one sampling interval will be compensated for in the next one and will appear as non detrimental random noise on the signal. An alternate solution of charge balancing circuit is provided in fig. 3(b). Ub is a fixed, known, voltage selected to be U b ≥ max{ uin } . Change of the duty cycle d

A. Approximation of transfer functions of a plant

U da = − round of [

III. ADJUSTMENT OF REGULATORS

Analysis of the synchronous sampling of instantaneous values versus synchronous sampling of average values will be done for a control loop with a PI regulator and a plant, with transfer functions Fr and Fp respectively [5]: Fr = K r Fp =

Fp =

1 + sTr , sTr

(4)

Kp (1 + sT1 ) (1 + sT2 ) Kp sT1 (1 + sT2 )

,

,

(5a)

(5b)

where Kr and Tr are gain and time constant of the regulator and Kp, T1 and T2 are gain and time constants of the plant, with T1 . The open loop transfer functions Fo is:

C u in

Fo=FpFr ,

R

-

u out

R

(6)

and closed loop transfer function Fc with a unity feedback:

+

Fc=Fo/(1+Fo).

(7)

GND U da

MC

D/A

A/D

(a) C u in

R

+Ub

R

R/2

-Ub

u out

+ GND

-Ub d d

MC

A/D

The current control of a DC motor, decoupled current control of a synchronous reference frame induction motor drive, or a regenerative voltage source converter (VSC) [6], can be reduced to the plant with transfer function (5a). Typically in the drive, one of the time constants is dominant, i.e. T1>>T2. The other, smaller time constant T2, approximates/combines all small time constants in the system. In the current loop, T2 would typically approximate processing delays, PWM delays, sampling and filtering delays in the current feedback signal. The typical current control loop with a PWM and inductive load is given in Fig. 4. It will be used as a basis for the analysis that follows. The transfer functions, consisting of cascade connection of multiple lag elements with time constants Ti, i=1…n, and a transportation delay element with time constant Ts, can be approximated as [5]:

(b) Fig. 3. Signal averager with D/A converter (a) and timer and switch (b) in charge balancing circuit

07803-4070-1/97/$10.00 (c) 1997 IEEE

icmd

+ i

PI Regulator

Processing Delay

PWM

Kr (1 + sTr ) 1 + sTr

1 1+ sTµp

K PWM 1+ sTPWM

Sampling/Feedback Delay

RL Load

1 1 + sT fb

K RL 1+ sTRL

where Tµp is the processing or execution time of the algorithm, Tfb is the delay in the feedback loop dependent on sampling method and filter, and TPWM is the dead time of the PWM. TPWM is equal to one half of the PWM update time. Gain of the current control loop plant is Kp=1/(KPWM R), where KPWM is gain of the PWM. A standard procedure to analyze plant in Fig. 4, which can be reduced to (5a) using (10) and (11), is Technical Optimum (TO). According to this procedure time constant of PI regulator is select to be equal to the dominant time constant of the plant [5]:

u dis

-

+

Fig. 4. Block diagram of a current control loop of a PWM controlled inactive load

e − sTs n

2

n ( sTs ) sT (1 + s + +...) ∏ (1 + sTi ) 1! 2! i =1 1 1 ≈ = ; where n + s T 1 e 1 + s(Ts + ∑ Ti )

∏ (1 + sTi ) i =1

1

=

≈

(8)

i =1

n

T2= Te ≈ Ts + ∑ Ti .

(9)

Tr=TRL=T1.

(12)

This cancels the dominant pole in the open loop transfer function (6) and reduces the closed loop transfer function (7) to the second order system. For a damping factor D = 1 2 , the gain of the PI regulator in this second order system should be: 1 T1 Kr = (13) K p 2T2 The cross over frequency at which the open loop transfer function | Fo(ωc) |=1, with regulator parameters Tr and Kr selected according to (12) and (13) is:

i =1

ωc =

1 T2

2 − 1 0.455 ≈ T2 2

(14)

The transport delay in (8) was approximated with a single time constant Ts after neglecting higher order terms in Taylor series expansion of exponential function. The resulting n+1 lag elements were replaced by a single lag element with the equivalent time constant Te which in equation (5) appears as a time constant T2. It can be easily verified that transport delay and multiple lag elements have faster phase and slower amplitude response degradation with increase of frequency than their single, first order element approximation. Therefore the bandwidth in a real digital system, defined by -3dB amplitude response for a closed loop, is going to be substantially higher then bandwidth defined for fall of phase to -45 deg.

1 ωc ≈ . (15) 2π 1381 . T2 With the above settings, the regulator provides a good response to a step change of the reference. Because of the usually high time constant T1 = TRL, the integral time constant of the regulator Tr, selected according to (12) is also high. The consequence of such an adjustment is a relatively slow response to the disturbance udis.

B. Technical optimum

C. Symmetrical optimum

In the plant of Fig. 4, the dominant time constant is T1=TRL=L/R ,

(10)

where L and R are inductance and resistance of the inductive load. All other much smaller time constants are lumped together into the single equivalent time constant T2: T2=Tµp+Tfb+TPWM ,

(11)

or bandwidth frequency fb: fb =

For a speed control loop with an inertia load or a DC bus voltage control loop with a large capacitor bank, the transfer function (5b) of the plant can be used. For the current control loop with L / R = T1 >> T2 , the term jωT1 >> 1 in the vicinity of cross over frequency and the transfer function of plant (5a) can be approximated with the transfer function (5b). The open loop Bode plot of such a plant with a PI regulator is given in Fig. 5.

07803-4070-1/97/$10.00 (c) 1997 IEEE

Magnitude [dB]

60

(-2)

depending on the primary objective: rejection of the disturbance or following of the references signal with a small overshoot. The above equations suggests that Kr can be kept constant according to (13) and Tr reduced for improved disturbance rejection with the value given by (17) as the upper limit.

ω c = 2π f b (-1)

0

1 Tr

-60 2 10

10

3

1 T2

(-2)

10

4

ω [rad / s] 1 0

5

Phase [deg]

-120 -140 -160 -180 2 10

10

3

10

4

ω [rad / s] 1 0

5

Fig. 5. Open loop Bode diagram for the choice of regulator parameters according to SO

A common procedure for the determination of regulator parameters is Symmetrical Optimum (SO) [5]. To have maximum phase margin the gain of regulator should be:

D. Sampling methods and bandwidth of digital current control loop Control loop bandwidth will be used to benchmark the performance of digital current control loops with different sampling methods. The bandwidth is directly dependent on delays in the system lumped into time constant T2 (11). The results of the analysis are summarized in Table I, with typical delays in current feedback loop arranged into three groups: (a) Averager and Symmetric PWM (SPWM) with update rate once per carrier period Tcarr. (b) Synchronous Sampling (SS) and SPWM with update rate once per carrier period Tcarr. (c) SS and Asymmetric PWM (APWM) with update time 0.5Tcarr (or update rate twice per carrier).

TABLE I. Kr =

1 T1 , (a ≈ 2.4). K p aT2

(16)

BANDWIDTH OF CURRENT CONTROL LOOPS WITH DIFFERENT SAMPLING METHODS AND DIFFERENT TYPES OF PWM (UPDATED ONCE AND TWICE PER CARRIER CYCLE)

The integral time constant is:

Tr = T1 = a 2 T2 , with a =

(a) Averager & SPWM

1 + cosψ sin ψ

(17)

where ψ is a phase margin. Factor a directly influences selection of time constant of regulator. It effects phase margin and damping of the system. To have damping factor D = 1 2 , factor a should be a ≈ 2.4. The cross over and bandwidth frequencies are:

ωc =

1 , aT2

fb =

1 1 , for a=2.4, f b = 151 2π aT2 . T2

(18)

Note that while the gains of the PI regulator from (13) and (16) are very similar, the TO time constants from (12) is substantially higher then the SO time constant from (17). Because of the smaller integral time constant for regulator adjusted according to SO the disturbance rejection (Udis in Fig. 4) is superior to a regulator adjusted according to TO. However, control loop adjustment according to SO has an overshoot of about 40% in its step response due to a zero in the nominator of close loop transfer function [5]. Apparently the optimum adjustment is a combination of these two methods

(b) SS & SPWM

(c) SS & APWM

Tµ p

Tcarr

Tcarr

0.5Tcarr

T fb

0.5Tcarr

0

0

T pwm

0.5Tcarr

0.5Tcarr

0.25Tcarr

T2

2 Tcarr

1.5 Tcarr

0.75 Tcarr

fb

≈ f carr / 27 .6

≈ f carr / 20.7

≈ f carr / 10.3

The last row of Table I relates achievable bandwidths to carrier frequency for various sampling and PWM methods. The achievable bandwidths are approximately 10 to 30 times smaller then the carrier frequency. Note that case (c) provides 27.6/10.3=2.7 times higher bandwidth than case (a), demonstrating clear advantages of synchronous sampling in the current feedback loop. However when sampling a discontinuous signal like motor voltage in an encoderless drive, option (a) does not have an alternative. Option (a) still provides very high bandwidth and has substantial advantages over systems where motor voltage is first filtered and then sampled.

07803-4070-1/97/$10.00 (c) 1997 IEEE

IV. EXPERIMENTAL RESULTS A. Synchronous sampling of instantaneous and locally averaged value of current The experimental results were obtained on a three phase VSC [6], with input line voltage of 460V, DC bus voltage of 750V, and rated line current of 180A. Input line reactor was 0.52mH, 2.28mΩ. The PWM carrier frequency was fcarr=5kHz. Actual current waveform (a) is shown in Fig. 6. The waveform (b) in Fig. 6 is the sampled version of (a), obtained at the output of the signal averager (Fig. 3(b)) and then clocked out from the DSP through a D/A converter. Note that the averaged signal (b) accurately represents the fundamental component of load current (a).

Figure 7 shows (a) actual waveform of load current, (b) the same signals sampled synchronously with carrier with sampling period Ts=Tcarr (points 1,3, 5 etc. in Fig. 1), and (c) current sampled by averager. Note small phase shift of 0.5Ts between instantaneous and averaged sampled current values (b) and (c) respectively. B. Bandwidth of current regulator with different sampling methods To evaluate the influence of sampling methods on the speed of responses of the regulators, three different sampling methods, (a) to (c) from Table 1 were implemented. White noise was added to the current command icmd in a synchronous reference frame. The command icmd, feedback current i, and error (icmd-i) were clocked out from the DSP through a D/A converter to the frequency response analyzer. Open and closed loop Bode plots were measured. The regulator parameters were adjusted according to (12) and (13) or according to TO method. Measurement results are summarized in the Table II for the three different sampling methods from Table I. The first row contains calculated bandwidth fb from (15). The measured open loop bandwidth fb_ol and the measured closed loop bandwidth fb_cl are given in rows 2 and 3 for comparison purposes. The open loop bandwidth fb_ol was measured at the point where the amplitude of the open loop response crossed zero. The close loop bandwidth fb_cl was measured when the phase of the close loop response was -45deg. A good agreement between the predicted (15) and the measured bandwidths can be seen at the zero crossing of open loop amplitude response. The measured bandwidth fb_cl is about 15% to 20% lower then fb_ol.

Fig. 6. Actual current (a) and current sampled using signal averager (b)

TABLE II. ESTIMATED fb AND MEASURED OPEN fb_ol AND CLOSED fb_cl LOOP BANDWIDTH FREQUENCIES

(a) Averager & SPWM

fb

≈ f carr / 20.7

(c) SS & APWM

≈ f carr / 10.3

= 181 Hz

= 242 Hz

= 485 Hz

f b _ ol

201 Hz

250 Hz

508 Hz

f b _ cl

165 Hz

199 Hz

411 Hz

at fcarr= 5 k H z

Fig. 7. Actual current (a), instantaneous synchronously sampled current (b) and (c) averaged and then sampled current

≈ f carr / 27 .6

(b) SS & SPWM

Figure 8 shows open loop responses with the current sampled at frequency of 10kHz - twice the rate of carrier with regulators adjusted according to (a) TO and (b) SO methods. The bandwidth with regulators adjusted according to TO was 508Hz, what is 12% higher then 452Hz, the value obtained

07803-4070-1/97/$10.00 (c) 1997 IEEE

X:508

Y:-0.0431 dB

Hz

25 dB

/div dB Mag

5 dB

-25 dB 64Hz

100Hz

1.664kHz X:508

Hz

Y:-114.797 deg

1.664kHz

(a) X:452

1.608kHz Y:-45.748 deg

25 dB

100Hz X:199

Hz

X:199

Hz

1.608kHz

(a) Y:-0.59264 dB

Y:-0.04288 dB

/div

dB Mag 5 dB /div

Hz

5 dB

dB Mag

100Hz

Phase 36 deg /div 100Hz

-25 dB

64Hz

100Hz

1.664kHz X:452

Hz

100Hz

8Hz

180 deg

1.608kHz Y:-45.521 deg

/div

Phase 36 deg /div

Y:-131.815 deg

36 deg

Phase

Y:-0.69023 dB

-180 deg 8Hz 64Hz

100Hz

(b)

1.664kHz

Fig. 8. Open loop responses with current sampled at frequency of 10kHz and regulators adjusted according to (a) “TO” and (b) “SO” methods.

with regulators adjusted according to SO. This result is in good agreement with theoretical result; from (15) and (18) it follows that that TO should give 9.3% higher bandwidth then SO method. The close loop frequency responses of the regulators adjusted according to TO with three different sampling methods from Tables I and II are given in Fig. 9. Note that the amplitudes of the closed loop responses are fairly flat with 3dB fall at frequencies three times higher than open loop bandwidths. At the same points the phases assume values close to -180deg. Apparently, the bandwidth frequency measured when amplitude falls to -3dB would be too high.

25 dB

100Hz X:165

Hz

X:165

Hz

(b)

1.608kHz

Y:-0.58189 dB

dB Mag 5 dB /div

Phase

36 deg 64Hz

180 deg

-180 deg

Hz

-180 deg 8Hz

25 dB

-25 dB

X:411

8Hz

180 deg

/div

180 deg

-180 deg

Hz

-25 dB

100Hz

8Hz

180 deg

1.608kHz Y:-44.987 deg

Phase 36 deg /div

-25 dB

X:411

dB Mag 5 dB /div

25 dB

-180 deg 8Hz

100Hz

(c)

1.608kHz

Fig. 9. Amplitude and phase closed loop responses with current synchronously sampled (a) twice per carrier (b) once per carrier and (c) current sampled using averager; carrier frequency was 5kH

07803-4070-1/97/$10.00 (c) 1997 IEEE

Figure 10 shows the step response of a synchronous reference frame current loop with sampling rate of 10kHz and carrier frequency 5kHz. A compromise adjustment of current regulator combining TO and SO methods was adopted in order to improve disturbance rejection with still acceptable overshot to the step change of reference. The proportional gain was set according to TO (13). Note that both methods give similar results for proportional gain, equations (13) and (16). The integral time constant was arbitrarily set to Tr=10T2, the value between results given by TO and SO methods, equations (12) and (17). Such an adjustment resulted in improved disturbance rejection and acceptable overshot of 20% to the step change of reference.

The solution with an averager enables sampling of the locally averaged value of an input signal over a carrier period. The averager introduces a delay of only one half of the carrier period into the feedback. It can be used for sampling of load current and PWM types of voltage signals. The bandwidth of the current control loop with such a feedback is 27.6 times smaller then the PWM carrier frequency. Synchronous sampling (synchronized with PWM carrier) of instantaneous value was used as the effective alternative in a current feedback loop. The achievable bandwidth with synchronously sampled current signal, with sampling and PWM update rate twice per carrier, is 10.3 times smaller than the carrier frequency. REFERENCES

e

i de

id_c

66A 200us

Fig. 10. Step response of synchronous reference frame current control loop; ied_c - reference current, ied - feedback current

V. CONCLUSION The achievable bandwidth of the current control loops in electrical drives is approximately 10 to 30 times smaller than the carrier frequency of the PWM. The bandwidth is a function of a processing speed and the delay in feedback signal. The delay in feedback depends on sampling methods. Two cost effective methods of sampling of instantaneous and locally averaged values of signals are presented and analyzed.

[1] T. Matsui, T. Okuyama, J. Takahashi, T. Sekegava, K. Kamiyama, “A High Accuracy Current Component Detection Method for Fully Digital, Vector - Controlled PWM VSI - Fed AC Drives’, pp. 877-884, PESC’ 88 Conference Record, Kyoto, Japan, April 11 -14, 1988. [2] T. Yamada, Y. Yamamoto, T. Kodama, T. Ichioka, ‘Advancement of Variable - Speed Technology,’ Meiden Review International Edition, No. 3, 1990, Series No. 90. [3] Vladimir Blasko, ‘A Hybrid PWM Strategy Combining Modified Space Vector and Triangle Comparison Methods’, Conf. Rec. of PESC-96 Ann. Mtg, pp. 1872 - 1878. June 23-27, 1996, Baveno - Italy. [4] John D. Miskin, “Charge balancing current sampler for digital motor control”, U. S. Patent Number 4,804,895, Allen Bradley Co., February 14, 1989. [5] W. Leonhard, ‘Introduction to Control Engineering and Linear Systems,’ Springer International Student Edition, Allied Publishers Private Limited, New Delhi. (The original German edition: ‘Einfuhrung in die Regelungstechnik’, at Verlag Friedrich VIWEG & Sohn, Braunschweig, Germany 1970). [6] V. Blasko and V. Kaura, ‘A Novel Control to Actively Damp Resonance in Input LC Filter of a Three Phase Voltage Source Converter‘, IEEE Transactions on Industry Applications, pp. 542 - 550, Vol. 33, No. 2, March/April 1997.

07803-4070-1/97/$10.00 (c) 1997 IEEE