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Sb–Se-Based Phase-Change Memory Device With Lower Power and Higher Speed Operations Sung-Min Yoon, Nam-Yeal Lee, Sang-Ouk Ryu, Kyu-Jeong Choi, Young-Sam Park, Seung-Yun Lee, Byoung-Gon Yu, Myung-Jin Kang, Se-Young Choi, and Matthis Wuttig
Abstract—A phase-change material of Sb65 Se35 was newly proposed for the nonvolatile memory applications. The fabricated phase-change memory device using Sb65 Se35 showed a good electrical threshold switching characteristic in the dc current–voltage (I–V ) measurement. The programming time for set operation of the memory device decreased from 1 µs to 250 ns when Sb65 Se35 was introduced in place of the conventionally employed Ge2 Sb2 Te5 (GST). The reset current of Sb65 Se35 device also dramatically reduced from 15 mA to 1.6 mA, compared with that of GST device. These results are attributed to the low melting temperature and high crystallization speed of Sb65 Se35 and will contribute to lower power and higher speed operations of a phase-change nonvolatile memory. Index Terms—Nonvolatile memory, phase-change random access memory (PRAM), phase transition, Sb–Se alloy.
I. I NTRODUCTION
T
HE CONCEPT of unified memory has newly appeared, which is equipped with almighty functions such as low power, high speed, robust endurability, and nonvolatility. Recently, the phase-change random access memory (PRAM) has been attracted much attention as one of the most promising candidates for the next-generation unified memory due to its excellent logic compatibility and scaling-favorable operation schemes [1]–[4]. However, for the realization of future higher density PRAM comparable to flash memory, two major concerns of lower power and higher speed operations should be totally investigated. In this viewpoint, the reductions of the current for a reset programming (Ireset ) and the required time for set programming (tset ) are available solutions, which can be achieved by employing a phase-change material with lower melting temperature (Tm ) and higher crystallization speed (tc ). So far, Ge2 Sb2 Te5 (GST) has been mainly employed for the fabrication of PRAM. Although the PRAM devices using GST have shown a kind of good functionalities in the prototype chips, the introduction of new material can help the realization of unified PRAM, since GST has a relatively high Tm of about 620 ◦ C. In this paper, for the first time, we fabricated the phaseManuscript received January 23, 2006; revised March 6, 2006. The review of this letter was arranged by Editor C.-P. Chang. S.-M. Yoon, N.-Y. Lee, S.-O. Ryu, K.-J. Choi, Y.-S. Park, S.-Y. Lee, and B.-G. Yu are with Basic Research Laboratory, Electronics and Telecommunications Research Institute (ETRI), Daejeon 305-700, Korea (e-mail:
[email protected]). M.-J. Kang and S.-Y. Choi are with the School of New Materials Science and Engineering, Yonsei University, Seoul 120-749, Korea. M. Wuttig is with the Physikalisches Institut der RWTH Aachen, Aachen D-52056, Germany. Digital Object Identifier 10.1109/LED.2006.874130
Fig. 1. Schematic diagram of a cross section of the fabricated device. The BEC size of a memory contact was defined to be 0.5 µm.
change device using a new chalcogenide material of antimony selenide (Sbx Se100−x ) alloy and examined its memory device feasibility. II. E XPERIMENTAL The fabrication procedures of the phase-change memory devices using Sbx Se100−x and GST are as follows. First, a bottom electrode contact (BEC) of TiN/TiW was formed on SiO2 /Si substrate, on which oxide (SiO2 ) insulation layer of 2000 Å was deposited by a plasma-enhanced chemical vapor deposition (PECVD) method at 400 ◦ C. Active pores for the contact between the phase-change material and the BEC were patterned into oxide layer, in which the contact size was defined to be 0.5 µm. Then, Sbx Se100−x or GST was deposited by simultaneous evaporation from Knudsen cells in an ultrahigh vacuum and RF magnetron sputtering method, respectively. The thickness of a deposited film was about 3000 Å. Each chalcogenide material was patterned by the dry-etching system using a high-density helicon plasma. The etching behavior details of GST films can be referred in our previous publication [5]. On these structures, oxide passivation layer was formed by electron cyclotron resonance chemical vapor deposition (ECRCVD) method, which was carried out at room temperature in order to avoid the surface oxidation and composition change of Sb–Se alloy or GST. Finally, top electrode contact (TEC) of W was formed after a via contact was patterned. Fig. 1 shows a schematic cross section of the fabricated device. The operation behaviors of the fabricated devices were characterized by the electrical measurement system, in which the voltage and current pulses for set and reset operations were provided by a programmable pulse generator (HP 8110A). The resistance across the memory device at each operation was measured by a semiconductor parameter analyzer (HP 4145B) via steady-state current–voltage (I–V ) tests in sampling mode.
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The current values described at device operations were read from the panel of HP 8110A. Although the absolute current values were not correctly calculated by an oscilloscope, we can compare the operation behaviors of the fabricated devices using different materials at the same measurement conditions. III. R ESULTS AND D ISCUSSIONS A. Antimony Selenide Phase-Change Material Sbx Se100−x has been also researched for the application of rewritable optical storage [6], [7]. It was known that this material system is a very attractive candidate for its low melting temperature and low thermal conductance. Especially, a lower Tm (about 540 ◦ C–560 ◦ C) of Sb–Se alloys than GST is a very beneficial factor for the phase-change devices. For the realization of the phase-change device using Sbx Se100−x , it is important to determine the optimum composition of x. In this paper, we have referred the results [8] that were previously performed in a series of experiments for Sbx Se100−x thin films (60 ≤ x ≤ 70). According to the obtained results, the crystallization temperatures (Tc ) of Sbx Se100−x decreased from 161 ◦ C to 122 ◦ C when the Sb composition x increased from 60 to 70. On the other hand, it was also found that the minimum required time for crystallization (tc ) of Sbx Se100−x films decreased as the increase of x, in which the values of tc were observed to be dependent on the composition x. The Tc of 122 ◦ C for Sb70 Se30 is supposed to be too low for the operation reliability, which may be related to the recrystallization phenomenon during data retention and the thermal crosstalk between the neighboring cells, even though Sb70 Se30 film shows the fastest tc among the examined samples. Therefore, we selected the composition x of 65 for the device fabrication, since Sb65 Se35 has a suitable Tc of 152 ◦ C and a sufficiently fast tc . It was also confirmed that the tc of Sb65 Se35 was much faster than that of GST prepared in this paper at the same measuring conditions. B. Memory Operations of the Phase-Change Devices The phase-change device utilizes the reversible phase change between crystalline and amorphous states of the chalcogenide materials. Information data are stored by resistive joule heating and can be readout nondestructively by measuring the cell’s electrical resistance, in which the crystalline phase cell (set) shows a lower resistance in comparison to the amorphous phase cell (reset). First, we confirmed the I–V behavior of the fabricated phase-change device using a proposed new material of Sb65 Se35 . A negative resistance region can be obviously observed, and the threshold voltage (Vth ) for the electronic switching appears at 1.65 V. Only after this threshold switching, the cell resistance can possibly decrease with the phase change of Sb65 Se35 from a high-resistance amorphous state to a lowresistance crystalline state by joule heating. It can be confirmed that the fabricated memory device has programming capability due to the phase change of Sb65 Se35 . By the way, the BEC size (0.5 µm) of the fabricated device is supposed to be still too big to anticipate the practical level device operations. Therefore, we made comparisons of operation behaviors between Sb65 Se35 and GST devices in
Fig. 2. Resistance variation of phase-change memory devices using GST (circle) and Sb65 Se35 (square) as a function of pulsewidth when the voltage pulse of 5 V was applied. White and black data sets for two devices correspond to reset and set operations, respectively.
order to examine the feasibility of the proposed new material. The required time values for programming were measured for reset (treset ) and set (tset ) operations as a function of applied pulsewidth when the amplitude of voltage pulse was fixed at 5 V. The cell resistance was determined by applying dc readout voltage of 1 V after each programming operation. The treset and tset of GST device were observed to be 50 ns and 1 µs, respectively, as shown in Fig. 2. On the other hand, the programming time performance of the Sb65 Se35 device much improved to 35 ns (treset ) and 250 ns (tset ). It is noticeable that the tset of Sb65 Se35 device decreased to 25% compared with that of GST device. This evidently suggests that the Sb65 Se35 device can operate with a higher speed than GST device, which is related to the faster tc of Sb65 Se35 than GST. The programming curves (R–I) for set operations were characterized when the programming current pulses with various amplitude were applied to the devices, as shown in insets of Fig. 3. The pulsewidth was so chosen as 1 µs to provide a sufficient time for set transitions. For the Sb65 Se35 and GST devices, the cell resistance transition from reset to set begins at 30 and 50 µA, respectively. It can be found that a little smaller current (Iset ) is required for Sb65 Se35 device for obtaining the same degree of set–reset margin. On the other hand, it is more important to reduce the Ireset for realizing the PRAM with a lower power consumption, since Ireset is much larger than Iset for the PRAM programming in general. Fig. 3 compares the R–I characteristics for reset operations between Sb65 Se35 and GST memory devices when the pulsewidth was set to be 100 ns. The Ireset decreased from 15 to 1.6 mA when the GST was replaced by Sb65 Se35 with the same device structure. The lower Tm and the lower thermal conductivity of Sb–Se alloy are mainly responsible for this dramatic reduction of Ireset for Sb65 Se35 device. While the thermal conductivity of GST (with hcp structure) is known as about 0.46 W/cm · K, that of Sb–Se alloy was reported to be about 0.2 W/cm · K (for Sb2 Se3 ) [9]. In the phase-change memory device, heat confinement within the programming volume is very important for a lower power operation [10]. We can expect that the generated heat is more effectively utilized for phase transition of Sb65 Se35 device.
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loy. It was confirmed that the fabricated device using Sb65 Se35 described a kind of memory operations with shorter tset and smaller Ireset , compared with the operation behaviors of the device using a conventional GST. From theses obtained results, we can conclude that Sb65 Se35 must be one of the most promising materials for the high-density PRAM with lower power and higher speed operations. R EFERENCES
Fig. 3. Reset programming curves (R–I) of the phase-change devices using (a) GST and (b) Sb65 Se35 when the current pulse with 100 ns was applied. Insets represent set programming curves (R–I) of devices using (a) GST and (b) Sb65 Se35 when the current pulse with 1 µs was applied.
Considering the decrement of Ireset , we cannot completely rule out the possibility that there is the third unknown factor. In relation to the obtained current level, the programming currents would be much smaller if we scale down the device size to the practical level, although the obtained Ireset of 1.6 mA is still too large to be applied to practical PRAM applications. IV. C ONCLUSION This is the first report on the fabrication of a phase-change nonvolatile memory device employing Sb–Se chalcogenide al-
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