EDM
2009 International Conference on Computers and Devices for Communication
Scaling Issues in Nanoscale Double Gate FinFETs with Source/Drain Underlap Tapas Dutta and Sudeb Dasgupta
Abstract— In this paper the various scaling issues related to underlap FinFET devices with channel lengths of 30 nm and fin widths of 10 nm have been investigated in detail through device simulations using the Sentaurus TCAD simulation package. The effects of scaling the gate length, the fin thickness, the gate insulator thickness, metal gate thickness and source/drain extension lengths have been examined. The impact of image force effect on the gate leakage is also studied. Quantum mechanical effects which become prominent in the nanometer regime have been included in the simulations for obtaining a realistic picture. Index Terms—Device Simulation, Double Gate, Scaling, Quantum Mechanical Effects, Underlap FinFETs.
velocity saturation effects in these high fields. The Lombardi model [9] was used to include the degradation of carrier mobility at the interfaces due to scattering by acoustic surface phonons and surface roughness. Dielectric Spacers
Tgate
Gate Insulator
Gate
Source
Drain
Tfin Lextn
I. INTRODUCTION One of the promising non-classical devices is the doublegate FinFET ([1], [2]). This is a self-aligned nanoscale structure having a vertical channel and has the ability to facilitate more aggressive geometrical scaling as we approach the sub-45 nm technology nodes [3]. Because of better gate control in FinFETs, the Short-channel effects are reduced as compared to a bulk MOSFET [4]. These devices have sharper subthreshold slopes which allows for better switching in the device. Also, the threshold voltage is controlled without the use of heavy channel doping, thereby eliminating the problematic random doping fluctuations and at the same time reducing the mobility degradation due to scattering and the drain to body BTBT leakage currents. Also, it has been reported [5] that gate-source/drain underlap is needed to yield optimally designed nanoscale FinFETs. II. SIMULATION METHODOLOGY The Sentaurus TCAD package was used for the 2D device simulations. Fig. 1 depicts the top view of the FinFET device. The parameters of the primary FinFET used in this study have been listed in Table I. The Old Slotboom model [6] for Bandgap narrowing was used to evaluate the effective intrinsic carrier concentration. In addition to the constant mobility model, Masetti’s Doping Dependent Mobility Model [7] was utilised to take into account scattering of the carriers by the charged dopant ions. Since the FinFET dimensions are sub–100 nm, the electric fields in the channel can be pretty high. The Extended Canali model based on [8] was incorporated to account for the
This research work was supported by the Special Manpower Development Program in VLSI & Related Softwares Phase-II (SMDP-II), Ministry of Communication and Information Technology (MCIT), Department of Science and Technology, Government of India under Project No. MIT-218-ECD. The authors are with the department of Electronics & Computer Engineering, Indian Institute of Technology Roorkee, India – 247667. (Email:
[email protected])
978-81-8465-152-2/09/$26.00©2009 CODEC
Lg
Lspacer
Figure 1. 2D FinFET structure TABLE I THE PRIMARY FINFET DEVICE PARAMETERS Device Parameter
Value
Gate Length(Lg)
30 nm
Fin Width (Tfin)
10 nm
Gate Oxide Thickness(tox)
1 nm
Gate Oxide
SiO2
Fin Doping(Nfin)
1015 cm-3
S/D Doping
1022 cm-3
Spacer Material
Si3N4
Spacer Thickness
15 nm
Total Underlap Length( Lextn )
25 nm
Metal Gate Workfunction
4.72 eV
Supply Voltage (VDD)
1V
Shockley–Read–Hall (SRH) recombination was used to consider recombinations through deep defect levels in the band gap. Phonon-assisted band-to-band tunnelling (BTBT) based on the Schenk model [10] was included. Also, direct tunnelling [11] along with a consideration for the image force effect was incorporated. The density gradient quantum transport model based on [12] was used for the device simulations.
III. SIMULATION RESULTS The effects of geometric scaling of the DG FinFET devices was investigated. This section presents analysis of the results obtained by simulation.
10
15
Ig, leak (A/μm)
3.85E-04 3.80E-04 3.75E-04 3.70E-04 3.65E-04 3.60E-04 3.55E-04
10000 6000 4000 2000 0 0
1
2 tox (nm)
3
Figure 3(a). Variation of Ion and Ion/Ioff ratio with tox
gm (S/μm)
15 10
3.40E-04 5
3.20E-04
0
3.00E-04 0
20
Tfin (nm)
1
2
tox (nm)
3
Figure 3(b). Variation of gm and DIBL ratio with tox
0.15 0.1 10
15
20
Ig,leak(A/μm)
0.2
66 1.00E-02 S (mV/dec)
67 66 65 64 63 62 61
0.25
5
Ion/Ioff
8000
Figure 2(a). Variation of Ion, Ioff and gm with Tfin
0
20
65.5
1.00E-05
65
1.00E-08
64.5
1.00E-11
64
1.00E-14
63.5 0
1
2
3
Tfin (nm)
tox (nm)
Figure 2(b). Variation of Vt and S with Tfin
Figure 3(c). Variation of Ig,leak and S with tox
S (mV/dec)
5
15
C. Gate Oxide Thickness (tox)Scaling As we decrease the gate length, the gate oxide thickness also needs to be reduced. In this section the oxide thickness was varied from 1 nm to 2.5 nm and its impact on the FinFET characteristics was studied. The on current, Ion/Ioff ratio and gate transconductance were found to increase with decreasing tox as depicted in Fig. 3(a) and Fig. 3(b). The subthreshold slope and DIBL were also found to improve as the oxide layer was made thinner, due to better gate control.
0.00E+00 0
10
Figure 2(c). Variation of gate leakage current with Tfin
3.60E-04
5.00E-08
5
Tfin (nm)
2.00E-07 1.00E-07
0.00E+00
1.20E-05
3.80E-04
1.50E-07
2.00E-04
Vt(V)
Ion (A/μm), gm
4.00E-04
1.40E-05
2.50E-07 Ioff (A/μm)
gm Ion Ioff
6.00E-04
1.60E-05
DIBL (mV/V)
B. Fin Thickness (Tfin) Scaling An overall performance improvement is observed as far as the short channel effects are concerned. Ioff, and S are found to decrease on reducing the fin thickness as can be seen from Fig. 2(a) and 2(b). The on current reduces (Fig. 2(a)) due to reduction in number of carriers in a thinner fin. The structural quantum confinement in the thin fin causes the minimum energy of electrons in the potential well to rise to non-zero values as the silicon fin becomes thinner. This effectively increases the threshold voltage of the device as carriers must now populate a higher energy subband [13]. The Vt variation is shown in Fig. 2(b). As the fin thickness decreases, the depletion charge goes on reducing, thereby decreasing the normal electric field from gate to channel. Consequently the gate leakage is reduced as depicted in Fig 2(c).
1.80E-05
0
Ion(A/μm)
A. Gate Length (Lg) Scaling Gate lengths were varied from 40 nm to 15 nm and the different parameters were extracted to see the effect of scaling. Both Ion, Ioff and the transconductance are found to increase with decreasing gate lengths, as they do in case of bulk MOSFETs, because of the increased longitudinal electric field. But the Ion/Ioff ratio degrades. The subthreshold swing (S) is found to worsen, indicating poorer switching behavior at shorter gate lengths. The threshold voltage was found to roll off and DIBL was seen to degrade by about 100% on reducing the gate length from 40 nm to 15 nm, because of the increased proximity of the source and drain regions.
2.00E-05
Ion (A/μm)
3.00E-04
5.50E-08 5.40E-08
2.00E-04
5.30E-08
1.00E-04
5.20E-08 5.10E-08
0.00E+00 0
10
20 30 40 Tgate (nm)
50
3.40E-04 3.30E-04 3.20E-04 3.10E-04 3.00E-04 2.90E-04 2.80E-04 2.70E-04
7500 6000 4500
Ion/Ioff
3000
gm
1500 0
1.00E-07
0
1.00E-11
10
20 30 40 Tgate (nm)
gm (S/μm)
Figure 5(a). Effect of scaling the gate thickness on Ion and Ioff
With Image Force Without Image Force
1.00E-03
4.00E-04
5.60E-08
Ioff (A/μm)
5.70E-08
50
Figure 5(b). Effect of scaling the gate thickness on Ion/Ioff and gm
1.00E-15 1.5 2 tox (nm)
2.5
3
Figure 4. Impact of image force effect on the gate leakage
E. Gate Thickness (Tgate) Scaling The impact of gate thickness is a relatively less explored area. Generally the minimum gate thickness allowed in current technologies is kept at a value equal to the gate length (Lg), but there are some published results [15] that mention fabrication of MOS devices with gates thinner than the gate length used. It can be seen from Fig. 5(a) and Fig. 5(b) that reducing the gate thickness results in decreased on currents and increased off currents and hence poorer Ion/Ioff ratio and transconductance. From Fig. 5(c) and 5(d), it can be observed that the other parameters, namely S, DIBL, Vt and gate leakage don’t change much, until the gate thickness is made very small. F. Effect of S/D Extension Region Scaling The effective channel length increases on increasing the extension region (underlap) length. This, in addition to the increased fin resistance results in a non-linear decrease of the on current. This effect is also visible in the increase of threshold voltage of the device. Off current is reduced due to the suppression of DIBL. Subthreshold slope is seen to improve while the gate leakage is reduced. Hence there is a
64.5
0.1615
Vt
64.4
0.161
S
64.3
0.1605
64.2
0.16
64.1
0.1595 0
10
20 30 40 Tgate (nm)
Vt(V)
1
50
Figure 5(c). Effect of scaling the gate thickness on S and Vt
10.6 10.4 10.2 10 9.8 9.6 9.4
1.73E-05 1.72E-05 1.72E-05 1.71E-05 1.71E-05
Ig,leak(A/μm)
0.5
DIBL (mV/V)
0
S (mV/dec)
Ig,leak(A/μm)
D. Impact of Image Force on Gate Leakage Simulations were carried out with and without the inclusion of the image force effect and the results are shown in Fig. 4. The gate leakage is increased when the image force effect is also accounted for. When an electron approaches a dielectric layer, it induces a positive charge on the interface which acts like an image charge within the layer [14]. This effect leads to a reduction of the barrier height for both electrons and holes. The conduction band bends downward and the valence band bends upward, respectively. The reduced barrier results in appreciable increase in current flow across the dielectric and hence, the image force effect can’t be neglected while considering gate leakages in FinFETs with ultra thin oxides.
trade-off between improved short channel behaviour and reduced drive current in devices with longer extension lengths. The simulation results have been shown in Fig. 6(a)-(c).
Ion/Ioff
But the main concern is the overwhelming increase in the gate leakage. The gate leakage current was found to increase exponentially with decreasing gate oxide thickness (showing a linear variation on the log scale in Fig. 3(c)). This is because of the exponential dependence of the tunneling probability on the oxide thickness, as can be calculated by applying the WKB approximation. The electric field across the SiO2 layer increases on reducing its thickness, and as a result the tunneling probability increases.
1.70E-05 0
10
20 30 40 Tgate (nm)
50
Figure 5(d). Effect of scaling the gate thickness on DIBL and gate leakage current
6.00E-04
8.00E-08 4.00E-04
6.00E-08 4.00E-08
2.00E-04
Ioff (A/μm)
Ion (A/μm)
1.00E-07
2.00E-08 0.00E+00
0.00E+00 0
10 20 Lextn (nm)
30
0.162 0.16 0.158 0.156 0.154 0.152 0.15 0.148
6.00E-04 5.00E-04 4.00E-04 3.00E-04 2.00E-04
0
10 20 Lextn (nm)
gm (S/μm)
Vt(V)
Figure 6(a). Change in Ion and Ioff with Lextn scaling
0.00E+00
[4] [5] [6] [7]
1.43E-05
66
1.43E-05 1.43E-05 1.42E-05
65
1.42E-05
64.5
1.42E-05 10 20 Lextn (nm)
[8]
Ig,leak(A/μm)
66.5
0
[2] [3]
30
65.5
REFERENCES [1]
1.00E-04
Figure 6(b). Effect of Lextn scaling on Vt and gm
S (mV/dec)
fin thickness reduction is necessary to improve the SCEs and gate leakages at small gate lengths. Though oxide thickness scaling results in better transistor characteristics, the gate leakage increases excessively. It was found that the image force effect plays an important role and its impact can’t be neglected while evaluating gate leakages as it can increase leakage currents by an order of magnitude. Scaling down of the gate thickness resulted in higher drive currents and lower off currents, but gate transconductance and subthreshold slope were found to degrade. Increasing the S/D extension lengths improved the SCEs and resulted in reduced leakage currents, but the on current was severely degraded on account of increased fin resistance. Hence suitable optimization of the extension lengths is needed for achieving desired operation.
30
Figure 6(c). Variation of S and Ig. leak with Lextn
IV. CONCLUSIONS A thorough analysis of the scaling issues in double gate underlap FinFET devices with gate lengths of 30 nm was carried out in this work using numerical simulations. It was found that gate length scaling severely degrades the device performance, reducing the Ion/Ioff ratio, causing Vt roll- off and increasing the DIBL and subthreshold slope. It was seen that
[9] [10] [11] [12] [13] [14]
[15]
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