Portions of this work are from the book, Digital Logic Design: An Embedded.
Systems Approach Using VHDL, by Peter J. Ashenden, published by Morgan.
Digital Logic Design. Chapter 4
24 April © 2007
Digital Logic Design: An Embedded Systems Approach Using VHDL Chapter 4 Sequential Basics
Portions of this work are from the book, Digital Logic Design: An Embedded Systems Approach Using VHDL, by Peter J. Ashenden, published by Morgan Kaufmann Publishers, Copyright 2007 Elsevier Inc. All rights reserved.
Sequential Basics
Sequential circuits
Outputs depend on current inputs and previous inputs Store state: an abstraction of the history of inputs
Usually governed by a periodic clock signal
Digital Logic Design. Chapter 4
KU EECS 140/141
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Digital Logic Design. Chapter 4
24 April © 2007
D-Flipflops
1-bit storage element We will treat it as a basic component
clk
D
Q
clk
D Q
Other kinds of flipflops
SR (set/reset), JK, T (toggle) Digital Logic Design. Chapter 4
3
Registers
Store a multi-bit encoded value
One D-flipflop per bit Stores a new value on each clock cycle
signal d, q: ...; ...
d(0)
q(0)
sensitivity list
D
Q
q(1)
clk
D
Q
…
…
…
d(n) clk
Digital Logic Design. Chapter 4
KU EECS 140/141
Q
clk
d(1)
reg: process (clk) is begin if rising_edge(clk) then q Total delay d_in
d_in
combinational circuit 1
combinational circuit 1
D clk
Q
combinational circuit 2
combinational circuit 2
combinational circuit 3
D
Q
clk
d_out
combinational circuit 3
D
Q
d_out
clk
clk
Clock period = max(Delay1, Delay2, Delay3) Total delay = 3 × clock period Interval between outputs = 1 clock period Digital Logic Design. Chapter 4
5
Pipeline Example
Compute the average of corresponding numbers in three input streams
New values arrive on each clock edge
library ieee; use ieee.std_logic_1164.all, ieee.fixed_pkg.all; entity average_pipeline is port ( clk : in std_logic; a, b, c : in sfixed(5 downto -8); avg : out sfixed(5 downto -8) ); end entity average_pipeline;
Digital Logic Design. Chapter 4
KU EECS 140/141
6
3
Digital Logic Design. Chapter 4
24 April © 2007
Pipeline Example architecture rtl of average_pipeline is signal a_plus_b, sum, sum_div_3 : sfixed(5 downto -8); signal saved_a_plus_b, saved_c, saved_sum : sfixed(5 downto -8); begin a_plus_b > 0 64
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Digital Logic Design. Chapter 4
24 April © 2007
Synchronizers asynch_in
D
Q
D
clk
Q
synch_in
clk
clk
If input changes outside setup/hold window
If input changes during setup/hold window
Change is simply delayed by one cycle First flipflop has a whole cycle to resolve metastability
See data sheets for metastability parameters Digital Logic Design. Chapter 4
65
Switch Inputs and Debouncing
Switches and push-buttons suffer from contact bounce
Takes up to 10ms to settle
Need to debounce to avoid false triggering +V
R
S
Q
Requires two inputs and two resistors Must use a breakbefore-make doublethrow switch
Digital Logic Design. Chapter 4
KU EECS 140/141
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Digital Logic Design. Chapter 4
24 April © 2007
Switch Inputs and Debouncing
Alternative
+V
Use a single-throw switch Sample input at intervals longer than bounce time Look for two successive samples with the same value
Assumption
Extra circuitry inside the chip is cheaper than extra components and connections outside
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Debouncing in VHDL library ieee; use ieee.std_logic_1164.all; entity debouncer is port ( clk, reset : in std_logic; -- clk frequency = 50MHz pb : in std_logic; pb_debounced : out std_logic ); end entity debouncer;
architecture rtl of debouncer is signal count500000 : integer range 0 to 499999; signal clk_100Hz : std_logic; signal pb_sampled : std_logic; begin
Digital Logic Design. Chapter 4
KU EECS 140/141
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Digital Logic Design. Chapter 4
24 April © 2007
Debouncing in VHDL div_100Hz : process (clk, reset) is begin if reset = '1' then clk_100Hz
